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* [FastISel][AArch64] Fold bit test and branch into TBZ and TBNZ.Juergen Ributzka2014-09-181-8/+32
| | | | | | | Teach selectBranch to fold bit test and branch into a single instruction (TBZ or TBNZ). llvm-svn: 218010
* [FastISel][AArch64] Custom lower sdiv by power-of-2.Juergen Ributzka2014-09-171-0/+72
| | | | | | | | | Emit an optimized instruction sequence for sdiv by power-of-2 depending on the exact flag. This fixes rdar://problem/18224511. llvm-svn: 217986
* [FastISel][AArch64] Simplify mul to shift when possible.Juergen Ributzka2014-09-171-12/+48
| | | | | | This is related to rdar://problem/18369687. llvm-svn: 217980
* [FastISel][AArch64] Fold mul into add/sub and logical operations.Juergen Ributzka2014-09-171-19/+69
| | | | | | | | | Try to fold the multiply into the add/sub or logical operations (when possible). This is related to rdar://problem/18369687. llvm-svn: 217978
* [FastISel][AArch64] Fold mul into the address computation of memory operations.Juergen Ributzka2014-09-171-0/+70
| | | | | | | | | Teach 'computeAddress' to also fold multiplies into the address computation (when possible). This fixes rdar://problem/18369443. llvm-svn: 217977
* [FastISel][AArch64] Fold compare with zero and branch into CBZ and CBNZ.Juergen Ributzka2014-09-171-0/+64
| | | | | | | | | This takes advanatage of the CBZ and CBNZ instruction to further optimize the common null check pattern into a single instruction. This is related to rdar://problem/18358882. llvm-svn: 217972
* [FastISel][AArch64] Improve branch selection to support all FP conditions.Juergen Ributzka2014-09-171-10/+48
| | | | | | | | | | | | This adds the last two missing floating-point condition codes (FCMP_UEQ and FCMP_ONE) also to the branch selection. In these two cases an additonal branch instruction is required. This also adds unit tests to checks all the different condition codes. This is related o rdar://problem/18358882. llvm-svn: 217966
* [FastISel][AArch64] Add vector support to argument lowering.Juergen Ributzka2014-09-161-42/+44
| | | | | | Lower the first 8 vector arguments too. llvm-svn: 217850
* [FastISel][AArch64] Allow handling of vectors during return lowering for ↵Juergen Ributzka2014-09-151-2/+7
| | | | | | | | | | little endian machines. Allow handling of vectors during return lowering at least for little endian machines. This was restricted in r208200 to fix it for big endian machines (according to the comment), but it also disabled it for little endian too. llvm-svn: 217846
* [FastISel][AArch64] Update function and variable names to follow the coding ↵Juergen Ributzka2014-09-151-164/+162
| | | | | | standard. NFC. llvm-svn: 217845
* [FastISel][AArch64] Make AArch64FastISel class final. NFC.Juergen Ributzka2014-09-151-1/+1
| | | | llvm-svn: 217840
* [FastISel][AArch64] Lower sin/cos/pow to runtime lib calls.Juergen Ributzka2014-09-151-0/+50
| | | | | | | | Also lower sin/cos/pow to runtime lib calls. This fixes rdar://problem/18343468. llvm-svn: 217839
* [FastISel][AArch64] Add lowering support for frem.Juergen Ributzka2014-09-151-1/+44
| | | | | | | | | | | This lowers frem to a runtime libcall inside fast-isel. The test case also checks the CallLoweringInfo bug that was exposed by this change. This fixes rdar://problem/18342783. llvm-svn: 217833
* [FastISel][AArch64] Refactor selectAddSub, selectLogicalOp, and SelectShift. ↵Juergen Ributzka2014-09-151-27/+41
| | | | | | | | NFC. Small refactor to tidy up the code a little. llvm-svn: 217827
* [FastISel][AArch64] Refactor code to use isTypeSupported. NFC.Juergen Ributzka2014-09-151-19/+6
| | | | | | Gets rid of isLoadStoreTypeLegal and replace it with isTypeSupported. llvm-svn: 217826
* [FastISel][AArch64] Improve floating-point compare support.Juergen Ributzka2014-09-151-7/+62
| | | | | | | | Add support for the last two missing fcmp condition codes: UEQ and ONE. This fixes rdar://problem/18341575. llvm-svn: 217823
* [FastISel][AArch64] Add support for non-native types for logical ops.Juergen Ributzka2014-09-131-36/+48
| | | | | | | | | Extend the logical ops selection to also support non-native types such as i1, i8, and i16. Fixes rdar://problem/18330589. llvm-svn: 217732
* [AArch 64] Use a constant pool load for weak symbol references whenAsiri Rathnayake2014-09-101-0/+3
| | | | | | | | | | | | | | using static relocation model and small code model. Summary: currently we generate GOT based relocations for weak symbol references regardless of the underlying relocation model. This should be change so that in static relocation model we use a constant pool load instead. Patch from: Keith Walker Reviewers: Renato Golin, Tim Northover llvm-svn: 217503
* [FastISel][AArch64] Cleanup and simplify 'fastSelectInstruction'. NFC.Juergen Ributzka2014-09-041-75/+12
| | | | llvm-svn: 217119
* [FastISel][AArch64] Add target-specific lowering for logical operations.Juergen Ributzka2014-09-041-26/+163
| | | | | | | | | This change adds support for immediate and shift-left folding into logical operations. This fixes rdar://problem/18223183. llvm-svn: 217118
* [FastISel][tblgen] Rename tblgen generated FastISel functions. NFC.Juergen Ributzka2014-09-031-33/+33
| | | | | | | | | | This is the final round of renaming. This changes tblgen to emit lower-case function names for FastEmitInst_* and FastEmit_*, and updates all its uses in the source code. Reviewed by Eric llvm-svn: 217075
* [FastISel] Rename public visible FastISel functions. NFC.Juergen Ributzka2014-09-031-43/+43
| | | | | | | | | | | | | | | | | | | | | This commit renames the following public FastISel functions: LowerArguments -> lowerArguments SelectInstruction -> selectInstruction TargetSelectInstruction -> fastSelectInstruction FastLowerArguments -> fastLowerArguments FastLowerCall -> fastLowerCall FastLowerIntrinsicCall -> fastLowerIntrinsicCall FastEmitZExtFromI1 -> fastEmitZExtFromI1 FastEmitBranch -> fastEmitBranch UpdateValueMap -> updateValueMap TargetMaterializeConstant -> fastMaterializeConstant TargetMaterializeAlloca -> fastMaterializeAlloca TargetMaterializeFloatZero -> fastMaterializeFloatZero LowerCallTo -> lowerCallTo Reviewed by Eric llvm-svn: 217074
* [FastISel] Some long overdue spring cleaning of FastISel.Juergen Ributzka2014-09-031-30/+30
| | | | | | | | | | | | | Things got a little bit messy over the years and it is time for a little bit spring cleaning. This first commit is focused on the FastISel base class itself. It doxyfies all comments, C++11fies the code where it makes sense, renames internal methods to adhere to the coding standard, and clang-formats the files. Reviewed by Eric llvm-svn: 217060
* [FastISel][AArch64] Move unconditional branch handling into 'SelectBranch'. NFC.Juergen Ributzka2014-09-031-9/+7
| | | | llvm-svn: 217054
* [FastISel][AArch64] Add target-dependent instruction selection for Add/Sub.Juergen Ributzka2014-09-031-187/+164
| | | | | | | | | | | There is already target-dependent instruction selection support for Adds/Subs to support compares and the intrinsics with overflow check. This takes advantage of the existing infrastructure to also support Add/Sub, which allows the folding of immediates, sign-/zero-extends, and shifts. This fixes rdar://problem/18207316. llvm-svn: 217007
* [FastISel][AArch64] Use the target-dependent selection code for shifts first.Juergen Ributzka2014-09-021-6/+6
| | | | | | | | | | | | This uses the target-dependent selection code for shifts first, which allows us to create better code for shifts with immediates and sign-/zero-extend folding. Vector type are not handled yet and the code falls back to target-independent instruction selection for these cases. This fixes rdar://problem/17907920. llvm-svn: 216985
* [FastISel][AArch64] Use a new helper function to determine if a value type ↵Juergen Ributzka2014-09-021-6/+25
| | | | | | | | | | | | is supported. NFCI. FastISel for AArch64 supports more value types than are actually legal. Use a dedicated helper function to reflect this. It is very similar to the isLoadStoreTypeLegal function, with the exception that vector types are not supported yet. llvm-svn: 216984
* [FastISel][AArch64] Move over to target-dependent instruction selection only.Juergen Ributzka2014-09-021-41/+133
| | | | | | | | | | | This change moves FastISel for AArch64 to target-dependent instruction selection only. This change replicates the existing target-independent behavior, therefore there are no changes to the unit tests or new tests. Future changes will take advantage of this change and update functionality and unit tests. llvm-svn: 216955
* [FastISel][AArch64] Use the correct register class for branches.Juergen Ributzka2014-08-291-7/+9
| | | | | | | | Also constrain the register class for branches. This fixes rdar://problem/18181496. llvm-svn: 216804
* [FastISel][AArch64] Fix an incorrect kill flag due to a bug in SelectTrunc.Juergen Ributzka2014-08-291-6/+13
| | | | | | | | | | | | | | | | | | | | When we select a trunc instruction we don't emit any code if the type is already i32 or smaller. This is because the instruction that uses the truncated value will deal with it. This behavior can incorrectly transfer a kill flag, which was meant for the result of the truncate, onto the source register. %2 = trunc i32 %1 to i16 ... = ... %2 -> ... = ... vreg1 <kill> ... = ... %1 ... = ... vreg1 This commit fixes this by emitting a COPY instruction, so that the result and source register are distinct virtual registers. This fixes rdar://problem/18178188. llvm-svn: 216750
* [FastISel][AArch64] Don't fold instructions that are not in the same basic ↵Juergen Ributzka2014-08-291-23/+38
| | | | | | | | | | | | | | | block. This fix checks first if the instruction to be folded (e.g. sign-/zero-extend, or shift) is in the same machine basic block as the instruction we are folding into. Not doing so can result in incorrect code, because the value might not be live-out of the basic block, where the value is defined. This fixes rdar://problem/18169495. llvm-svn: 216700
* Revert "[FastISel][AArch64] Don't fold instructions too aggressively into ↵Juergen Ributzka2014-08-271-92/+16
| | | | | | | | the memory operation." Quentin pointed out that this is not the correct approach and there is a better and easier solution. llvm-svn: 216632
* [FastISel][AArch64] Don't fold instructions too aggressively into the memory ↵Juergen Ributzka2014-08-271-16/+92
| | | | | | | | | | | | | | | | | | | | | operation. Currently instructions are folded very aggressively into the memory operation, which can lead to the use of killed operands: %vreg1<def> = ADDXri %vreg0<kill>, 2 %vreg2<def> = LDRBBui %vreg0, 2 ... = ... %vreg1 ... This usually happens when the result is also used by another non-memory instruction in the same basic block, or any instruction in another basic block. If the computed address is used by only memory operations in the same basic block, then it is safe to fold them. This is because all memory operations will fold the address computation and the original computation will never be emitted. This fixes rdar://problem/18142857. llvm-svn: 216629
* [FastISel][AArch64] Fix a comment in my previous commit (r216617).Juergen Ributzka2014-08-271-1/+1
| | | | llvm-svn: 216622
* [FastISel][AArch64] Fix simplify address when the address comes from a shift.Juergen Ributzka2014-08-271-0/+4
| | | | | | | | | When the address comes directly from a shift instruction then the address computation cannot be folded into the memory instruction, because the zero register is not available as a base register. Simplify addess needs to emit the shift instruction and use the result as base register. llvm-svn: 216621
* [FastISel][AArch64] Use the zero register for stores.Juergen Ributzka2014-08-271-5/+19
| | | | | | | | | Use the zero register directly when possible to avoid an unnecessary register copy and a wasted register at -O0. This also uses integer stores to store a positive floating-point zero. This saves us from materializing the positive zero in a register and then storing it. llvm-svn: 216617
* [FastISel][AArch64] Fix address simplification.Juergen Ributzka2014-08-271-8/+103
| | | | | | | | | | | | When a shift with extension or an add with shift and extension cannot be folded into the memory operation, then the address calculation has to be materialized separately. While doing so the code forgot to consider a possible sign-/zero- extension. This fix folds now also the sign-/zero-extension into the add or shift instruction which is used to materialize the address. This fixes rdar://problem/18141718. llvm-svn: 216511
* [FastISel][AArch64] Fold Sign-/Zero-Extend into the shift immediate instruction.Juergen Ributzka2014-08-271-55/+249
| | | | llvm-svn: 216510
* [FastISel][AArch64] Refactor float zero materialization. NFCI.Juergen Ributzka2014-08-251-20/+29
| | | | llvm-svn: 216403
* [FastISel][AArch64] Add support for variable shift.Juergen Ributzka2014-08-211-32/+141
| | | | | | | | This adds the missing variable shift support for value type i8, i16, and i32. This fixes <rdar://problem/18095685>. llvm-svn: 216242
* [FastISel][AArch64] Use the correct register class to make the MI verifier ↵Juergen Ributzka2014-08-211-135/+140
| | | | | | | | | | | | | | | happy. This is mostly achieved by providing the correct register class manually, because getRegClassFor always returns the GPR*AllRegClass for MVT::i32 and MVT::i64. Also cleanup the code to use the FastEmitInst_* method whenever possible. This makes sure that the operands' register class is properly constrained. For all the remaining cases this adds the missing constrainOperandRegClass calls for each operand. llvm-svn: 216225
* [FastISel][AArch64] Factor out ANDWri instruction generation into a helper ↵Juergen Ributzka2014-08-211-42/+50
| | | | | | function. NFCI. llvm-svn: 216199
* [FastISel][AArch64] Don't fold the sign-/zero-extend from i1 into the compare.Juergen Ributzka2014-08-201-7/+20
| | | | | | | | | | This fixes a bug I introduced in a previous commit (r216033). Sign-/Zero- extension from i1 cannot be folded into the ADDS/SUBS instructions. Instead both operands have to be sign-/zero-extended with separate instructions. Related to <rdar://problem/17913111>. llvm-svn: 216073
* Silencing an MSVC C4334 warning ('<<' : result of 32-bit shift implicitly ↵Aaron Ballman2014-08-201-1/+1
| | | | | | converted to 64 bits (was 64-bit shift intended?)). NFC. llvm-svn: 216067
* [FastISel][AArch64] Use the proper FMOV instruction to materialize a +0.0.Juergen Ributzka2014-08-201-1/+1
| | | | | | | | | | Use FMOVWSr/FMOVXDr instead of FMOVSr/FMOVDr, which have the proper register class to be used with the zero register. This makes the MachineInstruction verifier happy again. This is related to <rdar://problem/18027157>. llvm-svn: 216040
* [FastISel][AArch64] Factor out ADDS/SUBS instruction emission and add ↵Juergen Ributzka2014-08-191-224/+397
| | | | | | | | | | | | | support for extensions and shift folding. Factor out the ADDS/SUBS instruction emission code into helper functions and make the helper functions more clever to support most of the different ADDS/SUBS instructions the architecture support. This includes better immedediate support, shift folding, and sign-/zero-extend folding. This fixes <rdar://problem/17913111>. llvm-svn: 216033
* Reapply [FastISel][AArch64] Add support for more addressing modes (r215597).Juergen Ributzka2014-08-191-168/+289
| | | | | | | | | | | | | | | | | | | | | Note: This was originally reverted to track down a buildbot error. Reapply without any modifications. Original commit message: FastISel didn't take much advantage of the different addressing modes available to it on AArch64. This commit allows the ComputeAddress method to recognize more addressing modes that allows shifts and sign-/zero-extensions to be folded into the memory operation itself. For Example: lsl x1, x1, #3 --> ldr x0, [x0, x1, lsl #3] ldr x0, [x0, x1] sxtw x1, w1 lsl x1, x1, #3 --> ldr x0, [x0, x1, sxtw #3] ldr x0, [x0, x1] llvm-svn: 216013
* Reapply [FastISel][AArch64] Make use of the zero register when possible ↵Juergen Ributzka2014-08-191-1/+13
| | | | | | | | | | | | | | | | (r215591). Note: This was originally reverted to track down a buildbot error. Reapply without any modifications. Original commit message: This change materializes now the value "0" from the zero register. The zero register can be folded by several instruction, so no materialization is need at all. Fixes <rdar://problem/17924413>. llvm-svn: 216009
* [FastISel][AArch64] Fix a few BuildMI callsites where the result register ↵Juergen Ributzka2014-08-191-8/+5
| | | | | | | | | | | | was added as an operand register. This fixes a few BuildMI callsites where the result register was added by using addReg, which is per default a use and therefore an operand register. Also use the zero register as result register when emitting a compare instruction (SUBS with unused result register). llvm-svn: 215997
* [FastISel][AArch64] Fix a latent bug in floating-point materialization.Juergen Ributzka2014-08-151-1/+10
| | | | | | | | | | | | | | | | | | | | | | The floating-point value positive zero (+0.0) is a valid immedate value according to isFPImmLegal. As a result AArch64 FastISel went ahead and used the immediate version of fmov to materialize the constant. The problem is that the immediate version of fmov cannot encode an imediate for postive zero. Instead a fmov from the zero register was supposed to be used in this case. This fix adds handling for this special case and uses fmov from the zero register to materialize a positive zero (negative zeroes go to the constant pool). There is no test case for this, because this code is currently dead. It will be enabled in a future commit and I will add a test case in a separate commit after that. This fixes <rdar://problem/18027157>. llvm-svn: 215753
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