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* Make PrintAsmOperand call to the superclass to handle 'n' and 'c' operand ↵Richard Barton2013-11-081-6/+2
| | | | | | modifiers. llvm-svn: 194270
* AArch64: use default asm operand printing when modifier inapplicableTim Northover2013-11-041-47/+59
| | | | | | | | | | | | If an inline assembly operand has multiple constraints (e.g. "Ir" for immediate or register) and an operand modifier (E.g. "w" for "print register as wN") then we need to decide behaviour when the modifier doesn't apply to the constraint. Previousely produced some combination of an assertion failure and a fatal error. GCC's behaviour appears to be to ignore the modifier and print the operand in the default way. This patch should implement that. llvm-svn: 194024
* Add a helper getSymbol to AsmPrinter.Rafael Espindola2013-10-291-1/+1
| | | | llvm-svn: 193627
* AArch64: add 'a' inline asm operand modifierTim Northover2013-10-291-0/+2
| | | | | | | This is used in the Linux kernel, and effectively just means "print an address". llvm-svn: 193593
* AArch64: use RegisterOperand for NEON registers.Tim Northover2013-09-131-19/+7
| | | | | | | | | | | | | | | | Previously we modelled VPR128 and VPR64 as essentially identical register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias" sub-registers). This model is starting to cause significant problems for code generation, particularly writing EXTRACT/INSERT_SUBREG patterns for converting between the two. The change here switches to classifying VPR64 & VPR128 as RegisterOperands, which are essentially aliases for RegisterClasses with different parsing and printing behaviour. This fits almost exactly with their real status (VPR128 == FPR128 printed strangely, VPR64 == FPR64 printed strangely). llvm-svn: 190665
* Remove address spaces from MC.Rafael Espindola2013-07-021-1/+1
| | | | | | | | This is dead code since PIC16 was removed in 2010. The result was an odd mix, where some parts would carefully pass it along and others would assert it was zero (most of the object streamer for example). llvm-svn: 185436
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE ↵David Blaikie2013-06-161-40/+0
| | | | | | | | | | MachineInstrs Frame index handling is now target-agnostic, so delete the target hooks for creation & asm printing of target-specific addressing in DBG_VALUEs and any related functions. llvm-svn: 184067
* AArch64: remove ConstantIsland pass & put literals in separate section.Tim Northover2013-02-151-16/+0
| | | | | | | | This implements the review suggestion to simplify the AArch64 backend. If we later discover that we *really* need the extra complexity of the ConstantIslands pass for performance reasons it can be resurrected. llvm-svn: 175258
* Fix formatting in AArch64 backend.Tim Northover2013-02-051-2/+4
| | | | | | | | | | | This should fix three purely whitespace issues: + 80 column violations. + Tab characters. + TableGen brace placement. No functional changes. llvm-svn: 174370
* Add AArch64 as an experimental target.Tim Northover2013-01-311-0/+361
This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. llvm-svn: 174054
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