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path: root/llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
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* AArch64: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-131-1/+1
| | | | llvm-svn: 250216
* [AArch64] Register (existing) AArch64AdvSIMDScalar pass with LLVM pass manager.Chad Rosier2015-08-051-2/+13
| | | | | | | | | Summary: Among other things, this allows -print-after-all/-print-before-all to dump IR around this pass. IIRC, this pass is off by default, but it's still helpful when debugging. llvm-svn: 244056
* MachineInstr: Change return value of getOpcode() to unsigned.Matthias Braun2015-05-181-4/+4
| | | | | | | | | This was previously returning int. However there are no negative opcode numbers and more importantly this was needlessly different from MCInstrDesc::getOpcode() (which even is the value returned here) and SDValue::getOpcode()/SDNode::getOpcode(). llvm-svn: 237611
* This only needs TargetInstrInfo, not the specialized one.Eric Christopher2015-01-301-3/+3
| | | | llvm-svn: 227529
* Migrate AArch64 except for TTI and AsmPrinter away from getSubtargetImpl.Eric Christopher2015-01-281-3/+1
| | | | llvm-svn: 227293
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-1/+3
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* [AArch64] Extend the number of scalar instructions supported in the AdvSIMDChad Rosier2014-08-041-0/+6
| | | | | | | | | scalar integer instruction pass. This is a patch I had lying around from a few months ago. The pass is currently disabled by default, so nothing to interesting. llvm-svn: 214779
* Run sort_includes.py on the AArch64 backend.Benjamin Kramer2014-07-251-1/+1
| | | | | | No functionality change. llvm-svn: 213938
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-0/+387
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
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