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* LiveRegUnits: Rename accumulateBackward()->accumulate()Matthias Braun2017-07-071-1/+1
| | | | | | | | | Contrary to the stepForward()/stepBackward() method accumulate() doesn't have a direction as defs, uses and clobbers all have the same effect. Also improve the documentation comment. llvm-svn: 307351
* LiveRegUnits: Add accumulateBackward() functionMatthias Braun2017-01-211-31/+18
| | | | | | | | | | | | | | | | | | | Re-Commit r292543 with a fix for the situation when the chain end is MBB.end(). This function can be used to accumulate the set of all read and modified register in a sequence of instructions. Use this code in AArch64A57FPLoadBalancing::scavengeRegister() to prove the concept. - The AArch64A57LoadBalancing code is using a backwards analysis now which is irrespective of kill flags. This is the main motivation for this change. Differential Revision: http://reviews.llvm.org/D22082 llvm-svn: 292705
* Revert "LiveRegUnits: Add accumulateBackward() function"Matthias Braun2017-01-201-18/+32
| | | | | | | | This seems to be breaking some bots. This reverts commit r292543. llvm-svn: 292574
* LiveRegUnits: Add accumulateBackward() functionMatthias Braun2017-01-201-32/+18
| | | | | | | | | | | | | | | | This function can be used to accumulate the set of all read and modified register in a sequence of instructions. Use this code in AArch64A57FPLoadBalancing::scavengeRegister() to prove the concept. - The AArch64A57LoadBalancing code is using a backwards analysis now which is irrespective of kill flags. This is the main motivation for this change. Differential Revision: http://reviews.llvm.org/D22082 llvm-svn: 292543
* Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini2016-10-011-1/+1
| | | | llvm-svn: 283004
* MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, ↵Matthias Braun2016-08-251-1/+1
| | | | | | | | | | | | | compute it Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes that no vregs are used in a machine function. With that we can simply compute the property and do not need to dump/parse it in .mir files. Differential Revision: http://reviews.llvm.org/D23850 llvm-svn: 279698
* [AArch64] Register passes so they can be run by llcDiana Picus2016-08-011-4/+0
| | | | | | | | | | | | | | Initialize all AArch64-specific passes in the TargetMachine so they can be run by llc. This can lead to conflicts in opt with some command line options that share the same name as the pass, so I took this opportunity to do some cleanups: * rename all relevant command line options from "aarch64-blah" to "aarch64-enable-blah" and update the tests accordingly * run clang-format on their declarations * move all these declarations to a common place (the TargetMachine) as opposed to having them scattered around (AArch64BranchRelaxation and AArch64AddressTypePromotion were the only offenders) llvm-svn: 277322
* AArch64: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-081-12/+10
| | | | | | | | Avoid implicit conversions from MachineInstrBundleInstr to MachineInstr* in the AArch64 backend, mainly by preferring MachineInstr& over MachineInstr* when a pointer isn't nullable. llvm-svn: 274924
* AArch64: Do not test for CPUs, use SubtargetFeaturesMatthias Braun2016-06-021-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Testing for specific CPUs has a number of problems, better use subtarget features: - When some tweak is added for a specific CPU it is often desirable for the next version of that CPU as well, yet we often forget to add it. - It is hard to keep track of checks scattered around the target code; Declaring all target specifics together with the CPU in the tablegen file is a clear representation. - Subtarget features can be tweaked from the command line. To discourage people from using CPU checks in the future I removed the isCortexXX(), isCyclone(), ... functions. I added an getProcFamily() function for exceptional circumstances but made it clear in the comment that usage is discouraged. Reformat feature list in AArch64.td to have 1 feature per line in alphabetical order to simplify merging and sorting for out of tree tweaks. No functional change intended. Differential Revision: http://reviews.llvm.org/D20762 llvm-svn: 271555
* Add optimization bisect opt-in calls for AArch64 passesAndrew Kaylor2016-04-251-0/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D19394 llvm-svn: 267479
* [NFC] Header cleanupMehdi Amini2016-04-181-1/+0
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* RegisterScavenger: Take a reference as enterBasicBlock() argument.Matthias Braun2016-04-061-1/+1
| | | | | | | Make it obvious that the argument cannot be nullptr. Remove an unnecessary nullptr check in initRegState. llvm-svn: 265511
* Add MachineFunctionProperty checks for AllVRegsAllocated for target passesDerek Schuff2016-04-041-0/+5
| | | | | | | | | | | | | | Summary: This adds the same checks that were added in r264593 to all target-specific passes that run after register allocation. Reviewers: qcolombet Subscribers: jyknight, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18525 llvm-svn: 265313
* [AArch64] Slight cleanup in FPLoadBalancingJames Molloy2016-02-261-2/+1
| | | | | | | | Instead of the convoluted if-statment we can just use getColor. This also fixes a bug where we relied upon the parity of tablegen-generated register indexes (instead of using the machine encoding). llvm-svn: 261990
* Delete trailing whitespace; NFCJunmo Park2016-01-061-4/+4
| | | | llvm-svn: 256906
* MachineRegisterInfo: Remove UsedPhysReg infrastructureMatthias Braun2015-07-141-1/+0
| | | | | | | | | | | | | We have a detailed def/use lists for every physical register in MachineRegisterInfo anyway, so there is little use in maintaining an additional bitset of which ones are used. Removing it frees us from extra book keeping. This simplifies VirtRegMap. Differential Revision: http://reviews.llvm.org/D10911 llvm-svn: 242173
* Fix a bug in the A57FPLoadBalancing register tracking/scavenger.Chad Rosier2015-07-061-3/+11
| | | | | | | | | | | | The code in AArch64A57FPLoadBalancing::scavengeRegister() to handle dead defs was not correctly handling aliased registers. E.g. if the dead def was of D2, then S2 was not being marked as unavailable, so it could potentially be used across a live-range in which it would be clobbered. Patch by Geoff Berry <gberry@codeaurora.org>! Phabricator: http://reviews.llvm.org/D10900 llvm-svn: 241449
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-231-1/+1
| | | | | | Apparently, the style needs to be agreed upon first. llvm-svn: 240390
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-191-1/+1
| | | | | | | | | | | | | The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! llvm-svn: 240137
* unique_ptrs are unique already, no need to unique them any further.Benjamin Kramer2015-03-131-8/+7
| | | | llvm-svn: 232178
* Remove subtarget dependence in pass pipeline setup for AArch64.Eric Christopher2015-03-031-0/+5
| | | | llvm-svn: 231165
* Rewrite MachineOperand::print and MachineInstr::print to avoidEric Christopher2015-02-271-3/+3
| | | | | | | | | | | | uses of TM->getSubtargetImpl and propagate to all calls. This could be a debugging regression in places where we had a TargetMachine and/or MachineFunction but don't have it as part of the MachineInstr. Fixing this would require passing a MachineFunction/Function down through the print operator, but none of the existing uses in tree seem to do this. llvm-svn: 230710
* [AArch64] Make AArch64A57FPLoadBalancing output stable.Chad Rosier2015-01-301-2/+9
| | | | | | | | | | | | | Add tie breaker to colorChainSet() sort so that processing order doesn't depend on std::set order, which depends on pointer order, which is unstable from run to run. No test case as this is nearly impossible to reproduce. Phabricator Review: http://reviews.llvm.org/D7265 Patch by Geoff Berry <gberry@codeaurora.org>! llvm-svn: 227606
* Clean up some uses of getSubtarget in AArch64.Eric Christopher2015-01-301-3/+0
| | | | llvm-svn: 227530
* [AArch64] Add INITIALIZE_PASS macros to AArch64A57FPLoadBalancing.Chad Rosier2015-01-291-1/+15
| | | | | | | | | | These are needed so this pass will produce output when e.g. -print-after-all is used. Phabricator Review: http://reviews.llvm.org/D7264 Patch by Geoff Berry <gberry@codeaurora.org>! llvm-svn: 227506
* [cleanup] Re-sort all the #include lines in LLVM usingChandler Carruth2015-01-141-1/+1
| | | | | | | | | | | utils/sort_includes.py. I clearly haven't done this in a while, so more changed than usual. This even uncovered a missing include from the InstrProf library that I've added. No functionality changed here, just mechanical cleanup of the include order. llvm-svn: 225974
* [AArch64] Fix clobber computation in A57LoadBalancing pass.Chad Rosier2014-11-241-1/+7
| | | | | | | Extremely difficult to reproduce, so no test case included. PR21637 llvm-svn: 222677
* Eliminate some deep std::vector copies. NFC.Benjamin Kramer2014-10-031-2/+2
| | | | llvm-svn: 218999
* [A57FPLoadBalancing] Modify r217689 - actually we do need to check defsJames Molloy2014-09-141-6/+6
| | | | | | | | ... Just make sure we check uses first so we see the kill first. It turns out ignoring defs gives some pretty nasty runtime failures. I'm certain this is the fix but I'm still reducing a testcase. llvm-svn: 217735
* [A57FPLoadBalancing] Remove support for vector typesJames Molloy2014-09-121-5/+0
| | | | | | | | Vector MUL/MLAs have tied operands, which gives us extra constraints that we currently can't handle. Instead of silently doing the wrong thing, remove support to be readded later properly. llvm-svn: 217690
* [A57FPLoadBalancing] Ignore <def>s when checking if a chain may be killed.James Molloy2014-09-121-0/+4
| | | | | | | | Defs are seen before uses, so a def without the kill flag doesn't necessarily mean that the register is not killed on that instruction. It may be killed in a later use operand. llvm-svn: 217689
* [A57LoadBalancing] unique_ptr-ify.James Molloy2014-09-121-25/+20
| | | | | | Thanks to David Blakie for the in-depth review! llvm-svn: 217682
* [AArch64] FPLoadBalancing: move ownership of the chain to its current ↵Arnaud A. de Grandmaison2014-08-291-5/+14
| | | | | | | | | | | | | | | | | accumulator register and forget about the previously used accumulator. Coming up with a simple testcase is not easy, as this highly depends on what the register allocator is doing: this issue showed up while working with the PBQP allocator, which produced a different allocation scheme. A testcase would need to come up with chain starting in D[0-7], then moving to D[8-15], followed by a call to a function whose regmask clobbers the starting accumulator in D[0-7], then another use of the chain. Fixed some formatting, added some invariant checks while there. llvm-svn: 216721
* Change the return value of "getEnd()" from a MachineInstr* to a ↵James Molloy2014-08-261-1/+1
| | | | | | | | MachineBasicBlock::iterator. It seems on Darwin the illegal round-trip ::iterator -> MachineInstr* -> ::iterator breaks execution horribly when the iterator is not a real MachineInstr, like ::end(). llvm-svn: 216455
* AArch64: avoid deleting the current iterator in a loop.Tim Northover2014-08-081-3/+4
| | | | | | | | std::map invalidates the iterator to any element that gets deleted, which means we can't increment it correctly afterwards. This was causing Darwin test failures. llvm-svn: 215233
* AArch64A57FPLoadBalancing.cpp: Define ColorNames in !NDEBUG.NAKAMURA Takumi2014-08-081-0/+2
| | | | llvm-svn: 215226
* [AArch64] Add an FP load balancing pass for Cortex-A57James Molloy2014-08-081-0/+694
For best-case performance on Cortex-A57, we should try to use a balanced mix of odd and even D-registers when performing a critical sequence of independent, non-quadword FP/ASIMD floating-point multiply or multiply-accumulate operations. This pass attempts to detect situations where the register allocation may adversely affect this load balancing and to change the registers used so as to better utilize the CPU. Ideally we'd just take each multiply or multiply-accumulate in turn and allocate it alternating even or odd registers. However, multiply-accumulates are most efficiently performed in the same functional unit as their accumulation operand. Therefore this pass tries to find maximal sequences ("Chains") of multiply-accumulates linked via their accumulation operand, and assign them all the same "color" (oddness/evenness). This optimization affects S-register and D-register floating point multiplies and FMADD/FMAs, as well as vector (floating point only) muls and FMADD/FMA. Q register instructions (and 128-bit vector instructions) are not affected. llvm-svn: 215199
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