summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Support/TargetParser.cpp
Commit message (Collapse)AuthorAgeFilesLines
* [NFC] Fixes -Wrange-loop-analysis warningsMark de Wever2020-01-011-4/+4
| | | | | | This avoids new warnings due to D68912 adds -Wrange-loop-analysis to -Wall. Differential Revision: https://reviews.llvm.org/D71857
* [AMDGPU] gfx908 targetStanislav Mekhanoshin2019-07-091-1/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D64429 llvm-svn: 365525
* [AMDGPU] gfx1011/gfx1012 targetsStanislav Mekhanoshin2019-06-141-1/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D63307 llvm-svn: 363344
* [AMDGPU] Add gfx1010 target definitionsStanislav Mekhanoshin2019-04-241-18/+20
| | | | | | Differential Revision: https://reviews.llvm.org/D61041 llvm-svn: 359113
* AMDGPU: Partially fix default device for HSAMatt Arsenault2019-03-171-4/+6
| | | | | | | | | | | | | | | | | | There are a few different issues, mostly stemming from using generation based checks for anything instead of subtarget features. Stop adding flat-address-space as a feature for HSA, as it should only be a device property. This was incorrectly allowing flat instructions to select for SI. Increase the default generation for HSA to avoid the encoding error when emitting objects. This has some other side effects from various checks which probably should be separate subtarget features (in the cost model and for dealing with the DS offset folding issue). Partial fix for bug 41070. It should probably be an error to try using amdhsa without flat support. llvm-svn: 356347
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* Fix build error due to missing cctype includeDavid Spickett2018-11-281-1/+0
| | | | | | in ARMTargetParser.cpp. llvm-svn: 347762
* [ARM, AArch64] Move ARM/AArch64 target parsers intoDavid Spickett2018-11-281-931/+0
| | | | | | | | | | | | | | | | | separate files to enable future changes. This moves ARM and AArch64 target parsing into their own files. They are still accessible through TargetParser.h as before. Several functions in AArch64 which were just forwarders to ARM have been removed. All except AArch64::getFPUName were unused, and that was only used in a test. Which itself was overlapping one in ARM, so it has also been removed. Differential revision: https://reviews.llvm.org/D53980 llvm-svn: 347741
* [AMDGPU] Defined gfx909 Raven Ridge 2Tim Renouf2018-10-241-1/+3
| | | | | | | Differential Revision: https://reviews.llvm.org/D53418 Change-Id: Ie3d054f2e956c2768988c0f4c0ffd29a47294eef llvm-svn: 345120
* [ARM/AArch64][v8.5A] Add Armv8.5-A targetOliver Stannard2018-09-261-0/+5
| | | | | | | | | | | | | This patch allows targeting Armv8.5-A, adding the architecture to tablegen and setting the options to be identical to Armv8.4-A for the time being. Subsequent patches will add support for the different features included in the Armv8.5-A Reference Manual. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52470 llvm-svn: 343102
* AMDGPU: Re-apply r341982 after fixing the layering issueKonstantin Zhuravlyov2018-09-121-10/+40
| | | | | | | | | | | | Move isa version determination into TargetParser. Also switch away from target features to CPU string when determining isa version. This fixes an issue when we output wrong isa version in the object code when features of a particular CPU are altered (i.e. gfx902 w/o xnack used to result in gfx900). llvm-svn: 342069
* Revert "AMDGPU: Move isa version and EF_AMDGPU_MACH_* determination into ↵Ilya Biryukov2018-09-121-128/+10
| | | | | | | | | | | TargetParser." This reverts commit r341982. The change introduced a layering violation. Reverting to unbreak our integrate. llvm-svn: 342023
* AMDGPU: Move isa version and EF_AMDGPU_MACH_* determinationKonstantin Zhuravlyov2018-09-111-10/+128
| | | | | | | | | | | | | | into TargetParser. Also switch away from target features to CPU string when determining isa version. This fixes an issue when we output wrong isa version in the object code when features of a particular CPU are altered (i.e. gfx902 w/o xnack used to result in gfx900). Differential Revision: https://reviews.llvm.org/D51890 llvm-svn: 341982
* Start reserving x18 by default on Android targets.Peter Collingbourne2018-08-291-1/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D45588 llvm-svn: 340889
* Try to fix bot build failureMatt Arsenault2018-08-211-1/+1
| | | | llvm-svn: 340296
* AMDGPU: Partially move target handling code from clang to TargetParserMatt Arsenault2018-08-211-0/+147
| | | | | | | | | | | | | | | | | | | | A future change in clang necessitates access of this information from the driver, so move this into a common place. Try to mimic something resembling the API the other targets are using here. One thing I'm uncertain about is how to split amdgcn and r600 handling. Here I've mostly duplicated the functions for each, while keeping the same enums. I think this is a bit awkward for the features which don't matter for amdgcn. It's also a bit messy that this isn't a complete set of subtarget features. This is just the minimum set needed for the driver code. For example building the list of subtarget feature names is still in clang. llvm-svn: 340291
* [ARM/AArch64] Support FP16 +fp16fml instructionsBernard Ogden2018-08-171-0/+7
| | | | | | | | | | | | | | | | | | Add +fp16fml feature for new FP16 instructions, which are a mandatory part of FP16 from v8.4-A and an optional part of FP16 from v8.2-A. It doesn't seem to be possible to model this in LLVM, but the relationship between the options is handled by the related clang patch. In keeping with what I think is the usual practice, the fp16fml extension is accepted regardless of base architecture version. Builds on/replaces Sjoerd Meijer's patch to add these instructions at https://reviews.llvm.org/D49839. Differential Revision: https://reviews.llvm.org/D50228 llvm-svn: 340013
* [AArch64] Armv8.2-A: add the crypto extensionsSjoerd Meijer2018-07-261-0/+11
| | | | | | | | | This adds MC support for the crypto instructions that were made optional extensions in Armv8.2-A (AArch64 only). Differential Revision: https://reviews.llvm.org/D49370 llvm-svn: 338010
* [ARM][AArch64] Armv8.4-A EnablementSjoerd Meijer2018-06-291-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initial patch adding assembly support for Armv8.4-A. Besides adding v8.4 as a supported architecture to the usual places, this also adds target features for the different crypto algorithms. Armv8.4-A introduced new crypto algorithms, made them optional, and allows different combinations: - none of the v8.4 crypto functions are supported, which is independent of the implementation of the Armv8.0 SHA1 and SHA2 instructions. - the v8.4 SHA512 and SHA3 support is implemented, in this case the Armv8.0 SHA1 and SHA2 instructions must also be implemented. - the v8.4 SM3 and SM4 support is implemented, which is independent of the implementation of the Armv8.0 SHA1 and SHA2 instructions. - all of the v8.4 crypto functions are supported, in this case the Armv8.0 SHA1 and SHA2 instructions must also be implemented. The v8.4 crypto instructions are added to AArch64 only, and not AArch32, and are made optional extensions to Armv8.2-A. The user-facing Clang options will map on these new target features, their naming will be compatible with GCC and added in follow-up patches. The Armv8.4-A instruction sets can be downloaded here: https://developer.arm.com/products/architecture/a-profile/exploration-tools Differential Revision: https://reviews.llvm.org/D48625 llvm-svn: 335953
* AArch64: Implement support for the shadowcallstack attribute.Peter Collingbourne2018-04-041-0/+4
| | | | | | | | | | | | The implementation of shadow call stack on aarch64 is quite different to the implementation on x86_64. Instead of reserving a segment register for the shadow call stack, we reserve the platform register, x18. Any function that spills lr to sp also spills it to the shadow call stack, a pointer to which is stored in x18. Differential Revision: https://reviews.llvm.org/D45239 llvm-svn: 329236
* [ARM] Add 'fillValidCPUArchList' to ARM targetsErich Keane2018-02-081-0/+14
| | | | | | | | | This is a support change for a CFE change (https://reviews.llvm.org/D42978) that allows march and -target-cpu to list the valid targets in a note. The changes are limited to the ARM/AArch64, since this is the only target that gets the CPU list from LLVM. llvm-svn: 324623
* [Support] Return an enum instead of an unsigned; NFC.George Burgess IV2018-01-171-2/+2
| | | | | | | | | | | | | | We seem to be (logically) returning ArchExtKinds here in all cases, so the return type should reflect that. The static_cast is necessary because `A.ID` is actually an `unsigned`, presumably since we use `decltype(A)` to represent extended attributes for both ARM and AArch64, which use distinct `ArchExtKinds`. We can't trivially make the same change for ARM, because one of the values it returns is the bitwise-or of two `ARM::ArchExtKind`s. llvm-svn: 322613
* [TargetParser] Add missing armv8l ARMv8 variant.Florian Hahn2018-01-091-1/+1
| | | | | | | | | | | | | | | | | | This change adds the missing armv8l variant as an alias of armv8 architecture. The issue was observed with several regressions in validation on armv8l hardware (for instance ExecutionEngine/frem.ll failed due to lack of neon fpu). Tested with regression testsuite passed without regression on ARM and x86_64. Patch by Yvan Roux. Reviewers: rengolin, rogfer01, olista01, fhahn Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D41859 llvm-svn: 322098
* [TargetParser] Check size before accessing architecture version.Florian Hahn2017-12-201-2/+2
| | | | | | | | | | | | | | | | | | Summary: This fixes a crash when invalid -march options like `armv` are provided. Based on a patch by Will Lovett. Reviewers: rengolin, samparker, mcrosier Reviewed By: samparker Subscribers: aemerson, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D41429 llvm-svn: 321166
* Silence a bunch of implicit fallthrough warningsAdrian Prantl2017-12-191-1/+0
| | | | llvm-svn: 321114
* Remove redundant includes from lib/Support.Michael Zolotukhin2017-12-131-1/+0
| | | | llvm-svn: 320627
* [TargetParser][AArch64] Add support for RDM feature in the target parser.Chad Rosier2017-08-241-0/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D37081 llvm-svn: 311659
* [ARM][AArch64] Cortex-A75 and Cortex-A55 supportSam Parker2017-08-211-0/+14
| | | | | | | | | | | | | | | | | | This patch introduces support for Cortex-A75 and Cortex-A55, Arm's latest big.LITTLE A-class cores. They implement the ARMv8.2-A architecture, including the cryptography and RAS extensions, plus the optional dot product extension. They also implement the RCpc AArch64 extension from ARMv8.3-A. Cortex-A75: https://developer.arm.com/products/processors/cortex-a/cortex-a75 Cortex-A55: https://developer.arm.com/products/processors/cortex-a/cortex-a55 Differential Revision: https://reviews.llvm.org/D36667 llvm-svn: 311316
* [ARM][AArch64] ARMv8.3-A enablementSam Parker2017-08-101-0/+5
| | | | | | | | | | | | | | | | | The beta ARMv8.3 ISA specifications have been released for AArch64 and AArch32, these can be found at: https://developer.arm.com/products/architecture/a-profile/exploration-tools An introduction to this architecture update can be found at: https://community.arm.com/processors/b/blog/posts/armv8-a-architecture-2016-additions This patch is the first in a series which will add ARM v8.3-A support in LLVM and Clang. It adds the necessary changes that create targets for both the ARM and AArch64 backends. Differential Revision: https://reviews.llvm.org/D36514 llvm-svn: 310561
* [TargetParser] Use enum classes for various ARM kind enums.Florian Hahn2017-07-271-156/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Using c++11 enum classes ensures that only valid enum values are used for ArchKind, ProfileKind, VersionKind and ISAKind. This removes the need for checks that the provided values map to a proper enum value, allows us to get rid of AK_LAST and prevents comparing values from different enums. It also removes a bunch of static_cast from unsigned to enum values and vice versa, at the cost of introducing static casts to access AArch64ARCHNames and ARMARCHNames by ArchKind. FPUKind and ArchExtKind are the only remaining old-style enum in TargetParser.h. I think it's beneficial to keep ArchExtKind as old-style enum, but FPUKind can be converted too, but this patch is quite big, so could do this in a follow-up patch. I could also split this patch up a bit, if people would prefer that. Reviewers: rengolin, javed.absar, chandlerc, rovka Reviewed By: rovka Subscribers: aemerson, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D35882 llvm-svn: 309287
* [AArch64] Add an SVE target feature to the backend and TargetParser.Amara Emerson2017-07-131-0/+2
| | | | | | | The feature will be used properly once assembler/disassembler support begins to land. llvm-svn: 307917
* Unified logic for computing target ABI in backend and front end by moving ↵Eric Christopher2017-06-301-0/+36
| | | | | | | | | | this common code to Support/TargetParser. Modeled Triple::GNU after front end code (aapcs abi) and updated tests that expect apcs abi. Based heavily on a patch by Ana Pazos! llvm-svn: 306768
* [AArch64] Fix variable name ambiguity in r302078.Ahmed Bougacha2017-05-031-2/+4
| | | | | | ArchKind is passed to the function, but it's also a type. llvm-svn: 302081
* [AArch64] Make the TargetParser add CPU exts provided by the arch.Ahmed Bougacha2017-05-031-1/+1
| | | | | | | | | | | | | | | | Otherwise, each CPU has to manually specify the extensions it supports, even though they have to be a superset of the base arch extensions. And when there's redundant data there's stale data, so most of the CPUs lie about the features they support (almost none lists AEK_FP). Instead, do the saner thing: add the optional extensions on top of the base extensions provided by the architecture. The ARM TargetParser has the same behavior. Differential Revision: https://reviews.llvm.org/D32780 llvm-svn: 302078
* [ARM] Rename HW div feature to HW div Thumb. NFCI.Diana Picus2017-04-201-1/+1
| | | | | | | | | | | | | | | | The hardware div feature refers only to Thumb, but because of its name it is tempting to use it to check for hardware division in general, which may cause problems in ARM mode. See https://reviews.llvm.org/D32005. This patch adds "Thumb" to its name, to make its scope clear. One notable place where I haven't made the change is in the feature flag (used with -mattr), which is still hwdiv. Changing it would also require changes in a lot of tests, including clang tests, and it doesn't seem like it's worth the effort. Differential Revision: https://reviews.llvm.org/D32160 llvm-svn: 300827
* [AArch64] Add Cavium ThunderX supportJoel Jones2017-02-171-0/+2
| | | | | | | | | | | | | | This set of patches adds support for Cavium ThunderX ARM64 processors: * ThunderX * ThunderX T81 * ThunderX T83 * ThunderX T88 Patch by Stefan Teleman Differential Revision: https://reviews.llvm.org/D28891 llvm-svn: 295475
* [ARM] Add support for armv7ve triple in llvm (PR31358).George Burgess IV2017-02-091-0/+2
| | | | | | | | | | | | | | | Gcc supports target armv7ve which is armv7-a with virtualization extensions. This change adds support for this in llvm for gcc compatibility. Also remove redundant FeatureHWDiv, FeatureHWDivARM for a few models as this is specified automatically by FeatureVirtualization. Patch by Manoj Gupta. Differential Revision: https://reviews.llvm.org/D29472 llvm-svn: 294661
* [ARM]: Add Cortex-R52 target to LLVMJaved Absar2016-10-071-0/+3
| | | | | | | This patch adds Cortex-R52, the new ARM real-time processor, to LLVM. Cortex-R52 implements the ARMv8-R architecture. llvm-svn: 283542
* Use StringReg in TargetParser APIs (NFC)Mehdi Amini2016-10-071-14/+14
| | | | llvm-svn: 283527
* Add unittests to {ARM | AArch64}TargetParser.Zijiao Ma2016-07-281-48/+51
| | | | | | | | | | | | | | Add unittest to {ARM | AArch64}TargetParser,and by the way correct problems as below: 1.Correct a incorrect indexing problem in AArch64TargetParser. The architecture enumeration is shared across ARM and AArch64 in original implementation.But In the code,I just used the index which was offset by the ARM, and this would index into the array incorrectly. To make AArch64 has its own arch enum,or we will do a lot of slowly iterating. 2.Correct a spelling error. The parameter of llvm::AArch64::getArchExtName. 3.Correct a writing mistake, in llvm::ARM::parseArchISA. Differential Revision: https://reviews.llvm.org/D21785 llvm-svn: 276957
* [AArch64] Add RAS extensions support in AArch64TargetParser.Zijiao Ma2016-06-131-0/+2
| | | | | | | RAS extensions are part of ARMv8.2,now supported in Clang. Add RAS extensions support in AArch64TargetParser. llvm-svn: 272533
* Support: correct AArch64 TargetParser implementationSaleem Abdulrasool2016-06-081-20/+21
| | | | | | | | | | | | | | | | | | | | | | | The architecture enumeration is shared across ARM and AArch64. However, the data is not. The code incorrectly would index into the array using the architecture index which was offset by the ARMv7 architecture enumeration. We do not have a marker for indicating the architectural family to which the enumeration belongs so we cannot be clever about offsetting the index (at least it is not immediately apparent to me). Instead, fall back to the tried-and-true method of slowly iterating the array (its not a large array, so the impact of this is not too high). Because of the incorrect indexing, if we were lucky, we would crash, but usually we would return an invalid StringRef. We did not have any tests for the AArch64 target parser previously;. Extend the previous tests I had added for ARM to cover AArch64 for ensuring that we return expected StringRefs. Take the opportunity to change some iterator types to references. This work is needed to support parsing `.arch name` directives in the AArch64 target asm parser. llvm-svn: 272145
* [AArch64] Adding a TargetParser for AArch64Renato Golin2016-05-251-0/+219
| | | | | | | | | | There's already a ARMTargetParser,now adding a similar one for aarch64. so we can use it to do ARCH/CPU/FPU parsing in clang and llvm, instead of string comparison. Patch by Jojo Ma. llvm-svn: 270687
* Support: catch invalid accessesSaleem Abdulrasool2016-03-051-2/+2
| | | | | | | | | | | It is possible to invoke these methods on an invalid input resulting in an invalid substring construction. It seems that we do not have unit tests for these methods. Tests to ensure that the invalid call is caught to follow in clang. Resolves PR26839. llvm-svn: 262778
* [ARM] Add ARMv8-M Baseline/Mainline LLVM targetingBradley Smith2016-01-151-0/+6
| | | | llvm-svn: 257878
* Reordering fields to reduce padding in LLVM. NFCBen Craig2015-12-141-4/+4
| | | | llvm-svn: 255554
* [ARM] Add ARMv8.2-A to TargetParserOliver Stannard2015-12-011-0/+3
| | | | | | | | | | | | Add ARMv8.2-A to TargetParser, so that it can be used by the clang command-line options and the .arch directive. Most testing of this will be done in clang, checking that the command-line options that this enables work. Differential Revision: http://reviews.llvm.org/D15037 llvm-svn: 254400
* Handle ARMv6-J as an alias, instead of fake architectureArtyom Skrobov2015-11-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | Summary: This follows D14577 to treat ARMv6-J as an alias for ARMv6, instead of an architecture in its own right. The functional change is that the default CPU when targeting ARMv6-J changes from arm1136j-s to arm1136jf-s, which is currently used as the default CPU for ARMv6; both are, in fact, ARMv6-J CPUs. The J-bit (Jazelle support) is irrelevant to LLVM, and it doesn't affect code generation, attributes, optimizations, or anything else, apart from selecting the default CPU. Reviewers: rengolin, logan, compnerd Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D14755 llvm-svn: 253675
* TargetParser.cpp: Fixup -- StringRef::startswith() is better here. NFC.NAKAMURA Takumi2015-11-191-1/+1
| | | | llvm-svn: 253570
* llvm/lib/Support/TargetParser.cpp: Rework llvm::ARM::getArchExtFeature() to ↵NAKAMURA Takumi2015-11-191-3/+7
| | | | | | avoid abuse of Twine in r253470. llvm-svn: 253566
OpenPOWER on IntegriCloud