| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fixed few warnings. | Galina Kistanova | 2012-07-12 | 1 | -5/+6 |
| | | | | | llvm-svn: 160142 | ||||
| * | The Mips specific function for instruction cache invalidation cannot be | Bruno Cardoso Lopes | 2011-10-10 | 1 | -34/+5 |
| | | | | | | | | | | compiled on mips32r1 processors because it uses synci and rdhwr instructions which are supported only on mips32r2, so I replaced this function with the call to function cacheflush which works for both mips32r1 and mips32r2. Patch by Sasa Stankovic llvm-svn: 141564 | ||||
| * | One more patch towards JIT support for Mips. | Bruno Cardoso Lopes | 2011-09-14 | 1 | -0/+35 |
| | | | | | | | | | | | | | | | - Add TSFlags for the instruction formats. The idea here is to use as much encoding as possible from getBinaryCodeForInstr, and having TSFLags formats for that would make it easier to encode most part of the instructions (since Mips encodings are pretty straightforward) - Improve the mips mechanism for compilation callback - Add Mips specific code for invalidating the instruction cache - Next patch will address wrong tablegen encoding Commit msg added by my own but the patch is from Sasa Stankovic. llvm-svn: 139688 | ||||
| * | Merge System into Support. | Michael J. Spencer | 2010-11-29 | 1 | -0/+74 |
| llvm-svn: 120298 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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