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* [X86] Remove the HLE feature flag.Craig Topper2017-02-091-1/+0
| | | | | | We only implemented it for one of the 3 HLE instructions and that instruction is also under the RTM flag. Clang only implements the RTM flag from its command line. llvm-svn: 294562
* [X86] Remove INVPCID and SMAP feature flags. They aren't currently used by ↵Craig Topper2017-02-091-2/+0
| | | | | | | | any instructions and not tested. If we implement intrinsics for their instructions in the future, the feature flags can be added back with proper testing. llvm-svn: 294561
* [X86] Clzero intrinsic and its addition under znver1Craig Topper2017-02-091-0/+4
| | | | | | | | | | | | | | | | | This patch does the following. 1. Adds an Intrinsic int_x86_clzero which works with __builtin_ia32_clzero 2. Identifies clzero feature using cpuid info. (Function:8000_0008, Checks if EBX[0]=1) 3. Adds the clzero feature under znver1 architecture. 4. The custom inserter is added in Lowering. 5. A testcase is added to check the intrinsic. 6. The clzero instruction is added to assembler test. Patch by Ganesh Gopalasubramanian with a couple formatting tweaks, a disassembler test, and using update_llc_test.py from me. Differential revision: https://reviews.llvm.org/D29385 llvm-svn: 294558
* [X86] Remove PCOMMIT instruction support since Intel has deprecated this ↵Craig Topper2017-02-081-1/+0
| | | | | | | | instruction with no plans to release products with it. Intel's documentation for the deprecation https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction llvm-svn: 294405
* AMD family 17h (znver1) enablementCraig Topper2017-01-101-0/+19
| | | | | | | | | | | | | | | | | | | | | | | Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This item is linked to clang review item https://reviews.llvm.org/D28018 Patch by Ganesh Gopalasubramanian Reviewers: RKSimon, craig.topper Subscribers: vprasad, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28017 llvm-svn: 291543
* [X86] Add Intel Kaby Lake model numbers to getHostCPUName aliased to ↵Craig Topper2017-01-051-2/+4
| | | | | | | | "skylake" since there are no feature differences. Model numbers found here http://www.sandpile.org/x86/cpuid.htm llvm-svn: 291086
* [X86] Change getHostCPUName to report Intel model 0x4e as "skylake" instead ↵Craig Topper2017-01-051-3/+11
| | | | | | | | | | | | | | | | | | | of "skylake-avx512". Add the proper 0x55 model for "skylake-avx512". Summary: Intel's i5-6300U CPU is reporting to have a model id of 78 (4e). The Host detection assumes that to be Skylake Xeon (with AVX512 support), instead of a normal Skylake machine. Patch by: Valentin Churavy Reviewers: nalimilan, craig.topper Subscribers: hfinkel, tkelman, craig.topper, nalimilan, llvm-commits Differential Revision: https://reviews.llvm.org/D28221 llvm-svn: 291084
* [PowerPC] Add identification for POWER8NVLNemanja Ivanovic2017-01-041-0/+1
| | | | | | | This CPU type was not previously recognized by LLVM which led to emitting poor (and sometimes incorrect) code in some JIT workloads on such a machine. llvm-svn: 290961
* Add computeHostNumPhysicalCores() implementation for DarwinMehdi Amini2016-10-191-0/+19
| | | | | | Differential Revision: https://reviews.llvm.org/D25800 llvm-svn: 284656
* Reduce global namespace pollution. NFC.Benjamin Kramer2016-10-181-2/+2
| | | | llvm-svn: 284521
* Add interface to compute number of physical cores on host systemTeresa Johnson2016-10-131-1/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: For now I have only added support for x86_64 Linux, but other systems can be added incrementally. This is to be used for setting the default parallelism for ThinLTO backends (instead of thread::hardware_concurrency which includes hyperthreading and is too aggressive). I'll send this as a follow-on patch, and it will fall back to hardware_concurrency when the new getHostNumPhysicalCores returns -1 (when not supported for a given host system). I also added an interface to MemoryBuffer to force reading a file as a stream - this is required for /proc/cpuinfo which is a special file that looks like a normal file but appears to have 0 size. The existing readers of this file in Host.cpp are reading the first 1024 or so bytes from it, because the necessary info is near the top. But for the new functionality we need to be able to read the entire file. I can go back and change the other readers to use the new getFileAsStream as a follow-on patch since it seems much more robust. Added a unittest. Reviewers: mehdi_amini Subscribers: beanz, mgorny, llvm-commits, modocache Differential Revision: https://reviews.llvm.org/D25564 llvm-svn: 284138
* [cpu-detection] Copy simplified version of get_cpuid_max to remove ↵Alina Sbirlea2016-10-041-5/+37
| | | | | | | | | | | | | | | | | dependency to clang's implementation Summary: Attempting to fix PR30384. Take the same approach as in compiler_rt and add a simplified version of __get_cpuid_max. Including cpuid.h is no longer needed. Reviewers: echristo, joerg Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D24597 llvm-svn: 283265
* Properly ifdef the use of cpuid.Alina Sbirlea2016-07-201-1/+6
| | | | llvm-svn: 276156
* [cpu-detection] Cleanup of Host.cpp.Alina Sbirlea2016-07-201-46/+48
| | | | | | | | | | | | | | Summary: Mirroring most cleanup changed from compiler-rt/lib/builtins/cpu_model. x86 methods are still returning a bool. Reviewers: llvm-commits, echristo, craig.topper, sanjoy Subscribers: mehdi_amini Differential Revision: https://reviews.llvm.org/D22480 llvm-svn: 276149
* [Support] Make helper function static. NFC.Benjamin Kramer2016-07-101-2/+2
| | | | llvm-svn: 275017
* Reapply 272328 and 272329 as a single patch.Alina Sbirlea2016-06-091-10/+3
| | | | | | | | | | | | | | | | | | | | [cpu-detection] [amdfam10] Return barcelona, and amdfam10 for all other subtypes. Address Bug 28067. Along with the refactoring of Host.cpp, getHostCPUName() was modified to return more precise types for CPUs in amdfam10. However, callers of getHostCPUName() do string matching on type, so this cannot be modified. Currently there is support in the x86 backend for barcelona. For all other subtypes the assumed return value is amdfam10. Fix: getHostCPUName() returns barcelona subtype and amdfam10 for all others. This can be extended further when support for the other subtypes is added. Differential revision: http://reviews.llvm.org/D21193 llvm-svn: 272333
* Revert 272328 and 272329 to recommit as a single patch.Alina Sbirlea2016-06-091-3/+10
| | | | llvm-svn: 272332
* Keep barcelona subtype for amdfam10Alina Sbirlea2016-06-091-1/+3
| | | | llvm-svn: 272329
* [cpu-detection] Return amdfam10 for all subtypes. Address Bug 28067.Alina Sbirlea2016-06-091-9/+0
| | | | | | | | | | | | Summary: Remove architecture subtype from the string returned by getHostCPUName(). String matching done on type. Reviewers: llvm-commits, echristo Subscribers: mehdi_amini Differential Revision: http://reviews.llvm.org/D21193 llvm-svn: 272328
* [cpu-detection] Add missing break statements in outer switchesAlina Sbirlea2016-06-091-6/+9
| | | | | | | | | | | | Summary: Break on all switch cases for outer and inner switches. No functionality changed. Reviewers: llvm-commits, sanjoy Differential Revision: http://reviews.llvm.org/D21158 llvm-svn: 272228
* [cpu-detection] Substantial refactor of Host CPU detection code (x86)Alina Sbirlea2016-06-061-261/+650
| | | | | | | | | | | | | | | | | | Summary: Following D20970 (committed as r271726). This is a substantial refactoring of the host CPU detection code. There is no functionality change intended, but the changes are extensive. Definitions of architecture types and subtypes are by no means exhaustive or perfectly defined, but a fair starting point. Suggestions for futher improvements are welcome. Reviewers: llvm-commits Differential Revision: http://reviews.llvm.org/D20988 llvm-svn: 271921
* [cpu-detection] Naming conventionAlina Sbirlea2016-06-031-28/+27
| | | | | | | | | | | | Summary: Follow-up to D20926 (committed as r271595, r271596). This patch is in preparation for a substantial refactoring of the code. No functionality changed. Differential Revision: http://reviews.llvm.org/D20970 llvm-svn: 271726
* 80-column fixup after last formatting change.Eric Christopher2016-06-021-4/+8
| | | | llvm-svn: 271598
* Fix a couple of misformatted comments spotted in post-commit review.Eric Christopher2016-06-021-8/+7
| | | | llvm-svn: 271596
* This patch is in preparation for a substantial refactoring of theEric Christopher2016-06-021-294/+304
| | | | | | | | | | | | code. To make the diffs easier to read, clang-format everything first. No functionality changed. Patch by Alina Sbirlea! http://reviews.llvm.org/D20926 llvm-svn: 271595
* Removing an unused variable introduced in r269911; NFC.Aaron Ballman2016-05-181-1/+0
| | | | llvm-svn: 269915
* Add new flag and intrinsic support for MWAITX and MONITORX instructionsAshutosh Nema2016-05-181-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: MONITORX/MWAITX instructions provide similar capability to the MONITOR/MWAIT pair while adding a timer function, such that another termination of the MWAITX instruction occurs when the timer expires. The presence of the MONITORX and MWAITX instructions is indicated by CPUID 8000_0001, ECX, bit 29. The MONITORX and MWAITX instructions are intercepted by the same bits that intercept MONITOR and MWAIT. MONITORX instruction establishes a range to be monitored. MWAITX instruction causes the processor to stop instruction execution and enter an implementation-dependent optimized state until occurrence of a class of events. Opcode of MONITORX instruction is "0F 01 FA". Opcode of MWAITX instruction is "0F 01 FB". These opcode information is used in adding tests for the disassembler. These instructions are enabled for AMD's bdver4 architecture. Patch by Ganesh Gopalasubramanian! Reviewers: echristo, craig.topper, RKSimon Subscribers: RKSimon, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D19795 llvm-svn: 269911
* [Power9] Add support for -mcpu=pwr9 in the back endNemanja Ivanovic2016-05-091-0/+1
| | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D19683 Simply adds the bits for being able to specify -mcpu=pwr9 to the back end. llvm-svn: 268950
* [Support][X86] Add a few more Intel model numbers to getHostCPUName for ↵Craig Topper2016-04-271-0/+4
| | | | | | airmont and knl. llvm-svn: 267670
* [Support][X86] Change the case values in the Intel family 6 code to hex so ↵Craig Topper2016-04-271-68/+66
| | | | | | its easier to compare with Intel's docs. NFC llvm-svn: 267669
* [Support][X86] Add a couple more Broadwell CPU models numbers to getHostCPUName.Craig Topper2016-04-271-0/+2
| | | | llvm-svn: 267666
* Revert "Fix Clang-tidy modernize-deprecated-headers warnings in remaining ↵Duncan P. N. Exon Smith2016-04-051-13/+11
| | | | | | | | | | files; other minor fixes." This reverts commit r265454 since it broke the build. E.g.: http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-incremental_build/22413/ llvm-svn: 265459
* Fix Clang-tidy modernize-deprecated-headers warnings in remaining files; ↵Eugene Zelenko2016-04-051-11/+13
| | | | | | | | | | | | other minor fixes. Some Include What You Use suggestions were used too. Use anonymous namespaces in source files. Differential revision: http://reviews.llvm.org/D18778 llvm-svn: 265454
* Fix LLVM's handling and detection of skylake and cannonlake CPUsSanjoy Das2016-02-211-0/+1
| | | | | | | | | | | | | | | | | Summary: - Rename `"skylake"` == SkylakeServerProc to `"skylake-avx512"` - Change `"skylake"` to denote SkylakeClientProc - Fix the detection of cpu family 6 and model 94 to be SkylakeClientProc instead of SkylakeServerProc - Remove the `"cnl"` for CannonLake Reviewers: craig.topper, delena Subscribers: zansari, echristo, qcolombet, RKSimon, spatel, DavidKreitzer, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17090 llvm-svn: 261482
* Added Skylake client to X86 targets and featuresElena Demikhovsky2016-01-241-3/+12
| | | | | | | | | | | | | Changes in X86.td: I set features of Intel processors in incremental form: IVB = SNB + X HSW = IVB + X .. I added Skylake client processor and defined it's features FeatureADX was missing on KNL Added some new features to appropriate processors SMAP, IFMA, PREFETCHWT1, VMFUNC and others Differential Revision: http://reviews.llvm.org/D16357 llvm-svn: 258659
* [AVX512] adding AVXVBMI feature flagMichael Zuckerman2016-01-181-1/+1
| | | | | | | | | Fixing wrong typo (avx515) → (avx512) Review over the shoulder by asaf . Differential Revision: http://reviews.llvm.org/D16190 llvm-svn: 258041
* [AVX512] adding AVXVBMI feature flagMichael Zuckerman2016-01-171-0/+1
| | | | | | | | | | The feature flag is for VPERMB,VPERMI2B,VPERMT2B and VPMULTISHIFTQB instructions. More about the instruction can be found in: hattps://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Differential Revision: http://reviews.llvm.org/D16190 llvm-svn: 258012
* [x86] adding PKU feature flagAsaf Badouh2015-12-151-0/+2
| | | | | | | | | the feature flag is essential for RDPKRU and WRPKRU instruction more about the instruction can be found in the SDM rev 56, vol 2 from http://www.intel.com/sdm Differential Revision: http://reviews.llvm.org/D15491 llvm-svn: 255644
* [X86] Update CPU detection to only enable XSAVE features if the OS has ↵Craig Topper2015-10-141-14/+16
| | | | | | enabled them and the saving of YMM state. This seems to be consistent with gcc behavior. llvm-svn: 250269
* [X86] Add XSAVE intrinsic familyAmjad Aboud2015-10-121-0/+9
| | | | | | | | | | | | Add intrinsics for the XSAVE instructions (XSAVE/XSAVE64/XRSTOR/XRSTOR64) XSAVEOPT instructions (XSAVEOPT/XSAVEOPT64) XSAVEC instructions (XSAVEC/XSAVEC64) XSAVES instructions (XSAVES/XSAVES64/XRSTORS/XRSTORS64) Differential Revision: http://reviews.llvm.org/D13012 llvm-svn: 250029
* [ADT] Switch a bunch of places in LLVM that were doing single-characterChandler Carruth2015-09-101-2/+2
| | | | | | | splits to actually use the single character split routine which does less work, and in a debug build is *substantially* faster. llvm-svn: 247245
* Add model numbers for Skylake CPUs and an additional Broadwell model.Craig Topper2015-08-081-0/+6
| | | | llvm-svn: 244385
* Add Intel family 6 model 93 as Silvermont.Craig Topper2015-08-081-0/+1
| | | | llvm-svn: 244384
* Add Intel family 6 model 90 as Silvermont. Fixes PR24392.Craig Topper2015-08-071-0/+1
| | | | llvm-svn: 244352
* [SystemZ] Add z13 vector facility and MC supportUlrich Weigand2015-05-051-0/+24
| | | | | | | | | | | | | | | | | | | | | This patch adds support for the z13 processor type and its vector facility, and adds MC support for all new instructions provided by that facilily. Apart from defining the new instructions, the main changes are: - Adding VR128, VR64 and VR32 register classes. - Making FP64 a subclass of VR64 and FP32 a subclass of VR32. - Adding a D(V,B) addressing mode for scatter/gather operations - Adding 1-, 2-, and 3-bit immediate operands for some 4-bit fields. Until now all immediate operands have been the same width as the underlying field (hence the assert->return change in decode[SU]ImmOperand). In addition, sys::getHostCPUName is extended to detect running natively on a z13 machine. Based on a patch by Richard Sandiford. llvm-svn: 236520
* [X86] Stop changing result of getHostCPUName based on whether the processor ↵Craig Topper2015-03-311-14/+5
| | | | | | supports AVX. getHostCPUFeatures should be used instead to determine whether to support AVX. llvm-svn: 233674
* [X86] Be more robust against unknown Intel family 6 models. Use feature ↵Craig Topper2015-03-311-10/+43
| | | | | | flags to guess what it might be. llvm-svn: 233671
* [X86] In getHostCPUFeatures, disable xop, f16c, fma, and fma4 if OS does not ↵Craig Topper2015-03-301-4/+4
| | | | | | support saving ymm state. llvm-svn: 233518
* [X86] Use the more specific CPU names like 'nehalem', 'westmere', 'haswell', ↵Craig Topper2015-03-301-12/+9
| | | | | | etc. Split Nehalem and Westmere CPUs. llvm-svn: 233516
* [X86] Move family 6 model 21 to 'pentium-m'. Near as I can tell this is a ↵Craig Topper2015-03-301-0/+2
| | | | | | Dothan based SOC. llvm-svn: 233515
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