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* [Support][X86] Add a few more Intel model numbers to getHostCPUName for ↵Craig Topper2016-04-271-0/+4
| | | | | | airmont and knl. llvm-svn: 267670
* [Support][X86] Change the case values in the Intel family 6 code to hex so ↵Craig Topper2016-04-271-68/+66
| | | | | | its easier to compare with Intel's docs. NFC llvm-svn: 267669
* [Support][X86] Add a couple more Broadwell CPU models numbers to getHostCPUName.Craig Topper2016-04-271-0/+2
| | | | llvm-svn: 267666
* Revert "Fix Clang-tidy modernize-deprecated-headers warnings in remaining ↵Duncan P. N. Exon Smith2016-04-051-13/+11
| | | | | | | | | | files; other minor fixes." This reverts commit r265454 since it broke the build. E.g.: http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-incremental_build/22413/ llvm-svn: 265459
* Fix Clang-tidy modernize-deprecated-headers warnings in remaining files; ↵Eugene Zelenko2016-04-051-11/+13
| | | | | | | | | | | | other minor fixes. Some Include What You Use suggestions were used too. Use anonymous namespaces in source files. Differential revision: http://reviews.llvm.org/D18778 llvm-svn: 265454
* Fix LLVM's handling and detection of skylake and cannonlake CPUsSanjoy Das2016-02-211-0/+1
| | | | | | | | | | | | | | | | | Summary: - Rename `"skylake"` == SkylakeServerProc to `"skylake-avx512"` - Change `"skylake"` to denote SkylakeClientProc - Fix the detection of cpu family 6 and model 94 to be SkylakeClientProc instead of SkylakeServerProc - Remove the `"cnl"` for CannonLake Reviewers: craig.topper, delena Subscribers: zansari, echristo, qcolombet, RKSimon, spatel, DavidKreitzer, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17090 llvm-svn: 261482
* Added Skylake client to X86 targets and featuresElena Demikhovsky2016-01-241-3/+12
| | | | | | | | | | | | | Changes in X86.td: I set features of Intel processors in incremental form: IVB = SNB + X HSW = IVB + X .. I added Skylake client processor and defined it's features FeatureADX was missing on KNL Added some new features to appropriate processors SMAP, IFMA, PREFETCHWT1, VMFUNC and others Differential Revision: http://reviews.llvm.org/D16357 llvm-svn: 258659
* [AVX512] adding AVXVBMI feature flagMichael Zuckerman2016-01-181-1/+1
| | | | | | | | | Fixing wrong typo (avx515) → (avx512) Review over the shoulder by asaf . Differential Revision: http://reviews.llvm.org/D16190 llvm-svn: 258041
* [AVX512] adding AVXVBMI feature flagMichael Zuckerman2016-01-171-0/+1
| | | | | | | | | | The feature flag is for VPERMB,VPERMI2B,VPERMT2B and VPMULTISHIFTQB instructions. More about the instruction can be found in: hattps://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Differential Revision: http://reviews.llvm.org/D16190 llvm-svn: 258012
* [x86] adding PKU feature flagAsaf Badouh2015-12-151-0/+2
| | | | | | | | | the feature flag is essential for RDPKRU and WRPKRU instruction more about the instruction can be found in the SDM rev 56, vol 2 from http://www.intel.com/sdm Differential Revision: http://reviews.llvm.org/D15491 llvm-svn: 255644
* [X86] Update CPU detection to only enable XSAVE features if the OS has ↵Craig Topper2015-10-141-14/+16
| | | | | | enabled them and the saving of YMM state. This seems to be consistent with gcc behavior. llvm-svn: 250269
* [X86] Add XSAVE intrinsic familyAmjad Aboud2015-10-121-0/+9
| | | | | | | | | | | | Add intrinsics for the XSAVE instructions (XSAVE/XSAVE64/XRSTOR/XRSTOR64) XSAVEOPT instructions (XSAVEOPT/XSAVEOPT64) XSAVEC instructions (XSAVEC/XSAVEC64) XSAVES instructions (XSAVES/XSAVES64/XRSTORS/XRSTORS64) Differential Revision: http://reviews.llvm.org/D13012 llvm-svn: 250029
* [ADT] Switch a bunch of places in LLVM that were doing single-characterChandler Carruth2015-09-101-2/+2
| | | | | | | splits to actually use the single character split routine which does less work, and in a debug build is *substantially* faster. llvm-svn: 247245
* Add model numbers for Skylake CPUs and an additional Broadwell model.Craig Topper2015-08-081-0/+6
| | | | llvm-svn: 244385
* Add Intel family 6 model 93 as Silvermont.Craig Topper2015-08-081-0/+1
| | | | llvm-svn: 244384
* Add Intel family 6 model 90 as Silvermont. Fixes PR24392.Craig Topper2015-08-071-0/+1
| | | | llvm-svn: 244352
* [SystemZ] Add z13 vector facility and MC supportUlrich Weigand2015-05-051-0/+24
| | | | | | | | | | | | | | | | | | | | | This patch adds support for the z13 processor type and its vector facility, and adds MC support for all new instructions provided by that facilily. Apart from defining the new instructions, the main changes are: - Adding VR128, VR64 and VR32 register classes. - Making FP64 a subclass of VR64 and FP32 a subclass of VR32. - Adding a D(V,B) addressing mode for scatter/gather operations - Adding 1-, 2-, and 3-bit immediate operands for some 4-bit fields. Until now all immediate operands have been the same width as the underlying field (hence the assert->return change in decode[SU]ImmOperand). In addition, sys::getHostCPUName is extended to detect running natively on a z13 machine. Based on a patch by Richard Sandiford. llvm-svn: 236520
* [X86] Stop changing result of getHostCPUName based on whether the processor ↵Craig Topper2015-03-311-14/+5
| | | | | | supports AVX. getHostCPUFeatures should be used instead to determine whether to support AVX. llvm-svn: 233674
* [X86] Be more robust against unknown Intel family 6 models. Use feature ↵Craig Topper2015-03-311-10/+43
| | | | | | flags to guess what it might be. llvm-svn: 233671
* [X86] In getHostCPUFeatures, disable xop, f16c, fma, and fma4 if OS does not ↵Craig Topper2015-03-301-4/+4
| | | | | | support saving ymm state. llvm-svn: 233518
* [X86] Use the more specific CPU names like 'nehalem', 'westmere', 'haswell', ↵Craig Topper2015-03-301-12/+9
| | | | | | etc. Split Nehalem and Westmere CPUs. llvm-svn: 233516
* [X86] Move family 6 model 21 to 'pentium-m'. Near as I can tell this is a ↵Craig Topper2015-03-301-0/+2
| | | | | | Dothan based SOC. llvm-svn: 233515
* [X86] Family 6 model 29 is a Penryn based processor not a Nehalem based ↵Craig Topper2015-03-301-2/+2
| | | | | | processor. llvm-svn: 233514
* Fix a variable name in MSVC specific part of rr233487.Craig Topper2015-03-291-2/+2
| | | | llvm-svn: 233488
* [X86] Implement getHostCPUFeatures for X86.Craig Topper2015-03-291-8/+93
| | | | | | Plan to use this as part of CPU 'native' support so we can stop picking a different CPU name if CPU doesn't support AVX or AVX2. llvm-svn: 233487
* Fix typo 'AVX too' instead of 'AVX2'Craig Topper2015-03-231-2/+2
| | | | llvm-svn: 232929
* [X86] Add one stepping of Broadwell to the CPU name autodetection for ↵Craig Topper2015-03-231-0/+6
| | | | | | march=native. llvm-svn: 232927
* We require MSVC 1800 as our minimum, so these checks can safely go away; NFC.Aaron Ballman2015-02-161-12/+7
| | | | llvm-svn: 229415
* Remove a debugging assert.Rafael Espindola2014-12-171-1/+0
| | | | | | Sorry for the noise, I have no idea how it survived to the final version. llvm-svn: 224414
* Fix the windows build.Rafael Espindola2014-12-171-0/+2
| | | | llvm-svn: 224412
* Refactor and simplify the code reading /proc/cpuinfo. NFC.Rafael Espindola2014-12-171-47/+32
| | | | llvm-svn: 224410
* Remove StringMap::GetOrCreateValue in favor of StringMap::insertDavid Blaikie2014-11-191-2/+2
| | | | | | | | | | | | | | Having two ways to do this doesn't seem terribly helpful and consistently using the insert version (which we already has) seems like it'll make the code easier to understand to anyone working with standard data structures. (I also updated many references to the Entry's key and value to use first() and second instead of getKey{Data,Length,} and get/setValue - for similar consistency) Also removes the GetOrCreateValue functions so there's less surface area to StringMap to fix/improve/change/accommodate move semantics, etc. llvm-svn: 222319
* Add support for ppc64/power8 as a hostWill Schmidt2014-06-261-0/+2
| | | | llvm-svn: 211781
* Fix .cpp files claiming to be header filesHans Wennborg2014-06-201-1/+1
| | | | llvm-svn: 211334
* Fix typosAlp Toker2014-05-311-1/+1
| | | | llvm-svn: 209982
* Fixup sys::getHostCPUFeatures crypto names so it doesn't clash with kernel ↵Bradley Smith2014-05-231-9/+9
| | | | | | headers llvm-svn: 209506
* Extend sys::getHostCPUFeatures to work on AArch64 platformsBradley Smith2014-05-221-1/+37
| | | | llvm-svn: 209420
* Select bdver2 instead of bdver1 if TBM support is present on models < 0x10.Kaelyn Takata2014-05-051-1/+2
| | | | | | | | | | Tested that the right -target-cpu is set in the clang -cc1 command line when running "clang -march=native -E -v - </dev/null" on both an FX-8150 and an FX-8350. Both are family 15h; the FX-8150 (Bulldozer processor) reports a model number of 1, and the FX-8350 (Piledriver processor) reports a model number of 2. llvm-svn: 207973
* Add a description for AMD's bdver4 (aka Excavator).Benjamin Kramer2014-05-021-0/+2
| | | | | | This is just bdver3 + AVX2 + BMI2. llvm-svn: 207847
* [Modules] Followup to r206822 to add a DEBUG_TYPE which is used on ARMChandler Carruth2014-04-211-0/+2
| | | | | | and PPC, but not x86. llvm-svn: 206830
* Add support for krait cpu in llvm::sys::getHostCPUName()Kai Nacke2013-12-201-0/+11
| | | | | | | Recently, support for krait cpu was added. This commit extends getHostCPUName() to return krait as cpu for the APQ8064 (a Krait 300). llvm-svn: 197792
* Fix Typo.Rafael Espindola2013-12-121-1/+1
| | | | llvm-svn: 197168
* Convert the other getHostByName implementations to StringRef.Rafael Espindola2013-12-121-5/+5
| | | | llvm-svn: 197166
* Return a StringRef from getHostCPUName.Rafael Espindola2013-12-121-1/+1
| | | | llvm-svn: 197158
* Make helper function static.Benjamin Kramer2013-11-251-2/+3
| | | | llvm-svn: 195650
* X86: enable AVX2 under Haswell native compilationTim Northover2013-11-251-6/+90
| | | | | | Patch by Adam Strzelecki llvm-svn: 195632
* X86: Add a description for AMD bdver3 aka Steamroller.Benjamin Kramer2013-11-041-3/+5
| | | | | | This is just bdver2 + FSGSBase. llvm-svn: 193984
* [SystemZ] Automatically detect zEC12 and z196 hostsRichard Sandiford2013-10-311-0/+42
| | | | | | | | | | As on other hosts, the CPU identification instruction is priveleged, so we need to look through /proc/cpuinfo. I copied the PowerPC way of handling "generic". Several tests were implicitly assuming z10 and so failed on z196. llvm-svn: 193742
* Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd2013-09-131-1/+2
| | | | | | | | | | | Implements Instruction scheduler latencies for Silvermont, using latencies from the Intel Silvermont Optimization Guide. Auto detects SLM. Turns on post RA scheduler when generating code for SLM. llvm-svn: 190717
* X86: Add a description of the Intel Atom Silvermont CPU.Benjamin Kramer2013-08-301-0/+5
| | | | | | Currently this is just the atom model with SSE4.2 enabled. llvm-svn: 189669
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