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* Lift EmitAssignment into MCObjectStreamer which gets rid of at least threeEli Bendersky2012-12-075-28/+5
| | | | | | duplicate implementations in format-specific streamers. llvm-svn: 169613
* Added Mapping Symbols for ARM ELFTim Northover2012-12-074-54/+8
| | | | | | | | | | Before this patch, when you objdump an LLVM-compiled file, objdump tried to decode data-in-code sections as if they were code. This patch adds the missing Mapping Symbols, as defined by "ELF for the ARM Architecture" (ARM IHI 0044D). Patch based on work by Greg Fitzgerald. llvm-svn: 169609
* Split MCELFStreamer into a header file.Logan Chien2012-12-071-107/+63
| | | | llvm-svn: 169603
* fixed valgrind issues of prior commit, this change applies r169456 changes ↵Pedro Artigas2012-12-061-8/+42
| | | | | | | | | | | | back to the tree with fixes. on darwin no valgrind issues exist in the tests that used to fail. original change description: change MCContext to work on the doInitialization/doFinalization model reviewed by Evan Cheng <evan.cheng@apple.com> llvm-svn: 169553
* Revert r169456, "change MCContext to work on the ↵NAKAMURA Takumi2012-12-061-31/+6
| | | | | | | | doInitialization/doFinalization model" It broke many builders. llvm-svn: 169462
* change MCContext to work on the doInitialization/doFinalization modelPedro Artigas2012-12-061-6/+31
| | | | | | reviewed by Evan Cheng <evan.cheng@apple.com> llvm-svn: 169456
* Change std::vector to SmallVector<4> and remove some unused methods.Eli Bendersky2012-12-051-1/+1
| | | | | | | | This is more consistent with other vectors in this code. In addition, I ran some tests compiling a large program and >96% of fragments have 4 or less fixups, so SmallVector<4> is a good optimization. llvm-svn: 169433
* Try to unbreak the build on hosts that don't transitively pull in a ↵Benjamin Kramer2012-12-051-2/+2
| | | | | | | | definition for int64_t. Also use the portable (ugly) format string macros, for MSVC compatibility. llvm-svn: 169396
* Added a option to the disassembler to print immediates as hex.Kevin Enderby2012-12-052-0/+15
| | | | | | | | | | | | | | | | | | | | This is for the lldb team so most of but not all of the values are to be printed as hex with this option. Some small values like the scale in an X86 address were requested to printed in decimal without the leading 0x. There may be some tweaks need to places that may still be in decimal that they want in hex. Specially for arm. I made my best guess. Any tweaks from here should be simple. I also did the best I know now with help from the C++ gurus creating the cleanest formatImm() utility function and containing the changes. But if someone has a better idea to make something cleaner I'm all ears and game for changing the implementation. rdar://8109283 llvm-svn: 169393
* This patch introduces initial-exec model support for thread-local storageBill Schmidt2012-12-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on 64-bit PowerPC ELF. The patch includes code to handle external assembly and MC output with the integrated assembler. It intentionally does not support the "old" JIT. For the initial-exec TLS model, the ABI requires the following to calculate the address of external thread-local variable x: Code sequence Relocation Symbol ld 9,x@got@tprel(2) R_PPC64_GOT_TPREL16_DS x add 9,9,x@tls R_PPC64_TLS x The register 9 is arbitrary here. The linker will replace x@got@tprel with the offset relative to the thread pointer to the generated GOT entry for symbol x. It will replace x@tls with the thread-pointer register (13). The two test cases verify correct assembly output and relocation output as just described. PowerPC-specific selection node variants are added for the two instructions above: LD_GOT_TPREL and ADD_TLS. These are inserted when an initial-exec global variable is encountered by PPCTargetLowering::LowerGlobalTLSAddress(), and later lowered to machine instructions LDgotTPREL and ADD8TLS. LDgotTPREL is a pseudo that uses the same LDrs support added for medium code model's LDtocL, with a different relocation type. The rest of the processing is straightforward. llvm-svn: 169281
* Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth2012-12-043-5/+3
| | | | | | | | | | missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-0325-95/+85
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* MC/AsmParser: Avoid unnecessary use of SourceMgr::FindBufferForLoc()Daniel Dunbar2012-12-011-7/+21
| | | | | | | | - Each macro instantiation introduces a new buffer, and FindBufferForLoc() is linear, so previously macro instantiation could be N^2 for some pathological inputs. llvm-svn: 169073
* Add the rest of the experimental fission sections to MC.Eric Christopher2012-11-301-0/+13
| | | | llvm-svn: 168986
* Add brief support for the fission .debug_info.dwo section forEric Christopher2012-11-281-0/+5
| | | | | | ELF output. llvm-svn: 168764
* Add comments.Eric Christopher2012-11-281-0/+4
| | | | llvm-svn: 168763
* This patch implements medium code model support for 64-bit PowerPC.Bill Schmidt2012-11-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default for 64-bit PowerPC is small code model, in which TOC entries must be addressable using a 16-bit offset from the TOC pointer. Additionally, only TOC entries are addressed via the TOC pointer. With medium code model, TOC entries and data sections can all be addressed via the TOC pointer using a 32-bit offset. Cooperation with the linker allows 16-bit offsets to be used when these are sufficient, reducing the number of extra instructions that need to be executed. Medium code model also does not generate explicit TOC entries in ".section toc" for variables that are wholly internal to the compilation unit. Consider a load of an external 4-byte integer. With small code model, the compiler generates: ld 3, .LC1@toc(2) lwz 4, 0(3) .section .toc,"aw",@progbits .LC1: .tc ei[TC],ei With medium model, it instead generates: addis 3, 2, .LC1@toc@ha ld 3, .LC1@toc@l(3) lwz 4, 0(3) .section .toc,"aw",@progbits .LC1: .tc ei[TC],ei Here .LC1@toc@ha is a relocation requesting the upper 16 bits of the 32-bit offset of ei's TOC entry from the TOC base pointer. Similarly, .LC1@toc@l is a relocation requesting the lower 16 bits. Note that if the linker determines that ei's TOC entry is within a 16-bit offset of the TOC base pointer, it will replace the "addis" with a "nop", and replace the "ld" with the identical "ld" instruction from the small code model example. Consider next a load of a function-scope static integer. For small code model, the compiler generates: ld 3, .LC1@toc(2) lwz 4, 0(3) .section .toc,"aw",@progbits .LC1: .tc test_fn_static.si[TC],test_fn_static.si .type test_fn_static.si,@object .local test_fn_static.si .comm test_fn_static.si,4,4 For medium code model, the compiler generates: addis 3, 2, test_fn_static.si@toc@ha addi 3, 3, test_fn_static.si@toc@l lwz 4, 0(3) .type test_fn_static.si,@object .local test_fn_static.si .comm test_fn_static.si,4,4 Again, the linker may replace the "addis" with a "nop", calculating only a 16-bit offset when this is sufficient. Note that it would be more efficient for the compiler to generate: addis 3, 2, test_fn_static.si@toc@ha lwz 4, test_fn_static.si@toc@l(3) The current patch does not perform this optimization yet. This will be addressed as a peephole optimization in a later patch. For the moment, the default code model for 64-bit PowerPC will remain the small code model. We plan to eventually change the default to medium code model, which matches current upstream GCC behavior. Note that the different code models are ABI-compatible, so code compiled with different models will be linked and execute correctly. I've tested the regression suite and the application/benchmark test suite in two ways: Once with the patch as submitted here, and once with additional logic to force medium code model as the default. The tests all compile cleanly, with one exception. The mandel-2 application test fails due to an unrelated ABI compatibility with passing complex numbers. It just so happens that small code model was incredibly lucky, in that temporary values in floating-point registers held the expected values needed by the external library routine that was called incorrectly. My current thought is to correct the ABI problems with _Complex before making medium code model the default, to avoid introducing this "regression." Here are a few comments on how the patch works, since the selection code can be difficult to follow: The existing logic for small code model defines three pseudo-instructions: LDtoc for most uses, LDtocJTI for jump table addresses, and LDtocCPT for constant pool addresses. These are expanded by SelectCodeCommon(). The pseudo-instruction approach doesn't work for medium code model, because we need to generate two instructions when we match the same pattern. Instead, new logic in PPCDAGToDAGISel::Select() intercepts the TOC_ENTRY node for medium code model, and generates an ADDIStocHA followed by either a LDtocL or an ADDItocL. These new node types correspond naturally to the sequences described above. The addis/ld sequence is generated for the following cases: * Jump table addresses * Function addresses * External global variables * Tentative definitions of global variables (common linkage) The addis/addi sequence is generated for the following cases: * Constant pool entries * File-scope static global variables * Function-scope static variables Expanding to the two-instruction sequences at select time exposes the instructions to subsequent optimization, particularly scheduling. The rest of the processing occurs at assembly time, in PPCAsmPrinter::EmitInstruction. Each of the instructions is converted to a "real" PowerPC instruction. When a TOC entry needs to be created, this is done here in the same manner as for the existing LDtoc, LDtocJTI, and LDtocCPT pseudo-instructions (I factored out a new routine to handle this). I had originally thought that if a TOC entry was needed for LDtocL or ADDItocL, it would already have been generated for the previous ADDIStocHA. However, at higher optimization levels, the ADDIStocHA may appear in a different block, which may be assembled textually following the block containing the LDtocL or ADDItocL. So it is necessary to include the possibility of creating a new TOC entry for those two instructions. Note that for LDtocL, we generate a new form of LD called LDrs. This allows specifying the @toc@l relocation for the offset field of the LD instruction (i.e., the offset is replaced by a SymbolLo relocation). When the peephole optimization described above is added, we will need to do similar things for all immediate-form load and store operations. The seven "mcm-n.ll" test cases are kept separate because otherwise the intermingling of various TOC entries and so forth makes the tests fragile and hard to understand. The above assumes use of an external assembler. For use of the integrated assembler, new relocations are added and used by PPCELFObjectWriter. Testing is done with "mcm-obj.ll", which tests for proper generation of the various relocations for the same sequences tested with the external assembler. llvm-svn: 168708
* Add support for .cfi_register now that it is easy to extent the representationRafael Espindola2012-11-254-0/+58
| | | | | | | to support it. Original patch with the parsing and plumbing by the PaX team and Roman Divacky. I added the bits in MCDwarf.cpp and the test. llvm-svn: 168565
* libLTO: Add a utility method to initialize the disassemblers.Benjamin Kramer2012-11-241-13/+0
| | | | | | | | | | | | Necessary to give disassembler users (like darwin's otool) a possibility to dlopen libLTO and still initialize the required LLVM bits. This used to go through libMCDisassembler but that's a gross layering violation, the MC layer can't pull in functions from the targets. Adding a function to libLTO is a bit of a hack but not worse than exposing other disassembler bits from libLTO. Fixes PR14362. llvm-svn: 168545
* Change the representation of MCCFIInstruction.Rafael Espindola2012-11-241-20/+12
| | | | | | | We now store the Register and Offset directly. MachineLocation is gone (from this file)! llvm-svn: 168536
* Give each MCCFIInstruction its own opcode.Rafael Espindola2012-11-242-41/+66
| | | | | | | This untangles the switch cases of the old Move and RelMove opcodes a bit and makes it clear how to add new instructions. llvm-svn: 168534
* Move a bit of duplicated code into a helper function.Rafael Espindola2012-11-241-46/+29
| | | | llvm-svn: 168533
* Refactor how MCCFIInstructions are created.Rafael Espindola2012-11-242-26/+36
| | | | | | | | | | Give MCCFIInstruction a single, private constructor and add helper static methods that create each type of cfi instruction. This is is preparation for changing its representation. The representation with a pair MachineLocations older than MC and has been abused quiet a bit to support more cfi instructions. llvm-svn: 168532
* Implement .cfi_undefined. Based on a patch from PaX team, updated byRafael Espindola2012-11-234-0/+47
| | | | | | Roman Divacky. I just added the testcase. llvm-svn: 168520
* Add relocations used for mips big GOT.Akira Hatanaka2012-11-211-0/+4
| | | | llvm-svn: 168448
* Emit relocations from .debug_aranges to .debug_info for asm filesAlexey Samsonov2012-11-141-9/+19
| | | | llvm-svn: 167926
* Add ARM TARGET2 relocation. The testcase will follow with actualy use-case.Anton Korobeynikov2012-11-091-1/+3
| | | | | | Based on the patch by Logan Chien! llvm-svn: 167633
* Fix for PR14264 cause by commit r167237 which did not take into account aKevin Enderby2012-11-051-1/+3
| | | | | | | | possible buffer change with a .macro directive. rdar://12637628 llvm-svn: 167408
* Add support for generating dwarf debugging info with assembly filesKevin Enderby2012-11-011-2/+19
| | | | | | | | | | run through the 'C' preprocessor. That is pick up the file name and line numbers from the cpp hash file line comments for the dwarf file and line numbers tables. rdar://9275556 llvm-svn: 167237
* [ms-inline asm] Add support for the TYPE operator.Chad Rosier2012-10-261-5/+10
| | | | | | Part of rdar://12576868 llvm-svn: 166790
* [ms-inline asm] Have the target AsmParser create the asmrewrite for the offsetofChad Rosier2012-10-261-6/+0
| | | | | | operator. llvm-svn: 166779
* [ms-inline asm] Add support for creating AsmRewrites in the target specificChad Rosier2012-10-252-26/+10
| | | | | | AsmParser logic. To be used/tested in a subsequent commit. llvm-svn: 166714
* Initial TOC support for PowerPC64 object creationAdhemerval Zanella2012-10-252-5/+21
| | | | | | | | | | | | | | This patch adds initial PPC64 TOC MC object creation using the small mcmodel (a single 64K TOC) adding the some TOC relocations (R_PPC64_TOC, R_PPC64_TOC16, and R_PPC64_TOC16DS). The addition of 'undefinedExplicitRelSym' hook on 'MCELFObjectTargetWriter' is meant to avoid the creation of an unreferenced ".TOC." symbol (used in the .odp creation) as well to set the R_PPC64_TOC relocation target as the temporary ".TOC." symbol. On PPC64 ABI, the R_PPC64_TOC relocation should not point to any symbol. llvm-svn: 166677
* [ms-inline asm] Create a register operand, rather than a memory operand when weChad Rosier2012-10-241-2/+2
| | | | | | | | | | see the offsetof operator. Previously, we were matching something like MOVrm in the front-end and later matching MOVrr in the back-end. This change makes things more consistent. It also fixes cases where we can't match against a memory operand as the source (test cases coming). Part of rdar://12470317 llvm-svn: 166592
* Make branch heavy code for generating marked up disassembly simplerKevin Enderby2012-10-231-0/+14
| | | | | | | and easier to read by adding a couple helper functions. Suggestion by Chandler Carruth and seconded by Meador Inge! llvm-svn: 166515
* [ms-inline asm] Add an implementation of the offset operator. This is a followChad Rosier2012-10-231-19/+38
| | | | | | | on patch to r166433. rdar://12470317 llvm-svn: 166488
* [ms-inline-asm] Implement _emit directive (which is roughly equivalent to ↵Eli Friedman2012-10-221-44/+68
| | | | | | | | .byte). <rdar://problem/12470345>. llvm-svn: 166451
* Add support for annotated disassembly output for X86 and arm.Kevin Enderby2012-10-221-0/+14
| | | | | | | | | | | Per the October 12, 2012 Proposal for annotated disassembly output sent out by Jim Grosbach this set of changes implements this for X86 and arm. The llvm-mc tool now has a -mdis option to produced the marked up disassembly and a couple of small example test cases have been added. rdar://11764962 llvm-svn: 166445
* [ms-inline asm] Don't rewrite out parts of an inline-asm skipped by .if 0 ↵Eli Friedman2012-10-221-24/+1
| | | | | | | | and friends. It's unnecessary and makes the generated assembly less faithful to the original source. llvm-svn: 166440
* Symbol hygiene: Make sure declarations and definitions match, make helper ↵Benjamin Kramer2012-10-201-2/+2
| | | | | | functions static. llvm-svn: 166376
* [ms-inline asm] Rename AsmOpRewrite to just AsmRewrite to be more generic. ↵Chad Rosier2012-10-201-13/+13
| | | | | | No functional change intended. llvm-svn: 166360
* [ms-inline asm] If the state of the parser is ignore, then don't parse theChad Rosier2012-10-201-2/+25
| | | | | | inline assembly. Also make sure the remove the ignored statements from the IR. llvm-svn: 166357
* [ms-inline asm] Continue parsing even when we're in an ignore block.Chad Rosier2012-10-191-1/+1
| | | | llvm-svn: 166352
* [ms-inline asm] Reset the opcode prior to parsing a statement.Chad Rosier2012-10-191-1/+6
| | | | llvm-svn: 166349
* [ms-inline asm] Have the TargetParser callback to Sema to determine the size ofChad Rosier2012-10-191-11/+35
| | | | | | | a memory operand. Retain this information and then add the sizing directives to the IR. This allows the backend to do proper instruction selection. llvm-svn: 166316
* [ms-inline asm] Add the isParsingInlineAsm() function to the MCAsmTargetParser.Chad Rosier2012-10-191-1/+1
| | | | llvm-svn: 166292
* Pacify -Wnon-virtual-dtor.Nick Lewycky2012-10-191-0/+2
| | | | llvm-svn: 166270
* [ms-inline asm] Add a size argument to the LookupInlineAsmIdentifier() callback,Chad Rosier2012-10-181-1/+3
| | | | | | which will be used by the asm matcher in the near future. llvm-svn: 166222
* [ms-inline asm] Have the LookupInlineAsmIdentifier() callback function return aChad Rosier2012-10-181-24/+13
| | | | | | | *NamedDecl. In turn, build the expressions after we're finished parsing the asm. This avoids a crasher if the lookup fails. llvm-svn: 166212
* [ms-inline asm] Move most of the AsmParsing logic in clang back into the MCChad Rosier2012-10-181-18/+201
| | | | | | | | | layer. Add the ParseMSInlineAsm() function, which is the new interface to clang. Also expose the new MCAsmParserSemaCallback interface, which is used by the back-end to do name lookup in Sema. Finally, remove the now defunct APIs introduced in r165946. llvm-svn: 166183
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