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path: root/llvm/lib/MC/MCSubtargetInfo.cpp
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* Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick2012-09-171-23/+14
| | | | | | | I have to work out the Target/CodeGen header dependencies before putting this back. llvm-svn: 164072
* InitMCProcessorAndrew Trick2012-09-171-14/+15
| | | | llvm-svn: 164066
* TargetSchedModel API. Implement latency lookup, disabled.Andrew Trick2012-09-171-1/+1
| | | | llvm-svn: 164065
* TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick2012-09-171-1/+9
| | | | | | model. llvm-svn: 164061
* TargetSchedModel interface. To be implemented...Andrew Trick2012-09-141-0/+6
| | | | llvm-svn: 163934
* Define MC data tables for the new scheduling machine model.Andrew Trick2012-09-141-5/+5
| | | | llvm-svn: 163933
* Constify subtarget info properly so that we dont cast away the const inRoman Divacky2012-09-051-3/+3
| | | | | | the SubtargetInfoKV tables. Found by gcc48 -Wcast-qual. llvm-svn: 163251
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-071-14/+19
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
* Tweak spelling.Andrew Trick2012-07-071-2/+2
| | | | llvm-svn: 159889
* misched: Added MultiIssueItineraries.Andrew Trick2012-06-051-2/+4
| | | | | | | | This allows a subtarget to explicitly specify the issue width and other properties without providing pipeline stage details for every instruction. llvm-svn: 157979
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-8/+11
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Change createAsmParser to take a MCSubtargetInfo instead of triple,Evan Cheng2011-07-091-0/+17
| | | | | | | | | CPU, and feature string. Parsing some asm directives can change subtarget state (e.g. .code 16) and it must be reflected in other modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance must be shared. llvm-svn: 134795
* Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng2011-07-071-8/+32
| | | | llvm-svn: 134606
* Add getFeatureBits to extract feature bits for a given CPU.Evan Cheng2011-07-021-0/+8
| | | | llvm-svn: 134298
* - Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng2011-07-011-0/+44
itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. llvm-svn: 134257
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