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* This patch improves the 64-bit PowerPC InitialExec TLS support by providingBill Schmidt2012-12-141-1/+2
| | | | | | | | | | | | | | | | | | | | | | | for a wider range of GOT entries that can hold thread-relative offsets. This matches the behavior of GCC, which was not documented in the PPC64 TLS ABI. The ABI will be updated with the new code sequence. Former sequence: ld 9,x@got@tprel(2) add 9,9,x@tls New sequence: addis 9,2,x@got@tprel@ha ld 9,x@got@tprel@l(9) add 9,9,x@tls Note that a linker optimization exists to transform the new sequence into the shorter sequence when appropriate, by replacing the addis with a nop and modifying the base register and relocation type of the ld. llvm-svn: 170209
* This patch implements local-dynamic TLS model support for the 64-bitBill Schmidt2012-12-121-0/+5
| | | | | | | | | | | | | | | | | | | | | | PowerPC target. This is the last of the four models, so we now have full TLS support. This is mostly a straightforward extension of the general dynamic model. I had to use an additional Chain operand to tie ADDIS_DTPREL_HA to the register copy following ADDI_TLSLD_L; otherwise everything above the ADDIS_DTPREL_HA appeared dead and was removed. As before, there are new test cases to test the assembly generation, and the relocations output during integrated assembly. The expected code gen sequence can be read in test/CodeGen/PowerPC/tls-ld.ll. There are a couple of things I think can be done more efficiently in the overall TLS code, so there will likely be a clean-up patch forthcoming; but for now I want to be sure the functionality is in place. Bill llvm-svn: 170003
* Add ARM NONE and PREL31 relocation types.Logan Chien2012-12-121-2/+6
| | | | | | | | Add R_ARM_NONE and R_ARM_PREL31 relocation types to MCExpr. Both of them will be used while generating .ARM.extab and .ARM.exidx sections. llvm-svn: 169965
* This patch implements the general dynamic TLS model for 64-bit PowerPC.Bill Schmidt2012-12-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Given a thread-local symbol x with global-dynamic access, the generated code to obtain x's address is: Instruction Relocation Symbol addis ra,r2,x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x addi r3,ra,x@got@tlsgd@l R_PPC64_GOT_TLSGD16_L x bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x R_PPC64_REL24 __tls_get_addr nop <use address in r3> The implementation borrows from the medium code model work for introducing special forms of ADDIS and ADDI into the DAG representation. This is made slightly more complicated by having to introduce a call to the external function __tls_get_addr. Using the full call machinery is overkill and, more importantly, makes it difficult to add a special relocation. So I've introduced another opcode GET_TLS_ADDR to represent the function call, and surrounded it with register copies to set up the parameter and return value. Most of the code is pretty straightforward. I ran into one peculiarity when I introduced a new PPC opcode BL8_NOP_ELF_TLSGD, which is just like BL8_NOP_ELF except that it takes another parameter to represent the symbol ("x" above) that requires a relocation on the call. Something in the TblGen machinery causes BL8_NOP_ELF and BL8_NOP_ELF_TLSGD to be treated identically during the emit phase, so this second operand was never visited to generate relocations. This is the reason for the slightly messy workaround in PPCMCCodeEmitter.cpp:getDirectBrEncoding(). Two new tests are included to demonstrate correct external assembly and correct generation of relocations using the integrated assembler. Comments welcome! Thanks, Bill llvm-svn: 169910
* This patch introduces initial-exec model support for thread-local storageBill Schmidt2012-12-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on 64-bit PowerPC ELF. The patch includes code to handle external assembly and MC output with the integrated assembler. It intentionally does not support the "old" JIT. For the initial-exec TLS model, the ABI requires the following to calculate the address of external thread-local variable x: Code sequence Relocation Symbol ld 9,x@got@tprel(2) R_PPC64_GOT_TPREL16_DS x add 9,9,x@tls R_PPC64_TLS x The register 9 is arbitrary here. The linker will replace x@got@tprel with the offset relative to the thread pointer to the generated GOT entry for symbol x. It will replace x@tls with the thread-pointer register (13). The two test cases verify correct assembly output and relocation output as just described. PowerPC-specific selection node variants are added for the two instructions above: LD_GOT_TPREL and ADD_TLS. These are inserted when an initial-exec global variable is encountered by PPCTargetLowering::LowerGlobalTLSAddress(), and later lowered to machine instructions LDgotTPREL and ADD8TLS. LDgotTPREL is a pseudo that uses the same LDrs support added for medium code model's LDtocL, with a different relocation type. The rest of the processing is straightforward. llvm-svn: 169281
* This patch implements medium code model support for 64-bit PowerPC.Bill Schmidt2012-11-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default for 64-bit PowerPC is small code model, in which TOC entries must be addressable using a 16-bit offset from the TOC pointer. Additionally, only TOC entries are addressed via the TOC pointer. With medium code model, TOC entries and data sections can all be addressed via the TOC pointer using a 32-bit offset. Cooperation with the linker allows 16-bit offsets to be used when these are sufficient, reducing the number of extra instructions that need to be executed. Medium code model also does not generate explicit TOC entries in ".section toc" for variables that are wholly internal to the compilation unit. Consider a load of an external 4-byte integer. With small code model, the compiler generates: ld 3, .LC1@toc(2) lwz 4, 0(3) .section .toc,"aw",@progbits .LC1: .tc ei[TC],ei With medium model, it instead generates: addis 3, 2, .LC1@toc@ha ld 3, .LC1@toc@l(3) lwz 4, 0(3) .section .toc,"aw",@progbits .LC1: .tc ei[TC],ei Here .LC1@toc@ha is a relocation requesting the upper 16 bits of the 32-bit offset of ei's TOC entry from the TOC base pointer. Similarly, .LC1@toc@l is a relocation requesting the lower 16 bits. Note that if the linker determines that ei's TOC entry is within a 16-bit offset of the TOC base pointer, it will replace the "addis" with a "nop", and replace the "ld" with the identical "ld" instruction from the small code model example. Consider next a load of a function-scope static integer. For small code model, the compiler generates: ld 3, .LC1@toc(2) lwz 4, 0(3) .section .toc,"aw",@progbits .LC1: .tc test_fn_static.si[TC],test_fn_static.si .type test_fn_static.si,@object .local test_fn_static.si .comm test_fn_static.si,4,4 For medium code model, the compiler generates: addis 3, 2, test_fn_static.si@toc@ha addi 3, 3, test_fn_static.si@toc@l lwz 4, 0(3) .type test_fn_static.si,@object .local test_fn_static.si .comm test_fn_static.si,4,4 Again, the linker may replace the "addis" with a "nop", calculating only a 16-bit offset when this is sufficient. Note that it would be more efficient for the compiler to generate: addis 3, 2, test_fn_static.si@toc@ha lwz 4, test_fn_static.si@toc@l(3) The current patch does not perform this optimization yet. This will be addressed as a peephole optimization in a later patch. For the moment, the default code model for 64-bit PowerPC will remain the small code model. We plan to eventually change the default to medium code model, which matches current upstream GCC behavior. Note that the different code models are ABI-compatible, so code compiled with different models will be linked and execute correctly. I've tested the regression suite and the application/benchmark test suite in two ways: Once with the patch as submitted here, and once with additional logic to force medium code model as the default. The tests all compile cleanly, with one exception. The mandel-2 application test fails due to an unrelated ABI compatibility with passing complex numbers. It just so happens that small code model was incredibly lucky, in that temporary values in floating-point registers held the expected values needed by the external library routine that was called incorrectly. My current thought is to correct the ABI problems with _Complex before making medium code model the default, to avoid introducing this "regression." Here are a few comments on how the patch works, since the selection code can be difficult to follow: The existing logic for small code model defines three pseudo-instructions: LDtoc for most uses, LDtocJTI for jump table addresses, and LDtocCPT for constant pool addresses. These are expanded by SelectCodeCommon(). The pseudo-instruction approach doesn't work for medium code model, because we need to generate two instructions when we match the same pattern. Instead, new logic in PPCDAGToDAGISel::Select() intercepts the TOC_ENTRY node for medium code model, and generates an ADDIStocHA followed by either a LDtocL or an ADDItocL. These new node types correspond naturally to the sequences described above. The addis/ld sequence is generated for the following cases: * Jump table addresses * Function addresses * External global variables * Tentative definitions of global variables (common linkage) The addis/addi sequence is generated for the following cases: * Constant pool entries * File-scope static global variables * Function-scope static variables Expanding to the two-instruction sequences at select time exposes the instructions to subsequent optimization, particularly scheduling. The rest of the processing occurs at assembly time, in PPCAsmPrinter::EmitInstruction. Each of the instructions is converted to a "real" PowerPC instruction. When a TOC entry needs to be created, this is done here in the same manner as for the existing LDtoc, LDtocJTI, and LDtocCPT pseudo-instructions (I factored out a new routine to handle this). I had originally thought that if a TOC entry was needed for LDtocL or ADDItocL, it would already have been generated for the previous ADDIStocHA. However, at higher optimization levels, the ADDIStocHA may appear in a different block, which may be assembled textually following the block containing the LDtocL or ADDItocL. So it is necessary to include the possibility of creating a new TOC entry for those two instructions. Note that for LDtocL, we generate a new form of LD called LDrs. This allows specifying the @toc@l relocation for the offset field of the LD instruction (i.e., the offset is replaced by a SymbolLo relocation). When the peephole optimization described above is added, we will need to do similar things for all immediate-form load and store operations. The seven "mcm-n.ll" test cases are kept separate because otherwise the intermingling of various TOC entries and so forth makes the tests fragile and hard to understand. The above assumes use of an external assembler. For use of the integrated assembler, new relocations are added and used by PPCELFObjectWriter. Testing is done with "mcm-obj.ll", which tests for proper generation of the various relocations for the same sequences tested with the external assembler. llvm-svn: 168708
* Add relocations used for mips big GOT.Akira Hatanaka2012-11-211-0/+4
| | | | llvm-svn: 168448
* Add ARM TARGET2 relocation. The testcase will follow with actualy use-case.Anton Korobeynikov2012-11-091-1/+3
| | | | | | Based on the patch by Logan Chien! llvm-svn: 167633
* Rename virtual table anchors from Anchor() to anchor() for consistency with ↵Craig Topper2012-09-261-1/+1
| | | | | | the rest of the tree. llvm-svn: 164666
* Release build: guard dump functions withManman Ren2012-09-121-1/+1
| | | | | | | | "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163344. llvm-svn: 163679
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-061-0/+2
| | | | | | No functional change. llvm-svn: 163344
* Lower constant pools and jump tables via TOC on PPC64/SVR4.Roman Divacky2012-08-241-1/+2
| | | | | | In collaboration with Adhemerval Zanella. llvm-svn: 162562
* Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind.Akira Hatanaka2012-07-211-0/+2
| | | | | | Test case will be added later when long branch patch is checked in. llvm-svn: 160597
* Implement local-exec TLS on PowerPC.Roman Divacky2012-06-041-0/+2
| | | | llvm-svn: 157935
* Prune some includes and forward declarations.Craig Topper2012-03-261-0/+1
| | | | llvm-svn: 153429
* ARM Thumb symbol references in assembly need the low bit set.Jim Grosbach2012-02-241-0/+5
| | | | | | | | | Add support for a missed case when the symbols in a difference expression are in the same section but not the same fragment. rdar://10924681 llvm-svn: 151345
* Add support for implicit TLS model used with MS VC runtime.Anton Korobeynikov2012-02-111-0/+1
| | | | | | Patch by Kai Nacke! llvm-svn: 150307
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-5/+3
| | | | llvm-svn: 149967
* Add support for the R_ARM_TARGET1 relocation, which should be given to ↵James Molloy2012-01-261-1/+3
| | | | | | | | relocations applied to all C++ constructors and destructors. This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against. llvm-svn: 149057
* Add 'llvm_unreachable' to passify GCC's understanding of the constraintsChandler Carruth2012-01-101-0/+2
| | | | | | | | of several newly un-defaulted switches. This also helps optimizers (including LLVM's) recognize that every case is covered, and we should assume as much. llvm-svn: 147861
* Remove unnecessary default cases in switches that cover all enum values.David Blaikie2012-01-101-3/+0
| | | | llvm-svn: 147855
* Local dynamic TLS model for direct object output. Create the correct TLS MIPSAkira Hatanaka2011-12-221-0/+18
| | | | | | | | ELF relocations. Patch by Jack Carter. llvm-svn: 147118
* Remove function printMipsSymbolRef.Akira Hatanaka2011-11-151-35/+0
| | | | llvm-svn: 144663
* This is the first of several patches for Mips direct object generation.Bruno Cardoso Lopes2011-10-251-0/+35
| | | | | | | | This first patch is for expression variable kinds. Patch by Jack Carter! llvm-svn: 142934
* Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to ↵Evan Cheng2011-07-251-1/+0
| | | | | | createMCAsmBackend. llvm-svn: 136010
* Move TargetAsmParser.h TargetAsmBackend.h and TargetAsmLexer.h to MC where ↵Evan Cheng2011-07-231-1/+1
| | | | | | they belong. llvm-svn: 135833
* Fix emission of PPC64 assembler on non-darwin platforms by splittingRoman Divacky2011-06-091-6/+8
| | | | | | | | VK_PPC_{HA,LO}16 into darwin and gas variants. Darwin wants {ha,lo}16(symbol) while gnu as wants symbol@{ha,l}. llvm-svn: 132802
* MCExpr: Add FindAssociatedSection, which attempts to mirror the 'as' semanticsDaniel Dunbar2011-04-291-0/+42
| | | | | | that associate sections with expressions. llvm-svn: 130517
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-1/+1
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Add support for Thumb interworking addresses for symbol offsets that get ↵Owen Anderson2011-03-211-0/+5
| | | | | | | | constant folded very early. This fixes SPASS with -integrated-as. <rdar://problem/9165399> llvm-svn: 128037
* Add support for lowercase variants.Rafael Espindola2011-01-231-0/+14
| | | | llvm-svn: 124071
* Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a stepEvan Cheng2011-01-131-8/+0
| | | | | | | | in the right direction. It eliminated some hacks and will unblock codegen work. But it's far from being done. It doesn't reject illegal expressions, e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all. llvm-svn: 123369
* Add r122359 back now that the bug in MCDwarfLineAddrFragment fragment has beenRafael Espindola2010-12-221-19/+5
| | | | | | fixed. llvm-svn: 122448
* Revert r122359 while I debug PR8845.Rafael Espindola2010-12-221-5/+19
| | | | llvm-svn: 122427
* Use references and simplify.Rafael Espindola2010-12-221-6/+3
| | | | llvm-svn: 122405
* Simplify EvaluateAsAbsolute now that EvaluateAsRelocatableImpl does allRafael Espindola2010-12-211-19/+5
| | | | | | the folding it can. llvm-svn: 122359
* Fixed version of 122160 (the previous one would fold undefined symbols).Rafael Espindola2010-12-191-50/+52
| | | | llvm-svn: 122167
* Revert 122160 while I debug it.Rafael Espindola2010-12-191-44/+50
| | | | llvm-svn: 122165
* Move all folding to AttemptToFoldSymbolOffsetDifference.Rafael Espindola2010-12-191-50/+44
| | | | llvm-svn: 122160
* Merge isAbsolute into IsSymbolRefDifferenceFullyResolved.Rafael Espindola2010-12-181-5/+4
| | | | llvm-svn: 122148
* Remove the MCObjectFormat class.Rafael Espindola2010-12-181-3/+2
| | | | llvm-svn: 122147
* Add a FIXME and explain a hack.Rafael Espindola2010-12-181-1/+4
| | | | llvm-svn: 122144
* Fix the note.Rafael Espindola2010-12-181-1/+1
| | | | llvm-svn: 122139
* Revert 122011, 122012, 122013, 122023 adding back an important optimization.Rafael Espindola2010-12-181-16/+56
| | | | | | I added a note, but suggestions on how to add a test are really welcome. llvm-svn: 122138
* MC/Expr: Implemnt more aggressive folding during symbol evaluation usingDaniel Dunbar2010-12-171-8/+44
| | | | | | | | | | | | | | | | IsSymbolRefDifferenceFullyResolved(). For example, we will now fold away something like: -- _a: ... L0: ... L1: ... .long (L1 - L0) / 2 -- llvm-svn: 122043
* MC/Expr: Simplify.Daniel Dunbar2010-12-171-8/+0
| | | | llvm-svn: 122023
* MC: Remove another dead MCAssembler argument, and update clients.Daniel Dunbar2010-12-171-21/+1
| | | | llvm-svn: 122013
* MC: Remove dead MCAssembler argument -- Rafael, can you check the FIXME I addedDaniel Dunbar2010-12-171-12/+9
| | | | | | here? llvm-svn: 122012
* MC: Simplify (remove unnecessary MCAssembler argument, obsoleted by containmentDaniel Dunbar2010-12-171-12/+8
| | | | | | in MCAsmLayout). llvm-svn: 122011
* Write => in a more normal form.Daniel Dunbar2010-12-171-1/+2
| | | | llvm-svn: 122009
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