| Commit message (Collapse) | Author | Age | Files | Lines |
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When two section names share a suffix, reuse the entry in shstrtab.
llvm-svn: 129115
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gun as does. This makes it a lot easier to compare the output of both
as the addresses are now a lot closer.
llvm-svn: 127972
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other components can use them.
llvm-svn: 126942
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for calls to weak symbols with a definition has the appearance of working
with LLVM-generated code because weak symbol definitions are put in their
own sections.
llvm-svn: 126933
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(duplicated) functions to new MCELF class.
llvm-svn: 126686
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Fixes PR9292.
llvm-svn: 126330
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llvm-svn: 126157
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the right thing and stop trying to copy it. Fixes PR8944.
llvm-svn: 125648
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failures with relocations.
The code committed is a first cut at compatibility for emitted relocations in
ELF .o.
Why do this? because existing ARM tools like emitting relocs symbols as
explicit relocations, not as section-offset relocs.
Result is that with these changes,
1) relocs are now substantially identical what to gcc outputs.
2) larger apps (including many spec2k tests) compile, cross-link, and pass
Added reminder fixme to tests for future conversion to .s form.
llvm-svn: 124996
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5 to match the current doc.
Added FIXME reminder Make it really configurable later.
llvm-svn: 124899
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(yes, this is different from R_ARM_CALL)
- Adds a new method getARMBranchTargetOpValue() which handles the
necessary distinction between the conditional and unconditional br/bl
needed for ARM/ELF
At least for ARM mode, the needed fixup for conditional versus unconditional
br/bl is identical, but the ARM docs and existing ARM tools expect this
reloc type...
Added a few FIXME's for future naming fixups in ARMInstrInfo.td
llvm-svn: 124895
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llvm-svn: 124077
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Add support for SHT_X86_64_UNWIND.
llvm-svn: 124059
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llvm-svn: 124056
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- Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first.
- Added support for Thumb2 :lower16: and :upper16: fix up.
- Added :upper16: and :lower16: relocation support to mach-o object writer.
llvm-svn: 123424
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llvm-svn: 123347
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R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)
llvm-svn: 123294
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llvm-svn: 122658
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llvm-svn: 122579
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supports.
llvm-svn: 122577
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llvm-svn: 122568
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have a single point where targets test if a relocation is needed.
llvm-svn: 122549
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llvm-svn: 122404
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llvm-svn: 122268
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llvm-svn: 122148
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llvm-svn: 122147
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llvm-svn: 122134
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llvm-svn: 122070
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llvm-svn: 122067
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llvm-svn: 122064
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llvm-svn: 122050
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specific hook.
- Currently just has stub implementations for Mach-O, ELF, and COFF.
llvm-svn: 122037
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-- and remove FIXME asking for the same!
llvm-svn: 122032
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2. Fixed EmitLocalCommonSymbol for ELF (Yes, they exist. :)
Test added.
llvm-svn: 121951
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Test has fixme, to move to .s -> .o test when AsmParser works better.
llvm-svn: 121732
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llvm-svn: 121496
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llvm-svn: 121404
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Added test to check bl __aeabi_read_tp gets emitted properly for ELF/ASM
as well as ELF/OBJ (including fixup)
Also added support for ELF::R_ARM_TLS_IE32
llvm-svn: 121312
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llvm-svn: 121308
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llvm-svn: 121226
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actuall addresses in a .o file, so it is better to let the MachO writer compute
it.
This is good for two reasons. First, areas that shouldn't care about
addresses now don't have access to it. Second, the layout of each section
is independent. I should use this in a subsequent commit to speed it up.
Most of the patch is just removing the section address computation. The two
interesting parts are the change on how we handle padding in the end
of sections and how MachO can get the address of a-b when a and b are in
different sections.
Since now the expression evaluation normally doesn't know the section address,
it will think that a-b needs relocation and let the MachO writer know. Once
it has computed the section addresses, it calls back the expression evaluation
with the section addresses to resolve these expressions.
The remaining problem is the handling of padding. Currently it will create
a special alignment fragment at the end. Since that fragment doesn't update
the alignment of the section, it needs the real address to be computed.
Since now the layout will not compute a-b with a and b in different sections,
the only effect that the special alignment fragment has is update the
address size of the section. This can also be done by the MachO writer.
llvm-svn: 121076
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llvm-svn: 121072
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+ ARM/X86/MBlaze now share a common RecordRelocation
+ ARM/X86/MBlaze arch specific routines are limited to GetRelocType()
llvm-svn: 121043
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that on the ELF writer to detect a section we created.
llvm-svn: 120981
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llvm-svn: 120977
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contain only data. Handle them specially instead of using AddSectionToTheEnd.
This moves a hack from the generic assembler to the elf writer. It is also
a bit faster and should make other improvements easier.
llvm-svn: 120683
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pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291.
llvm-svn: 120635
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Additionally, update these to unified syntax.
llvm-svn: 120589
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llvm-svn: 120585
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Lifted adjustFixupValue() from Darwin for sharing w ELF.
Test added
TODO:
refactor ELFObjectWriter::RecordRelocation more.
Possibly share more code with Darwin?
Lots more relocations...
llvm-svn: 120534
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