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* [Constant] add undef element query for vector constants; NFCSanjay Patel2018-07-061-0/+10
| | | | | | | This is likely to be used in D48987 and similar patches, so adding it as an NFC preliminary step. llvm-svn: 336442
* [X86] Remove FMA4 scalar intrinsics. Use llvm.fma intrinsic instead.Craig Topper2018-07-061-0/+16
| | | | | | | | The intrinsics can be implemented with a f32/f64 llvm.fma intrinsic and an insert into a zero vector. There are a couple regressions here due to SelectionDAG not being able to pull an fneg through an extract_vector_elt. I'm not super worried about this though as InstCombine should be able to do it before we get to SelectionDAG. llvm-svn: 336416
* [X86] Remove all of the avx512 masked packed fma intrinsics. Use llvm.fma or ↵Craig Topper2018-07-061-2/+128
| | | | | | | | | | unmasked 512-bit intrinsics with rounding mode. This upgrades all of the intrinsics to use fneg instructions to convert fma into fmsub/fnmsub/fnmadd/fmsubadd. And uses a select instruction for masking. This matches how clang uses the intrinsics these days. llvm-svn: 336409
* [X86] Remove the last of the 'x86.fma.' intrinsics and autoupgrade them to ↵Craig Topper2018-07-051-19/+25
| | | | | | | | 'llvm.fma'. Add upgrade tests for all. Still need to remove the AVX512 masked versions. llvm-svn: 336383
* [X86] Remove X86 specific scalar FMA intrinsics and upgrade to tart ↵Craig Topper2018-07-051-52/+33
| | | | | | independent FMA and extractelement/insertelement. llvm-svn: 336315
* [X86] Remove some of the packed FMA3 intrinsics since we no longer use them ↵Craig Topper2018-07-051-40/+32
| | | | | | | | | | in clang. There's a regression in here due to inability to combine fneg inputs of X86ISD::FMSUB/FNMSUB/FNMADD nodes. More removals to come, but I wanted to stop and fix the regression that showed up in this first. llvm-svn: 336303
* [Constants] add identity constants for fadd/fmulSanjay Patel2018-07-031-1/+6
| | | | | | | | | | | | | | | | As the test diffs show, the current users of getBinOpIdentity() are InstCombine and Reassociate. SLP vectorizer is a candidate for using this functionality too (D28907). The InstCombine shuffle improvements are part of the planned enhancements noted in D48830. InstCombine actually has several other uses of getBinOpIdentity() via SimplifyUsingDistributiveLaws(), but we don't call that for any FP ops. Fixing that might be another part of removing the custom reassociation in InstCombine that is only done for fadd+fmul. llvm-svn: 336215
* Rename lazy initialization functions to reflect behavior (NFC)Teresa Johnson2018-07-031-12/+12
| | | | | | Suggested in review for D48698. llvm-svn: 336207
* [InstCombine] fold shuffle-with-binop and common valueSanjay Patel2018-07-031-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | This is the last significant change suggested in PR37806: https://bugs.llvm.org/show_bug.cgi?id=37806#c5 ...though there are several follow-ups noted in the code comments in this patch to complete this transform. It's possible that a binop feeding a select-shuffle has been eliminated by earlier transforms (or the code was just written like this in the 1st place), so we'll fail to match the patterns that have 2 binops from: D48401, D48678, D48662, D48485. In that case, we can try to materialize identity constants for the remaining binop to fill in the "ghost" lanes of the vector (where we just want to pass through the original values of the source operand). I added comments to ConstantExpr::getBinOpIdentity() to show planned follow-ups. For now, we only handle the 5 commutative integer binops (add/mul/and/or/xor). Differential Revision: https://reviews.llvm.org/D48830 llvm-svn: 336196
* [IR] Strip trailing whitespace. NFCBjorn Pettersson2018-07-037-46/+46
| | | | llvm-svn: 336194
* [DebugInfo] Corrections for salvageDebugInfoBjorn Pettersson2018-07-031-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When salvaging a dbg.declare/dbg.addr we should not add DW_OP_stack_value to the DIExpression (see test/Transforms/InstCombine/salvage-dbg-declare.ll). Consider this example %vla = alloca i32, i64 2 call void @llvm.dbg.declare(metadata i32* %vla, metadata !1, metadata !DIExpression()) Instcombine will turn it into %vla1 = alloca [2 x i32] %vla1.sub = getelementptr inbounds [2 x i32], [2 x i32]* %vla, i64 0, i64 0 call void @llvm.dbg.declare(metadata [2 x i32]* %vla1.sub, metadata !19, metadata !DIExpression()) If the GEP can be eliminated, then the dbg.declare will be salvaged and we should get %vla1 = alloca [2 x i32] call void @llvm.dbg.declare(metadata [2 x i32]* %vla1, metadata !19, metadata !DIExpression()) The problem was that salvageDebugInfo did not recognize dbg.declare as being indirect (%vla1 points to the value, it does not hold the value), so we incorrectly got call void @llvm.dbg.declare(metadata [2 x i32]* %vla1, metadata !19, metadata !DIExpression(DW_OP_stack_value)) I also made sure that llvm::salvageDebugInfo and DIExpression::prependOpcodes do not add DW_OP_stack_value to the DIExpression in case no new operands are added to the DIExpression. That way we avoid to, unneccessarily, turn a register location expression into an implicit location expression in some situations (see test11 in test/Transforms/LICM/sinking.ll). Reviewers: aprantl, vsk Reviewed By: aprantl, vsk Subscribers: JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48837 llvm-svn: 336191
* [DebugInfo] Fix PR37395.Shiva Chen2018-07-031-1/+4
| | | | | | | | | | DbgLabelInst has no address as its operands. Differential Revision: https://reviews.llvm.org/D46738 Patch by Hsiangkai Wang. llvm-svn: 336176
* Reappl "[Dominators] Add the DomTreeUpdater class"Jakub Kuderski2018-07-032-0/+513
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch is the first in a series of patches related to the [[ http://lists.llvm.org/pipermail/llvm-dev/2018-June/123883.html | RFC - A new dominator tree updater for LLVM ]]. This patch introduces the DomTreeUpdater class, which provides a cleaner API to perform updates on available dominator trees (none, only DomTree, only PostDomTree, both) using different update strategies (eagerly or lazily) to simplify the updating process. —Prior to the patch— - Directly calling update functions of DominatorTree updates the data structure eagerly while DeferredDominance does updates lazily. - DeferredDominance class cannot be used when a PostDominatorTree also needs to be updated. - Functions receiving DT/DDT need to branch a lot which is currently necessary. - Functions using both DomTree and PostDomTree need to call the update function separately on both trees. - People need to construct an additional DeferredDominance class to use functions only receiving DDT. —After the patch— Patch by Chijun Sima <simachijun@gmail.com>. Reviewers: kuhar, brzycki, dmgreen, grosser, davide Reviewed By: kuhar, brzycki Author: NutshellySima Subscribers: vsk, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D48383 llvm-svn: 336163
* [ThinLTO] Fix printing of aliases for distributed backend indexesTeresa Johnson2018-07-031-2/+8
| | | | | | | | | | | | | | | | Summary: When we import an alias (which will import a copy of the aliasee), but aren't going to import the aliasee directly, the distributed backend index will not contain the aliasee summary. Handle this in the summary assembly printer by printing "null" as the aliasee. Reviewers: davidxl, dexonsmith Subscribers: mehdi_amini, inglorion, eraman, steven_wu, llvm-commits Differential Revision: https://reviews.llvm.org/D48699 llvm-svn: 336160
* [ThinLTO] Fix printing of module paths for distributed backend indexesTeresa Johnson2018-07-021-17/+41
| | | | | | | | | | | | | | | | Summary: In the individual index files emitted for distributed ThinLTO backends, the module path ids are not contiguous. Assign slots to module paths in order to handle this better and also to get contiguous numbering in the summary assembly. Reviewers: davidxl, dexonsmith Subscribers: mehdi_amini, inglorion, eraman, llvm-commits, steven_wu Differential Revision: https://reviews.llvm.org/D48698 llvm-svn: 336148
* Revert "[Dominators] Add the DomTreeUpdater class"Jakub Kuderski2018-07-022-512/+0
| | | | | | | | Temporary revert because of a failing test on some buildbots. This reverts commit r336114. llvm-svn: 336117
* [Dominators] Add the DomTreeUpdater classJakub Kuderski2018-07-022-0/+512
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch is the first in a series of patches related to the [[ http://lists.llvm.org/pipermail/llvm-dev/2018-June/123883.html | RFC - A new dominator tree updater for LLVM ]]. This patch introduces the DomTreeUpdater class, which provides a cleaner API to perform updates on available dominator trees (none, only DomTree, only PostDomTree, both) using different update strategies (eagerly or lazily) to simplify the updating process. —Prior to the patch— - Directly calling update functions of DominatorTree updates the data structure eagerly while DeferredDominance does updates lazily. - DeferredDominance class cannot be used when a PostDominatorTree also needs to be updated. - Functions receiving DT/DDT need to branch a lot which is currently necessary. - Functions using both DomTree and PostDomTree need to call the update function separately on both trees. - People need to construct an additional DeferredDominance class to use functions only receiving DDT. —After the patch— Patch by Chijun Sima <simachijun@gmail.com>. Reviewers: kuhar, brzycki, dmgreen, grosser, davide Reviewed By: kuhar, brzycki Subscribers: vsk, mgorny, llvm-commits Author: NutshellySima Differential Revision: https://reviews.llvm.org/D48383 llvm-svn: 336114
* Implement strip.invariant.groupPiotr Padlewski2018-07-021-1/+2
| | | | | | | | | | | | | | | | Summary: This patch introduce new intrinsic - strip.invariant.group that was described in the RFC: Devirtualization v2 Reviewers: rsmith, hfinkel, nlopes, sanjoy, amharc, kuhar Subscribers: arsenm, nhaehnle, JDevlieghere, hiraditya, xbolva00, llvm-commits Differential Revision: https://reviews.llvm.org/D47103 Co-authored-by: Krzysztof Pszeniczny <krzysztof.pszeniczny@gmail.com> llvm-svn: 336073
* [X86] Remove masking from avx512 rotate intrinsics. Use select in IR instead.Craig Topper2018-06-301-0/+64
| | | | llvm-svn: 336035
* [LLVMContext] Detecting leaked instructions with metadataVedant Kumar2018-06-291-0/+8
| | | | | | | | | | When instructions with metadata are accidentally leaked, the result is a difficult-to-find memory corruption in ~LLVMContextImpl that leads to random crashes. Patch by Arvīds Kokins! llvm-svn: 336010
* [X86] Remove masking from the avx512 packed sqrt intrinsics. Use select in ↵Craig Topper2018-06-291-8/+15
| | | | | | | | IR instead. While there improve the coverage of the intrinsic testing and add fast-isel tests. llvm-svn: 335944
* Revert "Add support for generating a call graph profile from Branch ↵Benjamin Kramer2018-06-281-20/+0
| | | | | | | | Frequency Info." This reverts commits r335794 and r335797. Breaks ThinLTO+FDO selfhost. llvm-svn: 335851
* Add support for generating a call graph profile from Branch Frequency Info.Michael J. Spencer2018-06-271-0/+20
| | | | | | | | | | | | | | | | | | | | | === Generating the CG Profile === The CGProfile module pass simply gets the block profile count for each BB and scans for call instructions. For each call instruction it adds an edge from the current function to the called function with the current BB block profile count as the weight. After scanning all the functions, it generates an appending module flag containing the data. The format looks like: ``` !llvm.module.flags = !{!0} !0 = !{i32 5, !"CG Profile", !1} !1 = !{!2, !3, !4} ; List of edges !2 = !{void ()* @a, void ()* @b, i64 32} ; Edge from a to b with a weight of 32 !3 = !{void (i1)* @freq, void ()* @a, i64 11} !4 = !{void (i1)* @freq, void ()* @b, i64 20} ``` Differential Revision: https://reviews.llvm.org/D48105 llvm-svn: 335794
* [X86] Rename the autoupgraded of packed fp compare and fpclass intrinsics ↵Craig Topper2018-06-271-111/+65
| | | | | | | | that don't take a mask as input to exclude '.mask.' from their name. I think the intrinsics named 'avx512.mask.' should refer to the previous behavior of taking a mask argument in the intrinsic instead of using a 'select' or 'and' instruction in IR to accomplish the masking. This is more consistent with the goal that eventually we will have no intrinsics that have masking builtin. When we reach that goal, we should have no intrinsics named "avx512.mask". llvm-svn: 335744
* Rename skipDebugInfo -> skipDebugIntrinsics, NFCVedant Kumar2018-06-261-1/+1
| | | | | | | | | | | | | This addresses post-commit feedback about the name 'skipDebugInfo' being misleading. This name could be interpreted as meaning 'a function that skips instructions with debug locations'. The new name, 'skipDebugIntrinsics', makes it clear that this function only skips debug info intrinsics. Thanks to Adrian Prantl for pointing this out! llvm-svn: 335667
* ConstantFold: Don't fold global address vs. null for addrspace != 0Matt Arsenault2018-06-261-3/+6
| | | | | | | | | | | Not sure why this logic seems to be repeated in 2 different places, one called by the other. On AMDGPU addrspace(3) globals start allocating at 0, so these checks will be incorrect (not that real code actually tries to compare these addresses) llvm-svn: 335649
* [ConstantRange] Add support of mul in makeGuaranteedNoWrapRegion.Tim Shen2018-06-261-0/+58
| | | | | | | | | | | | Summary: This is trying to add support for r334428. Reviewers: sanjoy Subscribers: jlebar, hiraditya, bixia, llvm-commits Differential Revision: https://reviews.llvm.org/D48399 llvm-svn: 335646
* Improve ConvertDebugDeclareToDebugValueBjorn Pettersson2018-06-261-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is a follow-up to r334830 and r335031. In the valueCoversEntireFragment check we now also handle the situation when there is a variable length array (VLA) involved, and the length of the array has been reduced to a constant. The ConvertDebugDeclareToDebugValue functions that are related to PHI nodes and load instructions now avoid inserting dbg.value intrinsics when the value does not, for certain, cover the variable/fragment that should be described. In r334830 we assumed that the value always covered the entire var/fragment and we had assertions in the code to show that assumption. However, those asserts failed when compiling code with VLAs, so we removed the asserts in r335031. Now when we know that the valueCoversEntireFragment check can fail also for PHI/Load instructions we avoid to insert the faulty dbg.value intrinsic in such situations. Compared to the Store instruction scenario we simply drop the dbg.value here (as the variable does not change its value due to PHI/Load, so an earlier dbg.value describing the variable should still be valid). Reviewers: aprantl, vsk, efriedma Reviewed By: aprantl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D48547 llvm-svn: 335580
* [X86] Redefine avx512 packed fpclass intrinsics to return a vXi1 mask and ↵Craig Topper2018-06-261-0/+43
| | | | | | | | | | | | implement the mask input argument using an 'and' IR instruction. This recommits r335562 and 335563 as a single commit. The frontend will surround the intrinsic with the appropriate marshalling to/from a scalar type to match the sigature of the builtin that software expects. By exposing the vXi1 type directly in the llvm intrinsic we make it available to optimizers much earlier. This can enable the scalar marshalling code to be optimized away. llvm-svn: 335568
* Revert r335562 and 335563 "[X86] Redefine avx512 packed fpclass intrinsics ↵Craig Topper2018-06-261-43/+0
| | | | | | | | to return a vXi1 mask and implement the mask input argument using an 'and' IR instruction." These were supposed to have been squashed to a single commit. llvm-svn: 335566
* fooCraig Topper2018-06-261-0/+43
| | | | llvm-svn: 335562
* SafepointIRVerifier should ignore dead blocks and dead edgesArtur Pilipenko2018-06-251-28/+189
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not only should SafepointIRVerifier ignore unreachable blocks (as suggested in https://reviews.llvm.org/D47011) but it also has to ignore dead blocks. In @test2 (see the new tests): br i1 true, label %right, label %left left: ... right: ... merge: %val = phi i8 addrspace(1)* [ ..., %left ], [ ..., %right ] use %val both left and right branches are reachable. If they collide then SafepointIRVerifier reports an error. Because of the foldable branch condition GVN finds the left branch dead and removes the phi node entry that merges values from right and left. Then the use comes from the right branch. This results in no collision. So, SafepointIRVerifier ends up in different results depending on either GVN is run or not. To solve this issue this patch adds Dead Block detection to SafepointIRVerifier which can ignore dead blocks while validating IR. The Dead Block detection algorithm is taken from GVN but modified to not split critical edges. That is needed to keep CFG unchanged by SafepointIRVerifier. Patch by Yevgeny Rouban. Reviewed By: anna, apilipenko, DaniilSuchkov Differential Revision: https://reviews.llvm.org/D47441 llvm-svn: 335473
* [IR] Split Intrinsics.inc into enums and implementationsReid Kleckner2018-06-231-7/+7
| | | | | | | | | | | | | | | | | | | Implements PR34259 Intrinsics.h is a very popular header. Most LLVM TUs care about things like dbg_value, but they don't care how they are implemented. After I split these out, IntrinsicImpl.inc is 1.7 MB, so this saves each LLVM TU from scanning 1.7 MB of source that gets pre-processed away. It also means we can modify intrinsic properties without triggering a full rebuild, but that's probably less of a win. I think the next best thing to do would be to split out the target intrinsics into their own header. Very, very few TUs care about target-specific intrinsics. It's very hard to split up the target independent intrinsics like llvm.expect, assume, and dbg.value, though. llvm-svn: 335407
* [IR] Use Instruction::isBinaryOp helper instead of raw enum range tests. NFCI.Simon Pilgrim2018-06-222-6/+3
| | | | llvm-svn: 335335
* Revert r335306 (and r335314) - the Call Graph Profile pass.Chandler Carruth2018-06-221-20/+0
| | | | | | | | | | | This is the first pass in the main pipeline to use the legacy PM's ability to run function analyses "on demand". Unfortunately, it turns out there are bugs in that somewhat-hacky approach. At the very least, it leaks memory and doesn't support -debug-pass=Structure. Unclear if there are larger issues or not, but this should get the sanitizer bots back to green by fixing the memory leaks. llvm-svn: 335320
* [Instrumentation] Add Call Graph Profile passMichael J. Spencer2018-06-211-0/+20
| | | | | | | | | | | | | | | | | | | | This patch adds support for generating a call graph profile from Branch Frequency Info. The CGProfile module pass simply gets the block profile count for each BB and scans for call instructions. For each call instruction it adds an edge from the current function to the called function with the current BB block profile count as the weight. After scanning all the functions, it generates an appending module flag containing the data. The format looks like: !llvm.module.flags = !{!0} !0 = !{i32 5, !"CG Profile", !1} !1 = !{!2, !3, !4} ; List of edges !2 = !{void ()* @a, void ()* @b, i64 32} ; Edge from a to b with a weight of 32 !3 = !{void (i1)* @freq, void ()* @a, i64 11} !4 = !{void (i1)* @freq, void ()* @b, i64 20} Differential Revision: https://reviews.llvm.org/D48105 llvm-svn: 335306
* [X86] Remove masking from 512-bit floating max/min intrinsics. Use select ↵Craig Topper2018-06-211-12/+32
| | | | | | instruction instead. llvm-svn: 335199
* [IR] add/use isIntDivRem convenience functionSanjay Patel2018-06-201-3/+1
| | | | | | | | There are more existing potential users of this, but I've limited this patch to the first couple that I found to minimize typo risk. llvm-svn: 335157
* [IR] Introduce helpers to skip debug instructions (NFC)Vedant Kumar2018-06-192-0/+14
| | | | | | | | | | | | | | | | | | | | | | | This patch introduces two helpers to make it easier to ignore debug intrinsics: - Instruction::getNextNonDebugInstruction() This is just like Instruction::getNextNode(), except that it skips debug info. - skipDebugInfo(BasicBlock::iterator) A free function which advances a BasicBlock iterator past any debug info. This is a no-op when the iterator already points to a non-debug instruction. Part of: llvm.org/PR37728 Related to: https://reviews.llvm.org/D47874 Differential Revision: https://reviews.llvm.org/D48305 llvm-svn: 335083
* [IR] move shuffle mask queries from TTI to ShuffleVectorInstSanjay Patel2018-06-191-2/+104
| | | | | | | | | | | | | | | | The optimizer is getting smarter (eg, D47986) about differentiating shuffles based on its mask values, so we should make queries on the mask constant operand generally available to avoid code duplication. We'll probably use this soon in the vectorizers and instcombine (D48023 and https://bugs.llvm.org/show_bug.cgi?id=37806). We might clean up TTI a bit more once all of its current 'SK_*' options are covered. Differential Revision: https://reviews.llvm.org/D48236 llvm-svn: 335067
* [X86] Lowering sqrt intrinsics to native IRTomasz Krupa2018-06-151-0/+32
| | | | | | | | | | | | | | Summary: Complementary patch to lowering sqrt intrinsics in Clang. Reviewers: craig.topper, spatel, RKSimon, DavidKreitzer, uriel.k Reviewed By: craig.topper Subscribers: tkrupa, mike.dvoretsky, llvm-commits Differential Revision: https://reviews.llvm.org/D41599 llvm-svn: 334849
* Re-apply "[DebugInfo] Check size of variable in ConvertDebugDeclareToDebugValue"Bjorn Pettersson2018-06-151-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is r334704 (which was reverted in r334732) with a fix for types like x86_fp80. We need to use getTypeAllocSizeInBits and not getTypeStoreSizeInBits to avoid dropping debug info for such types. Original commit msg: > Summary: > Do not convert a DbgDeclare to DbgValue if the store > instruction only refer to a fragment of the variable > described by the DbgDeclare. > > Problem was seen when for example having an alloca for an > array or struct, and there were stores to individual elements. > In the past we inserted a DbgValue intrinsics for each store, > just as if the store wrote the whole variable. > > When handling store instructions we insert a DbgValue that > indicates that the variable is "undefined", as we do not know > which part of the variable that is updated by the store. > > When ConvertDebugDeclareToDebugValue is used with a load/phi > instruction we assert that the referenced value is large enough > to cover the whole variable. Afaict this should be true for all > scenarios where those methods are used on trunk. If the assert > blows in the future I guess we could simply skip to insert a > dbg.value instruction. > > In the future I think we should examine which part of the variable > that is accessed, and add a DbgValue instrinsic with an appropriate > DW_OP_LLVM_fragment expression. > > Reviewers: dblaikie, aprantl, rnk > > Reviewed By: aprantl > > Subscribers: JDevlieghere, llvm-commits > > Tags: #debug-info > > Differential Revision: https://reviews.llvm.org/D48024 llvm-svn: 334830
* Make uitofp and sitofp defined on overflow.Eli Friedman2018-06-141-7/+2
| | | | | | | | | | | IEEE 754 defines the expected result on overflow. As far as I know, hardware implementations (of f16), and compiler-rt (__floatuntisf) correctly return +-Inf on overflow. And I can't think of any useful transform that would take advantage of overflow being undefined here. Differential Revision: https://reviews.llvm.org/D47807 llvm-svn: 334777
* Revert rL334704: "[DebugInfo] Check size of variable in ↵Bjorn Pettersson2018-06-141-7/+0
| | | | | | | | | | ConvertDebugDeclareToDebugValue" This reverts commit r334704. Buildbots detected an assertion in "test tsan in debug compiler-rt build". llvm-svn: 334732
* [DebugInfo] Check size of variable in ConvertDebugDeclareToDebugValueBjorn Pettersson2018-06-141-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Do not convert a DbgDeclare to DbgValue if the store instruction only refer to a fragment of the variable described by the DbgDeclare. Problem was seen when for example having an alloca for an array or struct, and there were stores to individual elements. In the past we inserted a DbgValue intrinsics for each store, just as if the store wrote the whole variable. When handling store instructions we insert a DbgValue that indicates that the variable is "undefined", as we do not know which part of the variable that is updated by the store. When ConvertDebugDeclareToDebugValue is used with a load/phi instruction we assert that the referenced value is large enough to cover the whole variable. Afaict this should be true for all scenarios where those methods are used on trunk. If the assert blows in the future I guess we could simply skip to insert a dbg.value instruction. In the future I think we should examine which part of the variable that is accessed, and add a DbgValue instrinsic with an appropriate DW_OP_LLVM_fragment expression. Reviewers: dblaikie, aprantl, rnk Reviewed By: aprantl Subscribers: JDevlieghere, llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D48024 llvm-svn: 334704
* Reland: [Timers] Use the pass argument name for JSON keys in time-passesFrancis Visoiu Mistrih2018-06-131-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using clang --save-stats -mllvm -time-passes, both timers and stats end up in the same json file. We could end up with things like: { "asm-printer.EmittedInsts": 1, "time.pass.Virtual Register Map.wall": 2.9015541076660156e-04, "time.pass.Virtual Register Map.user": 2.0500000000000379e-04, "time.pass.Virtual Register Map.sys": 8.5000000000001741e-05, } This patch makes use of the pass argument name (if available) in the JSON key to end up with things like: { "asm-printer.EmittedInsts": 1, "time.pass.virtregmap.wall": 2.9015541076660156e-04, "time.pass.virtregmap.user": 2.0500000000000379e-04, "time.pass.virtregmap.sys": 8.5000000000001741e-05, } This also helps avoiding to write another JSON printer to handle all the cases that we could have in our pass names. Fixed test instead of adding a new one originally from r334649. Differential Revision: https://reviews.llvm.org/D48109 llvm-svn: 334657
* Revert r334649 "[Timers] Use the pass argument name for JSON keys in ↵Francis Visoiu Mistrih2018-06-131-5/+1
| | | | | | | | | | time-passes" This reverts commit r334649. This breaks a test. llvm-svn: 334651
* [Timers] Use the pass argument name for JSON keys in time-passesFrancis Visoiu Mistrih2018-06-131-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using clang --save-stats -mllvm -time-passes, both timers and stats end up in the same json file. We could end up with things like: { "asm-printer.EmittedInsts": 1, "time.pass.Virtual Register Map.wall": 2.9015541076660156e-04, "time.pass.Virtual Register Map.user": 2.0500000000000379e-04, "time.pass.Virtual Register Map.sys": 8.5000000000001741e-05, } This patch makes use of the pass argument name (if available) in the JSON key to end up with things like: { "asm-printer.EmittedInsts": 1, "time.pass.virtregmap.wall": 2.9015541076660156e-04, "time.pass.virtregmap.user": 2.0500000000000379e-04, "time.pass.virtregmap.sys": 8.5000000000001741e-05, } This also helps avoiding to write another JSON printer to handle all the cases that we could have in our pass names. Differential Revision: https://reviews.llvm.org/D48109 llvm-svn: 334649
* [X86] Remove masking from avx512vbmi2 concat and shift by immediate ↵Craig Topper2018-06-131-0/+44
| | | | | | intrinsics. Use select in IR instead. llvm-svn: 334576
* [X86] Remove masking from dbpsadbw intrinsics, use select in IR instead.Craig Topper2018-06-111-0/+10
| | | | llvm-svn: 334384
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