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path: root/llvm/lib/ExecutionEngine/Orc/OrcABISupport.cpp
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* [ORC][MIPS] Fill delay-slot after `jr` instructionSimon Atanasyan2019-01-121-5/+5
| | | | | | | | | | MIPS `jr` instruction uses a delay-slot. To escape execution of arbitrary instruction we should either fill the delay-slot by `nop` instruction or swap `jr` instruction and logically preceding instruction. This fix implements the second method to generate a bit more effective code. llvm-svn: 351001
* [ORC][MIPS] Setup t9 register and call function through this registerSimon Atanasyan2019-01-121-11/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS ABI states that every function must be called through jalr $t9. In other words, a function expect that t9 register points to the beginning of its code. A function uses this register to calculate offset to the Global Offset Table and save it to the `gp` register. ``` lui $gp, %hi(_gp_disp) addiu $gp, %lo(_gp_disp) addu $gp, $gp, $t9 ``` If `t9` and as a result `$gp` point to the wrong place the following code loads incorrect value from GOT and passes control to invalid code. ``` lw $v0,%call16(foo)($gp) jalr $t9 ``` OrcMips32 and OrcMips64 writeResolverCode methods pass control to the resolved address, but do not setup `$t9` before the call. The `t9` holds value of the beginning of `resolver` code so any attempts to call routines via GOT failed. This change fixes the problem. The `OrcLazy/hidden-visibility.ll` test starts to pass correctly. Before the change it fails on MIPS because the `exitOnLazyCallThroughFailure` called from the resolver code could not call libc routine `exit` via GOT. Differential Revision: http://reviews.llvm.org/D56058 llvm-svn: 351000
* [ORC] Rename register in the OrcMips64 resolver code comments. NFCSimon Atanasyan2018-12-231-2/+2
| | | | | | | The `fp` and `s8` register names are synonyms. But `fp` better reflects a purpose of the register. llvm-svn: 350023
* [ORC] clang-format OrcMips32 and OrcMips64 code. NFCSimon Atanasyan2018-12-231-24/+16
| | | | llvm-svn: 350022
* [ORC] Remove redundant instruction from MIPS resolver code. NFCSimon Atanasyan2018-12-231-8/+7
| | | | | | It's redundant to restore the `$a3` register twice. llvm-svn: 350021
* [MIPS] ORC JIT supportPetar Jovanovic2018-09-111-0/+455
| | | | | | | | | | | | This patch adds support for ORC JIT for mips/mips64 architecture. In common code $static is changed to __ORCstatic because on MIPS architecture "$" is a reserved character. Patch by Luka Ercegovcevic Differential Revision: https://reviews.llvm.org/D49665 llvm-svn: 341934
* Remove redundant includes from lib/ExecutionEngine.Michael Zolotukhin2017-12-131-1/+0
| | | | llvm-svn: 320621
* [ORC] Fix a typo.Lang Hames2017-09-151-1/+1
| | | | llvm-svn: 313346
* [Orc] Rename OrcArchitectureSupport to OrcABISupport and add Win32 ABI support.Lang Hames2016-05-071-0/+542
This enables lazy JITing on Windows x86-64. Patch by David. Thanks David! llvm-svn: 268845
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