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* drop unneeded config.h includesDylan Noblesmith2011-12-223-3/+0
| | | | llvm-svn: 147197
* Hoisted some loop invariant smallvector lookups out of a MachineLICM loopPete Cooper2011-12-221-1/+3
| | | | llvm-svn: 147127
* Changed MachineLICM to use a worklist list MachineCSE instead of recursion.Pete Cooper2011-12-221-44/+125
| | | | | | Fixes <rdar://problem/10584116> llvm-svn: 147125
* Revert patch from 147090. There is not point to make code less readable if weJakub Staszak2011-12-211-43/+45
| | | | | | don't get any serious benefit there. llvm-svn: 147101
* - Change a few operator[] to lookup which is cheaper.Jakub Staszak2011-12-211-45/+43
| | | | | | - Add some constantness. llvm-svn: 147090
* Oops - LiveIntervalUnion.cpp file does use std::find. Moving STL header ↵Lang Hames2011-12-211-0/+2
| | | | | | include to LiveIntervalUnion.cpp file. llvm-svn: 147089
* Remove disused STL header include.Lang Hames2011-12-211-2/+0
| | | | llvm-svn: 147088
* Move common code into an MRI function.Jakob Stoklund Olesen2011-12-212-14/+5
| | | | llvm-svn: 147071
* Fix assert condition.Lang Hames2011-12-201-1/+1
| | | | llvm-svn: 146987
* Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo.Jakub Staszak2011-12-205-9/+20
| | | | llvm-svn: 146986
* Fix up the CMake build for the new files added in r146960, they'reChandler Carruth2011-12-201-0/+2
| | | | | | likely to stay either way that discussion ends up resolving itself. llvm-svn: 146966
* Unweaken vtables as per ↵David Blaikie2011-12-2014-1/+49
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Add basic generic CodeGen support for half.Dan Gohman2011-12-202-17/+39
| | | | llvm-svn: 146927
* Add a if-conversion optimization that allows 'true' side of a diamond to beEvan Cheng2011-12-191-5/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | unpredicated. That is, turn subeq r0, r1, #1 addne r0, r1, #1 into sub r0, r1, #1 addne r0, r1, #1 For targets where conditional instructions are always executed, this may be beneficial. It may remove pseudo anti-dependency in out-of-order execution CPUs. e.g. op r1, ... str r1, [r10] ; end-of-life of r1 as div result cmp r0, #65 movne r1, #44 ; raw dependency on previous r1 moveq r1, #12 If movne is unpredicated, then op r1, ... str r1, [r10] cmp r0, #65 mov r1, #44 ; r1 written unconditionally moveq r1, #12 Both mov and moveq are no longer depdendent on the first instruction. This gives the out-of-order execution engine more freedom to reorder them. This has passed entire LLVM test suite. But it has not been enabled for any ARM variant pending more performance evaluation. rdar://8951196 llvm-svn: 146914
* Attempt to fix PR11607 by shuffling around which class defines which methods.Eli Friedman2011-12-191-5/+5
| | | | llvm-svn: 146897
* Handle sub-register operands in recomputeRegClass().Jakob Stoklund Olesen2011-12-191-4/+6
| | | | | | | | | | | Now that getMatchingSuperRegClass() returns accurate results, it can be used to compute constraints imposed by instructions using a sub-register of a virtual register. This means we can recompute the register class of any virtual register by combining the constraints from all its uses. llvm-svn: 146874
* Allow inlining of functions with returns_twice calls, if they have theJoerg Sonnenberger2011-12-182-2/+2
| | | | | | attribute themselve. llvm-svn: 146851
* Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added theRafael Espindola2011-12-171-3/+2
| | | | | | asm parsing and testcase. llvm-svn: 146801
* Resolve part of a fixme and add a new one.Eric Christopher2011-12-161-2/+5
| | | | llvm-svn: 146784
* Add a fixme here.Eric Christopher2011-12-161-0/+1
| | | | llvm-svn: 146783
* Extraneous whitespace and 80-col.Eric Christopher2011-12-161-3/+2
| | | | llvm-svn: 146780
* Move parts of lib/Target that use CodeGen into lib/CodeGen.Nick Lewycky2011-12-154-0/+129
| | | | llvm-svn: 146702
* Update DebugLoc while merging nodes at -O0.Devang Patel2011-12-152-6/+21
| | | | | | Patch by Kyriakos Georgiou! llvm-svn: 146670
* Don't try to form FGETSIGN after legalization; it is possible in some cases, ↵Eli Friedman2011-12-151-1/+2
| | | | | | but the existing code can't do it correctly. PR11570. llvm-svn: 146630
* Enable synthesis of FLOG2 and FEXP2 SelectionDAG nodes from libm calls. ↵Owen Anderson2011-12-151-0/+22
| | | | | | These are already marked as illegal by default. llvm-svn: 146623
* Move Instruction::isSafeToSpeculativelyExecute out of VMCore andDan Gohman2011-12-141-2/+3
| | | | | | | | | into Analysis as a standalone function, since there's no need for it to be in VMCore. Also, update it to use isKnownNonZero and other goodies available in Analysis, making it more precise, enabling more aggressive optimization. llvm-svn: 146610
* Do not sink instruction, if it is not profitable.Devang Patel2011-12-141-13/+76
| | | | | | | | On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator. Radar 10266272. llvm-svn: 146604
* Reapply r146481 with a fix to create the Builder value in the correct place andBill Wendling2011-12-141-6/+35
| | | | | | | with the correct iterator. <rdar://problem/10530851> llvm-svn: 146600
* Model ARM predicated write as read-mod-write. e.g.Evan Cheng2011-12-141-2/+2
| | | | | | | | | | | r0 = mov #0 r0 = moveq #1 Then the second instruction has an implicit data dependency on the first instruction. Sadly I have yet to come up with a small test case that demonstrate the post-ra scheduler taking advantage of this. llvm-svn: 146583
* llvm/lib/CodeGen: Fix cmake build since r146542.NAKAMURA Takumi2011-12-141-0/+1
| | | | llvm-svn: 146550
* Add missing cases to SDNode::getOperationName(). Patch by Micah Villmow.Eli Friedman2011-12-141-0/+5
| | | | llvm-svn: 146548
* Allow target to specify register output dependency. Still default to one.Evan Cheng2011-12-141-1/+7
| | | | llvm-svn: 146547
* Revert r146481 to review possible miscompilations.Bill Wendling2011-12-141-33/+6
| | | | llvm-svn: 146546
* - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng2011-12-148-51/+297
| | | | | | | | | | to finalize MI bundles (i.e. add BUNDLE instruction and computing register def and use lists of the BUNDLE instruction) and a pass to unpack bundles. - Teach more of MachineBasic and MachineInstr methods to be bundle aware. - Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to prevent IT blocks from being broken apart. llvm-svn: 146542
* DW_AT_virtuality is also defined to be constant, not flag.Nick Lewycky2011-12-141-2/+2
| | | | llvm-svn: 146534
* [fast-isel] Remove SelectInsertValue() as fast-isel wasn't designed to handle Chad Rosier2011-12-131-103/+0
| | | | | | instructions that define aggregate types. llvm-svn: 146492
* Avoid using the 'insertvalue' instruction here.Bill Wendling2011-12-131-6/+33
| | | | | | | | | Fast ISel isn't able to handle 'insertvalue' and it causes a large slowdown during -O0 compilation. We don't necessarily need to generate an aggregate of the values here if they're just going to be extracted directly afterwards. <rdar://problem/10530851> llvm-svn: 146481
* DW_AT_accessibility is "constant" class, not form class, so it may not useNick Lewycky2011-12-131-6/+6
| | | | | | DW_FORM_flag. Use DW_FORM_data1 for one byte. llvm-svn: 146475
* Initial CodeGen support for CTTZ/CTLZ where a zero input produces anChandler Carruth2011-12-137-23/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | undefined result. This adds new ISD nodes for the new semantics, selecting them when the LLVM intrinsic indicates that the undef behavior is desired. The new nodes expand trivially to the old nodes, so targets don't actually need to do anything to support these new nodes besides indicating that they should be expanded. I've done this for all the operand types that I could figure out for all the targets. Owners of various targets, please review and let me know if any of these are incorrect. Note that the expand behavior is *conservatively correct*, and exactly matches LLVM's current behavior with these operations. Ideally this patch will not change behavior in any way. For example the regtest suite finds the exact same instruction sequences coming out of the code generator. That's why there are no new tests here -- all of this is being exercised by the existing test suite. Thanks to Duncan Sands for reviewing the various bits of this patch and helping me get the wrinkles ironed out with expanding for each target. Also thanks to Chris for clarifying through all the discussions that this is indeed the approach he was looking for. That said, there are likely still rough spots. Further review much appreciated. llvm-svn: 146466
* [fast-isel] Guard "exhastive" fast-isel output with -fast-isel-verbose2.Chad Rosier2011-12-131-1/+6
| | | | llvm-svn: 146453
* LLVMBuild: Introduce a common section which currently has a list of theDaniel Dunbar2011-12-121-0/+3
| | | | | | | | | | | subdirectories to traverse into. - Originally I wanted to avoid this and just autoscan, but this has one key flaw in that new subdirectories can not automatically trigger a rerun of the llvm-build tool. This is particularly a pain when switching back and forth between trees where one has added a subdirectory, as the dependencies will tend to be wrong. This will also eliminates FIXME implicitly. llvm-svn: 146436
* Fixed register allocator splitting a live range on a spilling variable.Pete Cooper2011-12-123-4/+25
| | | | | | | | If we create new intervals for a variable that is being spilled, then those new intervals are not guaranteed to also spill. This means that anything reading from the original spilling value might not get the correct value if spills were missed. Fixes <rdar://problem/10546864> llvm-svn: 146428
* LLVMBuild: Remove trailing newline, which irked me.Daniel Dunbar2011-12-123-3/+0
| | | | llvm-svn: 146409
* [fast-isel] SelectInsertValue seems to be causing miscompiles for ARM. ↵Chad Rosier2011-12-101-0/+1
| | | | | | Disable while I investigate. llvm-svn: 146331
* Typo.Chad Rosier2011-12-101-1/+1
| | | | llvm-svn: 146327
* [fast-isel] Add support for selecting insertvalue.Chad Rosier2011-12-091-0/+102
| | | | | | rdar://10530851 llvm-svn: 146276
* Move isUnpredicatedTerminator() default implementation to ↵Evan Cheng2011-12-091-0/+13
| | | | | | TargetInstrInfoImpl to break Target's dependency on CodeGen. llvm-svn: 146247
* Fix comment.Devang Patel2011-12-091-2/+1
| | | | llvm-svn: 146226
* Update stale comment.Devang Patel2011-12-091-4/+1
| | | | llvm-svn: 146220
* Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514.Eli Friedman2011-12-091-4/+3
| | | | llvm-svn: 146219
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