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* Don't crash when we see unallocatable registers in clobbersGeorge Burgess IV2017-10-233-15/+34
| | | | | | | | | | | | | | This fixes a bug where we'd crash given code like the test-case from https://bugs.llvm.org/show_bug.cgi?id=30792 . Instead, we let the offending clobber silently slide through. This doesn't fully fix said bug, since the assembler will still complain the moment it sees a crypto/fp/vector op, and we still don't diagnose calls that require vector regs. Differential Revision: https://reviews.llvm.org/D39030 llvm-svn: 316374
* [MachineOutliner] NFC: Rename getters/setters to fit coding styleJessica Paquette2017-10-231-13/+13
| | | | | | | Rename endIdx, startIdx, and length to getEndIdx, getStartIdx, and getLength in Candidate. llvm-svn: 316341
* [DAGCombine] Permit combining of shuffles of equivalent splat BUILD_VECTORsSimon Pilgrim2017-10-231-5/+15
| | | | | | | | | | combineShuffleOfScalars is very conservative about shuffled BUILD_VECTORs that can be combined together. This patch adds one additional case - if both BUILD_VECTORs represent splats of the same scalar value but with different UNDEF elements, then we should create a single splat BUILD_VECTOR, sharing only the UNDEF elements defined by the shuffle mask. Differential Revision: https://reviews.llvm.org/D38696 llvm-svn: 316331
* Add logic to greedy reg alloc to avoid bad eviction chainsMarina Yatsina2017-10-224-20/+413
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes bugzilla 26810 https://bugs.llvm.org/show_bug.cgi?id=26810 This is intended to prevent sequences like: movl %ebp, 8(%esp) # 4-byte Spill movl %ecx, %ebp movl %ebx, %ecx movl %edi, %ebx movl %edx, %edi cltd idivl %esi movl %edi, %edx movl %ebx, %edi movl %ecx, %ebx movl %ebp, %ecx movl 16(%esp), %ebp # 4 - byte Reload Such sequences are created in 2 scenarios: Scenario #1: vreg0 is evicted from physreg0 by vreg1 Evictee vreg0 is intended for region splitting with split candidate physreg0 (the reg vreg0 was evicted from) Region splitting creates a local interval because of interference with the evictor vreg1 (normally region spliiting creates 2 interval, the "by reg" and "by stack" intervals. Local interval created when interference occurs.) one of the split intervals ends up evicting vreg2 from physreg1 Evictee vreg2 is intended for region splitting with split candidate physreg1 one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills Scenario #2 vreg0 is evicted from physreg0 by vreg1 vreg2 is evicted from physreg2 by vreg3 etc Evictee vreg0 is intended for region splitting with split candidate physreg1 Region splitting creates a local interval because of interference with the evictor vreg1 one of the split intervals ends up evicting back original evictor vreg1 from physreg0 (the reg vreg0 was evicted from) Another evictee vreg2 is intended for region splitting with split candidate physreg1 one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills As compile time was a concern, I've added a flag to control weather we do cost calculations for local intervals we expect to be created (it's on by default for X86 target, off for the rest). Differential Revision: https://reviews.llvm.org/D35816 Change-Id: Id9411ff7bbb845463d289ba2ae97737a1ee7cc39 llvm-svn: 316295
* [SelectionDAG] Use dyn_cast without cast.Florian Hahn2017-10-211-2/+2
| | | | llvm-svn: 316258
* [SelectionDAG] Use isa to silence unused variable warning (NFC).Florian Hahn2017-10-211-1/+1
| | | | llvm-svn: 316257
* [SelectionDAG] Don't subject ConstantSDNodes to the depth limit in ↵Craig Topper2017-10-211-10/+13
| | | | | | | | computeKnownBits and ComputeNumSignBits. We don't need to do any additional recursion, we just need to analyze the APInt stored in the node. This matches what the ValueTracking versions do for IR. llvm-svn: 316256
* [SelectionDAG] Don't subject ISD:Constant to the depth limit in ↵Craig Topper2017-10-211-5/+7
| | | | | | | | | | | | | | | | | | | TargetLowering::SimplifyDemandedBits. Summary: We shouldn't recurse any further but it doesn't mean we shouldn't be able to give the known bits for a constant. The caller would probably like that we always return the right answer for a constant RHS. This matches what InstCombine does in this case. I don't have a test case because this showed up while trying to revive D31724. Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: arsenm, llvm-commits Differential Revision: https://reviews.llvm.org/D38967 llvm-svn: 316255
* [Packetizer] Add function to check for aliasing between instructionsKrzysztof Parzyszek2017-10-201-0/+32
| | | | llvm-svn: 316243
* [WebAssembly] MC: Fix crash when -g specified.Sam Clegg2017-10-201-8/+5
| | | | | | | | | At this point we don't output any debug sections or thier relocations. Differential Revision: https://reviews.llvm.org/D39076 llvm-svn: 316240
* [SelectionDAG] Add a check to getVectorShuffle to ensure that the only ↵Craig Topper2017-10-191-1/+2
| | | | | | negative index we allow is -1. llvm-svn: 316183
* Untabify.NAKAMURA Takumi2017-10-181-1/+1
| | | | llvm-svn: 316079
* [MachineOutliner][NFC] Clean up prune logic a bitJessica Paquette2017-10-171-33/+36
| | | | | | | | Move the prune logic in pruneOverlaps to a new function, prune. This lets us reuse the prune functionality. Makes the code a bit more readable. It'll also make it easier to emit remarks/debug statements for pruned functions. llvm-svn: 316031
* [MachineOutliner][NFC] Move decrement logic to OutlinedFunctionJessica Paquette2017-10-171-16/+26
| | | | | | | | | | | This commit moves the decrement logic for outlined functions into the class, and makes OccurrenceCount private. It can now be accessed via getOccurrenceCount(). This makes it more difficult to accidentally introduce bugs by incorrectly decrementing the occurrence count on OutlinedFunctions. llvm-svn: 316020
* [MachineOutliner][NFC] Move end index calculation into CandidateJessica Paquette2017-10-171-20/+31
| | | | | | | | Cleanup to Candidate that moves all end index calculations into Candidate.endIdx(). For the sake of consistency, StartIdx and Len are now private members, and can be accessed with length() and startIdx() respectively. llvm-svn: 316019
* [DAGCombine] Add SCALAR_TO_VECTOR undef handling to simplifyShuffleMask.Simon Pilgrim2017-10-171-2/+6
| | | | | | | | This allows us to simplify later visitVECTOR_SHUFFLE optimizations such as combineShuffleOfScalars. Noticed whilst working on D38696 llvm-svn: 316017
* Fix implicit null check with negative offsetYichao Yu2017-10-171-1/+1
| | | | | | | | | | | | | | | | | | | | Summary: It seems that negative offset was accidentally allowed in D17967. AFAICT small negative offset should be valid (always raise segfault) on all archs that I'm aware of (especially x86, which is the only one with this optimization enabled) and such case can be useful when loading hiden metadata from an object. However, like the positive side, it should only be done within a certain limit. For now, use the same limit on the positive side for the negative side. A separate option can be added if needs appear. Reviewers: mcrosier, skatkov Reviewed By: skatkov Subscribers: sanjoy, llvm-commits Differential Revision: https://reviews.llvm.org/D38925 llvm-svn: 315991
* Use the return value of UpdateNodeOperands(); in some cases, ↵Mark Searles2017-10-161-1/+1
| | | | | | | | UpdateNodeOperands() modifies the node in-place and using the return value isn’t strictly necessary. However, it does not necessarily modify the node, but may return a resultant node if it already exists in the DAG. See comments in UpdateNodeOperands(). In that case, the return value must be used to avoid such scenarios as an infinite loop (node is assumed to have been updated, so added back to the worklist, and re-processed; however, node hasn’t changed so it is once again passed to UpdateNodeOperands(), assumed modified, added back to worklist; cycle infinitely repeats). Differential Revision: https://reviews.llvm.org/D38466 llvm-svn: 315957
* Add iterator range MachineRegisterInfo::liveins(), adopt users, NFCKrzysztof Parzyszek2017-10-162-8/+7
| | | | llvm-svn: 315927
* [AMDGPU] : revert r315908Alexander Timofeev2017-10-161-12/+10
| | | | llvm-svn: 315916
* [AMDGPU] Prevent Machine Copy Propagation from replacing live copy with the ↵Alexander Timofeev2017-10-161-11/+13
| | | | | | | | dead one Differential revision: https://reviews.llvm.org/D38754 llvm-svn: 315908
* ISel type legalizer: debug messages. NFC.Sjoerd Meijer2017-10-162-4/+17
| | | | | | | | | | | Minor addition and follow up of r314773 and r311533: this adds more debug messages to the type legalizer. For each node, it dumps legalization info for results and operands nodes, rather than just the final legalized node. Differential Revision: https://reviews.llvm.org/D38726 llvm-svn: 315904
* Re-commit r315885: [globalisel][tblgen] Add support for iPTR and implement ↵Daniel Sanders2017-10-161-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | am_unscaled* and am_indexed* Summary: iPTR is a pointer of subtarget-specific size to any address space. Therefore type checks on this size derive the SizeInBits from a subtarget hook. At this point, we can import the simplests G_LOAD rules and select load instructions using them. Further patches will support for the predicates to enable additional loads as well as the stores. The previous commit failed on MSVC due to a failure to convert an initializer_list to a std::vector. Hopefully, MSVC will accept this version. Depends on D37457 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37458 llvm-svn: 315887
* Revert r315885: [globalisel][tblgen] Add support for iPTR and implement ↵Daniel Sanders2017-10-161-18/+0
| | | | | | | | am_unscaled* and am_indexed* MSVC doesn't like one of the constructors. llvm-svn: 315886
* [globalisel][tblgen] Add support for iPTR and implement am_unscaled* and ↵Daniel Sanders2017-10-161-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | am_indexed* Summary: iPTR is a pointer of subtarget-specific size to any address space. Therefore type checks on this size derive the SizeInBits from a subtarget hook. At this point, we can import the simplests G_LOAD rules and select load instructions using them. Further patches will support for the predicates to enable additional loads as well as the stores. Depends on D37457 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37458 llvm-svn: 315885
* Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as ↵Daniel Sanders2017-10-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315869
* Revert r315863: [globalisel][tablegen] Import ComplexPattern when used as an ↵Daniel Sanders2017-10-151-1/+1
| | | | | | | | operator A large number of bots are failing on an ambiguous constructor call. llvm-svn: 315866
* [globalisel][tablegen] Import ComplexPattern when used as an operatorDaniel Sanders2017-10-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315863
* Reverting r315590; it did not include changes for llvm-tblgen, which is ↵Aaron Ballman2017-10-1539-62/+62
| | | | | | | | causing link errors for several people. Error LNK2019 unresolved external symbol "public: void __cdecl `anonymous namespace'::MatchableInfo::dump(void)const " (?dump@MatchableInfo@?A0xf4f1c304@@QEBAXXZ) referenced in function "public: void __cdecl `anonymous namespace'::AsmMatcherEmitter::run(class llvm::raw_ostream &)" (?run@AsmMatcherEmitter@?A0xf4f1c304@@QEAAXAEAVraw_ostream@llvm@@@Z) llvm-tblgen D:\llvm\2017\utils\TableGen\AsmMatcherEmitter.obj 1 llvm-svn: 315854
* [RegisterBankInfo] Cache the getMinimalPhysRegClass informationQuentin Colombet2017-10-132-8/+21
| | | | | | | | | | | | | | | TargetRegisterInfo::getMinimalPhysRegClass is actually pretty expensive because it has to iterate over all the register classes. Cache this information as we need and get it so that we limit its usage. Right now, we heavily rely on it, because this is how we get the mapping for vregs defined by copies from physreg (i.e., the one that are ABI related). Improve compile time by up to 10% for that pass. NFC llvm-svn: 315759
* [Legalizer] Use SmallSetVector instead of SetVector.Quentin Colombet2017-10-131-1/+1
| | | | | | NFC llvm-svn: 315758
* [LegalizerInfo] Don't evaluate end boundary every time through the loopQuentin Colombet2017-10-131-3/+4
| | | | | | | | Match the LLVM coding standard for loop conditions. NFC. llvm-svn: 315757
* [Legalizer] Only allocate the SetVectors once per function.Quentin Colombet2017-10-131-3/+5
| | | | | | | | | | | | Prior to this patch we used to create SetVectors in temporaries that were created and destroyed for each instruction. Now, instead we create and destroyed them only once, but clear the content for each instruction. This speeds up the pass by ~25%. NFC. llvm-svn: 315756
* DAG: Add opcode and source type to isFPExtFreeMatt Arsenault2017-10-131-235/+253
| | | | | | | | This is only currently used for mad/fma transforms. This is the only case where it should be used for AMDGPU, so add an opcode to be sure. llvm-svn: 315740
* DAG: Add flags to dumpsMatt Arsenault2017-10-131-0/+30
| | | | llvm-svn: 315690
* [SelectionDAG] Cleanup the SIGN_EXTEND_INREG handling in computeKnownBits. NFCICraig Topper2017-10-131-26/+14
| | | | | | Use less temporary APInts. Use bit counting more. Don't call getScalarSizeInBits so many places, just capture it once. llvm-svn: 315671
* [SelectionDAG] Fix typo in comment. NFCCraig Topper2017-10-131-1/+1
| | | | llvm-svn: 315670
* [SelectionDAG] Correct the early out in SelectionDAG::getZeroExtendInReg to ↵Craig Topper2017-10-131-1/+1
| | | | | | | | work properly for vector types. I don't know if we ever hit this case or not. Turning it into an assert only fired on expanding some atomic operation in a SystemZ lit test. llvm-svn: 315648
* Add DK_Remark to SMDiagnosticAdam Nemet2017-10-121-0/+3
| | | | | | | | | | | Swift uses SMDiagnostic for diagnostic messages. For https://github.com/apple/swift/pull/12294, we need remark support. I picked the color that clang uses to display them. Differential Revision: https://reviews.llvm.org/D38865 llvm-svn: 315642
* [SelectionDAG] Const-correct the DemandedMask argument to one of the ↵Craig Topper2017-10-121-1/+1
| | | | | | overloads of SimplifyDemandedBits. NFC llvm-svn: 315641
* Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine"Matthias Braun2017-10-125-443/+39
| | | | | | | | | | Reverting to investigate layering effects of MCJIT not linking libCodeGen but using TargetMachine::getNameWithPrefix() breaking the lldb bots. This reverts commit r315633. llvm-svn: 315637
* Deprecate DwarfUnit::addBlockByrefAddress().Adrian Prantl2017-10-121-0/+6
| | | | | | | | | | | | The clang frontend already creates a DIExpression that replicates the logic in addBlockByrefAddress() exactly, thus making this function effectively unreachable. To guard against human error I'm hereby marking the function with an assertion and let it hit the bots before eventually removing it. rdar://problem/31629055 llvm-svn: 315636
* TargetMachine: Merge TargetMachine and LLVMTargetMachineMatthias Braun2017-10-125-39/+443
| | | | | | | | | | | | | | | Merge LLVMTargetMachine into TargetMachine. - There is no in-tree target anymore that just implements TargetMachine but not LLVMTargetMachine. - It should still be possible to stub out all the various functions in case a target does not want to use lib/CodeGen - This simplifies the code and avoids methods ending up in the wrong interface. Differential Revision: https://reviews.llvm.org/D38489 llvm-svn: 315633
* [SelectionDAG] Simplify the ISD::SIGN_EXTEND/ZERO_EXTEND handling to use ↵Craig Topper2017-10-121-25/+11
| | | | | | less temporary APInts by counting bits instead. NFCI llvm-svn: 315628
* [DWARF] Fix bad comparator in sortGlobalExprs.Eli Friedman2017-10-121-7/+12
| | | | | | | | | | | | | | | | | | The comparator passed to std::sort must provide a strict weak ordering; otherwise, the behavior is undefined. Fixes an assertion failure generating debug info for globals split by GlobalOpt. I have a testcase, but not sure how to reduce it, so not included here. (Someone else came up with a testcase, but I can't reproduce the crash with it, presumably because my version of LLVM ends up sorting the array differently.) This isn't really a complete fix (see the FIXME in the patch), but at least it doesn't have undefined behavior. Differential Revision: https://reviews.llvm.org/D38830 llvm-svn: 315619
* Implement custom lowering for ISD::CTTZ_ZERO_UNDEF and ISD::CTTZ.Wei Ding2017-10-121-4/+15
| | | | | | Differential Revision: http://reviews.llvm.org/D37348 llvm-svn: 315610
* [dump] Remove NDEBUG from test to enable dump methods [NFC]Don Hinton2017-10-1239-62/+62
| | | | | | | | | | | | | | | Summary: Add LLVM_FORCE_ENABLE_DUMP cmake option, and use it along with LLVM_ENABLE_ASSERTIONS to set LLVM_ENABLE_DUMP. Remove NDEBUG and only use LLVM_ENABLE_DUMP to enable dump methods. Move definition of LLVM_ENABLE_DUMP from config.h to llvm-config.h so it'll be picked up by public headers. Differential Revision: https://reviews.llvm.org/D38406 llvm-svn: 315590
* MachineInstr: Make isEqual agree with getHashValue in ↵Diana Picus2017-10-121-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MachineInstrExpressionTrait MachineInstr::isIdenticalTo has a lot of logic for dealing with register Defs (i.e. deciding whether to take them into account or ignore them). This logic gets things wrong in some obscure cases, for instance if an operand is not a Def for both the current MI and the one we are comparing to. I'm not sure if it's possible for this to happen for regular register operands, but it may happen in the ARM backend for special operands which use sentinel values for the register (i.e. 0, which is neither a physical register nor a virtual one). This causes MachineInstrExpressionTrait::isEqual (which uses MachineInstr::isIdenticalTo) to return true for the following instructions, which are the same except for the fact that one sets the flags and the other one doesn't: %1114 = ADDrsi %1113, %216, 17, 14, _, def _ %1115 = ADDrsi %1113, %216, 17, 14, _, _ OTOH, MachineInstrExpressionTrait::getHashValue returns different values for the 2 instructions due to the different isDef on the last operand. In practice this means that when trying to add those instructions to a DenseMap, they will be considered different because of their different hash values, but when growing the map we might get an assertion while copying from the old buckets to the new buckets because isEqual misleadingly returns true. This patch makes sure that isEqual and getHashValue agree, by improving the checks in MachineInstr::isIdenticalTo when we are ignoring virtual register definitions (which is what the Trait uses). Firstly, instead of checking isPhysicalRegister, we use !isVirtualRegister, so that we cover both physical registers and sentinel values. Secondly, instead of checking MachineOperand::isReg, we use MachineOperand::isIdenticalTo, which checks isReg, isSubReg and isDef, which are the same values that the hash function uses to compute the hash. Note that the function is symmetric with this change, since if the current operand is not a Def, we check MachineOperand::isIdenticalTo, which returns false if the operands have different isDef's. Differential Revision: https://reviews.llvm.org/D38789 llvm-svn: 315579
* Reinstantiate old/bad deduplication logic that was removed in r315279.Daniel Jasper2017-10-121-0/+10
| | | | | | | | | | | While this shouldn't be necessary anymore, we have cases where we run into the assertion below, i.e. cases with two non-fragment entries for the same variable at different frame indices. This should be fixed, but for now, we should revert to a version that does not trigger asserts. llvm-svn: 315576
* [ScheduleDAGInstrs] fix behavior of getUnderlyingObjectsForCodeGen when no ↵Hiroshi Inoue2017-10-121-10/+17
| | | | | | | | | | | | | | | identifiable object found This patch fixes the bug introduced in https://reviews.llvm.org/D35907; the bug is reported by http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20171002/491452.html. Before D35907, when GetUnderlyingObjects fails to find an identifiable object, allMMOsOkay lambda in getUnderlyingObjectsForInstr returns false and Objects vector is cleared. This behavior is unintentionally changed by D35907. This patch makes the behavior for such case same as the previous behavior. Since D35907 introduced a wrapper function getUnderlyingObjectsForCodeGen around GetUnderlyingObjects, getUnderlyingObjectsForCodeGen is modified to return a boolean value to ask the caller to clear the Objects vector. Differential Revision: https://reviews.llvm.org/D38735 llvm-svn: 315565
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