summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
* Pass the Mangler by reference.Rafael Espindola2014-02-085-35/+37
| | | | | | | It is never null and it is not used in casts, so there is no reason to use a pointer. This matches how we pass TM. llvm-svn: 201025
* Fix a bug with .weak_def_can_be_hidden: Mutable variables cannot use it.Rafael Espindola2014-02-071-0/+12
| | | | | | Thanks to John McCall for noticing it. llvm-svn: 200977
* Refactor logic into a function predicate.Rafael Espindola2014-02-071-14/+19
| | | | | | No functionality change. llvm-svn: 200976
* PGO branch weight: fix PR18752.Manman Ren2014-02-071-5/+4
| | | | | | | Fix a bug triggered in IfConverterTriangle when CvtBB has multiple predecessors by getting the weights before removing a successor. llvm-svn: 200958
* Track register pressure a bit more carefully (weird corner case).Andrew Trick2014-02-061-1/+8
| | | | | | | | | | | | | | | | This solves a problem where a def machine operand has no uses but has not been marked dead. In this case, the initial RP analysis was being extra precise and determining from LiveIntervals the the register was actually dead. This caused us to omit the register from the RP tracker's block live out. That's all good, but the per-instruction summary still accounted for it as a valid def. This could cause an assertion in the tracker later when we underflow pressure. This is from a bug report on an out-of-tree target. It is not reproducible on well-behaved targets. I'm just making an obvious fix without unit test. llvm-svn: 200941
* Remove const_cast for STI when parsing inline asmDavid Peixotto2014-02-061-10/+13
| | | | | | | | | | | | | | | | | | | | | In a previous commit (r199818) we added a const_cast to an existing subtarget info instead of creating a new one so that we could reuse it when creating the TargetAsmParser for parsing inline assembly. This cast was necessary because we needed to reuse the existing STI to avoid generating incorrect code when the inline asm contained mode-switching directives (e.g. .code 16). The root cause of the failure was that there was an implicit sharing of the STI between the parser and the MCCodeEmitter. To fix a different but related issue, we now explicitly pass the STI to the MCCodeEmitter (see commits r200345-r200351). The const_cast is no longer necessary and we can now create a fresh STI for the inline asm parser to use. Differential Revision: http://llvm-reviews.chandlerc.com/D2709 llvm-svn: 200929
* Yet another patch to reduce compile time for small programs:Puyan Lotfi2014-02-061-4/+28
| | | | | | | | | | | | | | | | | | | | | The aim in this patch is to reduce work that VirtRegRewriter needs to do when telling MachineRegisterInfo which physregs are in use. Up until now VirtRegRewriter::rewrite has been doing rewriting and populating def info and then proceeding to set whether a physreg is used based this info for every physreg that the target provides. This can be expensive when a target has an unusually high number of supported physregs, and is a noticeable chunk of compile time for small programs on such targets. So to reduce compile time, this patch simply adds the use of a SparseSet to the rewrite function that is used to flag each physreg that is encountered in a MachineFunction. Afterward, rather than iterating over the set of all physregs for a given target to set the physregs used in MachineRegisterInfo, the new way is to iterate over the set of physregs that were actually encountered and set in the SparseSet. This improves compile time because the existing rewrite function was iterating over all MachineOperands already, and because the iterations afterward to setPhysRegUsed is reduced by use of the SparseSet data. llvm-svn: 200919
* The following patch' purpose is to reduce compile time for compilation of smallPuyan Lotfi2014-02-062-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | | programs on targets with large register files. The root of the compile time overhead was in the use of llvm::SmallVector to hold PhysRegEntries, which resulted in slow-down from calling llvm::SmallVector::assign(N, 0). In contrast std::vector uses the faster __platform_bzero to zero out primitive buffers when assign is called, while SmallVector uses an iterator. The fix for this was simply to replace the SmallVector with a dynamically allocated buffer and to initialize or reinitialize the buffer based on the total registers that the target architecture requires. The changes support cases where a pass manager may be reused for different targets, and note that the PhysRegEntries is allocated using calloc mainly for good for, and also to quite tools like Valgrind (see comments for more info on this). There is an rdar to track the fact that SmallVector doesn't have platform specific speedup optimizations inside of it for things like this, and I'll create a bugzilla entry at some point soon as well. TL;DR: This fix replaces the expensive llvm::SmallVector<unsigned char>::assign(N, 0) with a call to calloc for N bytes which is much faster because SmallVector's assign uses iterators. llvm-svn: 200917
* This small change reduces compile time for small programs on targets that havePuyan Lotfi2014-02-061-1/+3
| | | | | | | | | | | large register files. The omission of Queries.clear() is perfectly safe because LiveIntervalUnion::Query doesn't contain any data that needs freeing and because LiveRegMatrix::runOnFunction happens to reset the OwningArrayPtr holding Queries every time it is run, so there's no need to zero out the queries either. Not having to do this for very large numbers of physregs is a noticeable constant cost reduction in compilation of small programs. llvm-svn: 200913
* [DAG] Don't pull the binary operation though the shift if the operands have ↵Juergen Ributzka2014-02-061-2/+9
| | | | | | | | | | | | opaque constants. During DAGCombine visitShiftByConstant assumes that certain binary operations with only constant operands can always be folded successfully. This is no longer true when the constant is opaque. This commit fixes visitShiftByConstant by not performing the optimization for opaque constants. Otherwise we would end up in an infinite DAGCombine loop. llvm-svn: 200900
* Pass address space to allowsUnalignedMemoryAccessesMatt Arsenault2014-02-053-11/+25
| | | | llvm-svn: 200888
* Add address space argument to allowsUnalignedMemoryAccess.Matt Arsenault2014-02-051-1/+1
| | | | | | | On R600, some address spaces have more strict alignment requirements than others. llvm-svn: 200887
* [RegAlloc] Add a last chance recoloring mechanism when everything else failed toQuentin Colombet2014-02-051-8/+263
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | find a register. The idea is to choose a color for the variable that cannot be allocated and recolor its interferences around. Unlike the current register allocation scheme, it is allowed to change the color of an already assigned (but maybe not splittable or spillable) live interval while propagating this change to its neighbors. In other word, there are two things that may help finding an available color: - Already assigned variables (RS_Done) can be recolored to different color. - The recoloring allows to catch solutions that needs to touch more that just the neighbors of the current allocated variable. E.g., vA can use {R1, R2 } vB can use { R2, R3} vC can use {R1 } Where vA, vB, and vC cannot be split anymore (they are reloads for instance) and they all interfere. vA is assigned R1 vB is assigned R2 vC tries to evict vA but vA is already done. => Regular register allocation heuristic fails. Last chance recoloring kicks in: vC does as if vA was evicted => vC uses R1. vC is marked as fixed. vA needs to find a color. None are available. vA cannot evict vC: vC is a fixed virtual register now. vA does as if vB was evicted => vA uses R2. vB needs to find a color. R3 is available. Recoloring => vC = R1, vA = R2, vB = R3. <rdar://problem/15947839> llvm-svn: 200883
* Remove support for not using .loc directives.Rafael Espindola2014-02-053-11/+6
| | | | | | Clang itself was not using this. The only way to access it was via llc. llvm-svn: 200862
* Add CheckChildInteger to ISelMatcher operations. Removes nearly 2000 bytes ↵Craig Topper2014-02-051-2/+23
| | | | | | from X86 matcher table. llvm-svn: 200821
* Use the default values.Rafael Espindola2014-02-041-1/+1
| | | | llvm-svn: 200781
* RegAllocGreedy.cpp: Use more simple value as Hysteresis, to suppress ↵NAKAMURA Takumi2014-02-041-1/+1
| | | | | | -mfpmath-dependent behavior. llvm-svn: 200738
* DebugInfo: Remove some unneeded conditionals now that DIBuilder no longer ↵David Blaikie2014-02-042-6/+3
| | | | | | | | | | | emits zero-length arrays as {i32 0} A bunch of test cases needed to be cleaned up for this, many my fault - when implementid imported modules I updated test cases by simply duplicating the prior metadata field - which wasn't always the empty metadata entry. llvm-svn: 200731
* Expand vector bswap in LegalizeVectorOpsHal Finkel2014-02-031-0/+1
| | | | | | | ISD::BSWAP was missing from the list of node types that should be expanded element-wise. llvm-svn: 200705
* Remove some unused #includesEli Bendersky2014-02-011-1/+0
| | | | llvm-svn: 200611
* [stackprotector] Implement the sspstrong rules for stack layout.Josh Magee2014-02-012-0/+22
| | | | | | | | | | | | | | | | | | This changes the PrologueEpilogInserter and LocalStackSlotAllocation passes to follow the extended stack layout rules for sspstrong and sspreq. The sspstrong layout rules are: 1. Large arrays and structures containing large arrays (>= ssp-buffer-size) are closest to the stack protector. 2. Small arrays and structures containing small arrays (< ssp-buffer-size) are 2nd closest to the protector. 3. Variables that have had their address taken are 3rd closest to the protector. Differential Revision: http://llvm-reviews.chandlerc.com/D2546 llvm-svn: 200601
* Implement inalloca codegen for x86 with the new inalloca designReid Kleckner2014-01-312-2/+25
| | | | | | | | | | | | | | | | Calls with inalloca are lowered by skipping all stores for arguments passed in memory and the initial stack adjustment to allocate argument memory. Now the frontend is responsible for the memory layout, and the backend doesn't have to do any work. As a result these changes are pretty minimal. Reviewers: echristo Differential Revision: http://llvm-reviews.chandlerc.com/D2637 llvm-svn: 200596
* Don't put non-static allocas in the static alloca mapReid Kleckner2014-01-311-1/+7
| | | | | | | | Allocas marked inalloca are never static, but we were trying to put them into the static alloca map if they were in the entry block. Also add an assertion in x86 fastisel. llvm-svn: 200593
* Remove a redundant call to hasRawTextSupport.Rafael Espindola2014-01-311-1/+1
| | | | | | The code path it was guarding was already using emitRawComment. llvm-svn: 200591
* If we're not producing DWARF accel tables, don't waste memoryPaul Robinson2014-01-311-0/+4
| | | | | | keeping track of those entries. llvm-svn: 200572
* Add support for DW_FORM_flag and DW_FORM_flag_present to the DIE hashingEric Christopher2014-01-311-10/+19
| | | | | | | | algorithm. Sink the 'A' + Attribute hash into each form so we don't have to check valid forms before deciding whether or not we're going to hash which will let the default be to return without doing anything. llvm-svn: 200571
* DebugInfo: Flag type unit references as declarationsDavid Blaikie2014-01-311-0/+5
| | | | | | | | | This ensures DWARF consumers don't confuse these references for definitions. I'd argue it might be nice to improve debuggers so we don't need this, but it's just one field in an abbreviation anyway - so it doesn't seem worth the fight. llvm-svn: 200569
* This patch teaches the DAGCombiner how to fold insert_subvector nodesManman Ren2014-01-311-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when the input is a concat_vectors and the insert replaces one of the concat halves: Lower half: fold (insert_subvector (concat_vectors X, Y), Z) -> (concat_vectors Z, Y) Upper half: fold (insert_subvector (concat_vectors X, Y), Z) -> (concat_vectors X, Z) This can be seen with the following IR: define <8 x float> @lower_half(<4 x float> %v1, <4 x float> %v2, <4 x float> %v3) { %1 = shufflevector <4 x float> %v1, <4 x float> %v2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %2 = tail call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %1, <4 x float> %v3, i8 0) The vinsertf128 intrinsic is converted into an insert_subvector node in SelectionDAGBuilder.cpp. Using AVX, without the patch this generates two vinsertf128 instructions: vinsertf128 $1, %xmm1, %ymm0, %ymm0 vinsertf128 $0, %xmm2, %ymm0, %ymm0 With the patch this is optimized into: vinsertf128 $1, %xmm1, %ymm2, %ymm0 Patch by Robert Lougher. llvm-svn: 200506
* DAGCombine should not produce ISD::OR nodes after operation legalization if ↵Owen Anderson2014-01-311-2/+4
| | | | | | they're not legal. llvm-svn: 200503
* PGO branch weight: update edge weights in SelectionDAGBuilder.Manman Ren2014-01-312-12/+65
| | | | | | | | | | | | | | | | When converting from "or + br" to two branches, or converting from "and + br" to two branches, we correctly update the edge weights of the two branches. The previous attempt at r200431 was reverted at r200434 because of two testing case failures. I modified my patch a little, but forgot to re-run "make check-all". Testing case CodeGen/ARM/lsr-unfolded-offset.ll is updated because of the patch's impact on branch probability which causes changes in spill placement. llvm-svn: 200502
* [Stackmaps] Record the stack size of each function that contains a ↵Juergen Ributzka2014-01-301-0/+24
| | | | | | | | | | stackmap/patchpoint intrinsic. Re-applying the patch, but this time without using AsmPrinter methods. Reviewed by Andy llvm-svn: 200481
* Revert "[Stackmaps] Record the stack size of each function that contains a ↵Juergen Ributzka2014-01-301-24/+0
| | | | | | | | stackmap/patchpoint intrinsic." This reverts commit r200444 to unbreak buildbots. llvm-svn: 200445
* [Stackmaps] Record the stack size of each function that contains a ↵Juergen Ributzka2014-01-301-0/+24
| | | | | | | | stackmap/patchpoint intrinsic. Reviewed by Andy llvm-svn: 200444
* Reland r200340 - 'Add line table debug info to COFF files when using a win32 ↵Timur Iskhodzhanov2014-01-305-28/+490
| | | | | | | | triple' This incorporates a couple of fixes reviewed at http://llvm-reviews.chandlerc.com/D2651 llvm-svn: 200440
* Revert r200431 due to bot failures.Manman Ren2014-01-302-65/+12
| | | | llvm-svn: 200434
* PGO branch weight: update edge weights in SelectionDAGBuilder.Manman Ren2014-01-302-12/+65
| | | | | | | | When converting from "or + br" to two branches, or converting from "and + br" to two branches, we correctly update the edge weights of the two branches. llvm-svn: 200431
* PGO branch weight: update edge weights in IfConverter.Manman Ren2014-01-292-0/+54
| | | | | | | | | | | | | This commit only handles IfConvertTriangle. To update edge weights of a successor, one interface is added to MachineBasicBlock: /// Set successor weight of a given iterator. setSuccWeight(succ_iterator I, uint32_t weight) An existing testing case test/CodeGen/Thumb2/v8_IT_5.ll is updated, since we now correctly update the edge weights, the cold block is placed at the end of the function and we jump to the cold block. llvm-svn: 200428
* Move range handling for a function to endFunction rather thanEric Christopher2014-01-291-5/+5
| | | | | | when we create the subprogram DIE. llvm-svn: 200426
* If we use DW_AT_ranges we need to specify a base address that rangesEric Christopher2014-01-291-2/+8
| | | | | | | | are relative to in the compile unit. Currently let's just use 0... Thanks to Greg Clayton for the catch! llvm-svn: 200425
* Turn on CU ranges if we've got multiple compile units in the sameEric Christopher2014-01-291-4/+6
| | | | | | | | module since there's no range guarantee that we could make given output order. This also fixes up the testcases that have multiple CUs to have the correct range offset. llvm-svn: 200422
* Make the compile unit map a MapVector so that we can assume a stableEric Christopher2014-01-292-3/+5
| | | | | | output ordering. llvm-svn: 200421
* Fix formatting of comment.Eric Christopher2014-01-291-4/+2
| | | | llvm-svn: 200420
* Enable EHABI by defaultRenato Golin2014-01-291-22/+14
| | | | | | | | | | | | | | | | | | | | | | After all hard work to implement the EHABI and with the test-suite passing, it's time to turn it on by default and allow users to disable it as a work-around while we fix the eventual bugs that show up. This commit also remove the -arm-enable-ehabi-descriptors, since we want the tables to be printed every time the EHABI is turned on for non-Darwin ARM targets. Although MCJIT EHABI is not working yet (needs linking with the right libraries), this commit also fixes some relocations on MCJIT regarding the EH tables/lib calls, and update some tests to avoid using EH tables when none are needed. The EH tests in the test-suite that were previously disabled on ARM now pass with these changes, so a follow-up commit on the test-suite will re-enable them. llvm-svn: 200388
* Revert r200340, "Add line table debug info to COFF files when using a win32 ↵NAKAMURA Takumi2014-01-295-480/+28
| | | | | | | | triple." It was incompatible with --target=i686-win32. llvm-svn: 200375
* Change MCStreamer EmitInstruction interface to take subtarget infoDavid Woodhouse2014-01-281-1/+10
| | | | llvm-svn: 200345
* Add line table debug info to COFF files when using a win32 triple.Timur Iskhodzhanov2014-01-285-28/+480
| | | | | | Reviewed at http://llvm-reviews.chandlerc.com/D2232 llvm-svn: 200340
* typoAdrian Prantl2014-01-281-1/+1
| | | | llvm-svn: 200323
* [DAGCombiner] Avoid introducing an illegal build_vector when folding a ↵Andrea Di Biagio2014-01-281-9/+15
| | | | | | | | | | | | | | | | | sign_extend. Make sure that we don't introduce illegal build_vector dag nodes when trying to fold a sign_extend of a build_vector. This fixes a regression introduced by r200234. Added test CodeGen/X86/fold-vector-sext-crash.ll to verify that llc no longer crashes with an assertion failure due to an illegal build_vector of type MVT::v4i64. Thanks to Ilia Filippov for spotting this regression and for providing a reproducible test case. llvm-svn: 200313
* [TLI] Add a new hook to TargetLowering to query the target if a load of a ↵Juergen Ributzka2014-01-282-11/+5
| | | | | | | | | | | | | | | | | constant should be converted to simply the constant itself. Before this patch we used getIntImmCost from TargetTransformInfo to determine if a load of a constant should be converted to just a constant, but the threshold for this was set to an arbitrary value. This value works well for the two targets (X86 and ARM) that implement this target-hook, but it isn't target-independent at all. Now targets have the possibility to decide directly if this optimization should be performed. The default value is set to false to preserve the current behavior. The target hook has been moved to TargetLowering, which removed the last use and need of TargetTransformInfo in SelectionDAG. llvm-svn: 200271
* Revert r199871 and replace it with a simple check in the debug infoEric Christopher2014-01-283-6/+15
| | | | | | | | | code to see if we're emitting a function into a non-default text section. This is still a less-than-ideal solution, but more contained than r199871 to determine whether or not we're emitting code into an array of comdat sections. llvm-svn: 200269
OpenPOWER on IntegriCloud