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* Fix a typo in the comment.Nadav Rotem2012-09-101-2/+2
| | | | llvm-svn: 163496
* Add an assertion that the frame index is indeed inside the declared lifetime ↵Nadav Rotem2012-09-101-0/+16
| | | | | | region. llvm-svn: 163495
* Teach the DAGBuilder about lifetime markers which are generated from PHINodes.Nadav Rotem2012-09-101-18/+22
| | | | llvm-svn: 163494
* Teach DAG combiner to constant fold fneg of a BUILD_VECTOR of constants.Craig Topper2012-09-091-1/+25
| | | | llvm-svn: 163483
* LiveVariables: Compute a set of defs and kills to speed up updating LV ↵Benjamin Kramer2012-09-091-4/+30
| | | | | | | | | | | | | | | during critical edge splitting. Previously we checked if the register is def'd in a block via the def/use list a nd walked the list of kills to check if the register is killed in a block. Both of these checks can be made much cheaper by walking the block first and recording all defs and kills. This reduces the compile time of the test case from PR13651 from 40s to 15s at -O2. The compile time is still dominated by LV updating but now the main culprit is SparseBitVector's slowness. llvm-svn: 163478
* Fix alignment of .comm and .lcomm on mingw32.Benjamin Kramer2012-09-071-1/+2
| | | | | | | | For some reason .lcomm uses byte alignment and .comm log2 alignment so we can't use the same setting for both. Fix this by reintroducing the LCOMM enum. I verified this against mingw's gcc. llvm-svn: 163420
* Fix indent.Chad Rosier2012-09-071-2/+2
| | | | llvm-svn: 163416
* Update function names to conform to guidelines. No functional change intended.Chad Rosier2012-09-072-49/+48
| | | | llvm-svn: 163401
* MC: Overhaul handling of .lcommBenjamin Kramer2012-09-071-2/+1
| | | | | | | | | | | | | - Darwin lied about not supporting .lcomm and turned it into zerofill in the asm parser. Push the zerofill-conversion down into macho-specific code. - This makes the tri-state LCOMMType enum superfluous, there are no targets without .lcomm. - Do proper error reporting when trying to use .lcomm with alignment on a target that doesn't support it. - .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2. - Fixes PR13755 (.lcomm crashes on ELF). llvm-svn: 163395
* Stop emitting lifetime region info when stack coloring is not enabled in O0Michael Liao2012-09-071-0/+6
| | | | | | - this should fix PR13780 llvm-svn: 163370
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-0618-0/+50
| | | | | | No functional change. llvm-svn: 163339
* Allow overlaps between virtreg and physreg live ranges.Jakob Stoklund Olesen2012-09-063-1/+53
| | | | | | | | | | | | | | | | | The RegisterCoalescer understands overlapping live ranges where one register is defined as a copy of the other. With this change, register allocators using LiveRegMatrix can do the same, at least for copies between physical and virtual registers. When a physreg is defined by a copy from a virtreg, allow those live ranges to overlap: %CL<def> = COPY %vreg11:sub_8bit; GR32_ABCD:%vreg11 %vreg13<def,tied1> = SAR32rCL %vreg13<tied0>, %CL<imp-use,kill> We can assign %vreg11 to %ECX, overlapping the live range of %CL. llvm-svn: 163336
* Handle overlapping regunit intervals in LiveIntervals::addKillFlags().Jakob Stoklund Olesen2012-09-062-3/+45
| | | | | | | | | | | | | | | | | | We will soon allow virtual register live ranges to overlap regunit live ranges when the physreg is defined as a copy of the virtreg: %EAX = COPY %vreg5 FOO %vreg5 BAR %EAX<kill> There is no real interference since %vreg5 and %EAX have the same value where they overlap. This patch prevents addKillFlags from adding virtreg kill flags to FOO where the assigned physreg is overlapping the virtual register live range. llvm-svn: 163335
* Clear kill flags while computing live ranges.Jakob Stoklund Olesen2012-09-061-1/+5
| | | | | | | | | Kill flags are difficult to maintain, and liveness queries are better handled by live intervals. Kill flags are reinserted after register allocation by addKillFlags(). llvm-svn: 163334
* Dont cast away const needlessly. Found by gcc48 -Wcast-qual.Roman Divacky2012-09-061-1/+1
| | | | llvm-svn: 163324
* Disable stack coloring by default in order to resolve the i386 failures.Nadav Rotem2012-09-061-1/+1
| | | | llvm-svn: 163316
* Fix a few old-GCC warnings. No functional change.Nadav Rotem2012-09-061-1/+1
| | | | llvm-svn: 163309
* Add a new optimization pass: Stack Coloring, that merges disjoint static ↵Nadav Rotem2012-09-0612-8/+712
| | | | | | | | allocations (allocas). Allocas are known to be disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics). llvm-svn: 163299
* [ms-inline asm] Use the asm dialect from the MI to set the parser dialect.Chad Rosier2012-09-051-2/+4
| | | | llvm-svn: 163273
* Cleanup a few magic numbers.Chad Rosier2012-09-052-2/+2
| | | | llvm-svn: 163263
* Stop casting away const qualifier needlessly.Roman Divacky2012-09-055-7/+7
| | | | llvm-svn: 163258
* [ms-inline asm] We only need one bit to represent the AsmDialect in theChad Rosier2012-09-052-11/+5
| | | | | | MachineInstr. llvm-svn: 163257
* Constify this properly. Found by gcc48 -Wcast-qual.Roman Divacky2012-09-051-4/+4
| | | | llvm-svn: 163256
* Constify SDNodeIterator an stop its only non-const user being cast strippedRoman Divacky2012-09-051-1/+1
| | | | | | of its constness. Found by gcc48 -Wcast-qual. llvm-svn: 163254
* [ms-inline asm] Propagate the asm dialect into the MachineInstr representation.Chad Rosier2012-09-052-1/+19
| | | | llvm-svn: 163243
* Remove unused typedefs gcc4.8 warns about.Roman Divacky2012-09-051-1/+0
| | | | llvm-svn: 163225
* Fixed the DAG combiner to better handle the folding of AND nodes for vector ↵Silviu Baranga2012-09-051-1/+11
| | | | | | types. The previous code was making the assumption that the length of the bitmask returned by isConstantSplat was equal to the size of the vector type. Now we first make sure that the splat value has at least the length of the vector lane type, then we only use as many fields as we have available in the splat value. llvm-svn: 163203
* Reorder the comments of EmitExceptionTable.Logan Chien2012-09-051-20/+20
| | | | llvm-svn: 163194
* Convert vextracti128/vextractf128 intrinsics to extract_subvector at DAG ↵Craig Topper2012-09-051-1/+15
| | | | | | build time. Similar was previously done for vinserti128/vinsertf128. Add patterns for folding these extract_subvectors with stores. llvm-svn: 163192
* Search the whole instruction for tied operands.Jakob Stoklund Olesen2012-09-041-2/+1
| | | | | | | Implicit uses can be dynamically tied to defs. This will soon be used for predicated instructions on ARM. llvm-svn: 163177
* Typo.Jakob Stoklund Olesen2012-09-041-1/+1
| | | | llvm-svn: 163154
* Actually use the MachineOperand field for isRegTiedToDefOperand().Jakob Stoklund Olesen2012-09-041-103/+0
| | | | | | | | | | The MachineOperand::TiedTo field was maintained, but not used. This patch enables it in isRegTiedToDefOperand() and isRegTiedToUseOperand() which are the actual functions use by the register allocator. llvm-svn: 163153
* Move tie checks into MachineVerifier::visitMachineOperand.Jakob Stoklund Olesen2012-09-041-36/+26
| | | | llvm-svn: 163152
* Allow tied uses and defs in different orders.Jakob Stoklund Olesen2012-09-041-30/+91
| | | | | | | | | | | | | | | | After much agonizing, use a full 4 bits of precious MachineOperand space to encode this. This uses existing padding, and doesn't grow MachineOperand beyond its current 32 bytes. This allows tied defs among the first 15 operands on a normal instruction, just like the current MCInstrDesc constraint encoding. Inline assembly needs to be able to tie more than the first 15 operands, and gets special treatment. Tied uses can appear beyond 15 operands, as long as they are tied to a def that's in range. llvm-svn: 163151
* Generic Bypass Slow DivPreston Gurd2012-09-041-1/+0
| | | | | | | | | | | | | | | | | | | | | | | - CodeGenPrepare pass for identifying div/rem ops - Backend specifies the type mapping using addBypassSlowDivType - Enabled only for Intel Atom with O2 32-bit -> 8-bit - Replace IDIV with instructions which test its value and use DIVB if the value is positive and less than 256. - In the case when the quotient and remainder of a divide are used a DIV and a REM instruction will be present in the IR. In the non-Atom case they are both lowered to IDIVs and CSE removes the redundant IDIV instruction, using the quotient and remainder from the first IDIV. However, due to this optimization CSE is not able to eliminate redundant IDIV instructions because they are located in different basic blocks. This is overcome by calculating both the quotient (DIV) and remainder (REM) in each basic block that is inserted by the optimization and reusing the result values when a subsequent DIV or REM instruction uses the same operands. - Test cases check for the presents of the optimization when calculating either the quotient, remainder, or both. Patch by Tyler Nowicki! llvm-svn: 163150
* IRBuilderify the SjlLjEHPrepare pass.Benjamin Kramer2012-09-031-57/+25
| | | | | | No functionality change. llvm-svn: 163115
* When updating live range endpoints, make sure to preserve the early clobber bit.Lang Hames2012-09-031-2/+2
| | | | | | Fixs PR13719. llvm-svn: 163107
* Fix a typo.Nadav Rotem2012-09-021-1/+1
| | | | llvm-svn: 163094
* Generate better select code by allowing the target to use scalar select, and ↵Nadav Rotem2012-09-021-4/+3
| | | | | | not sign-extend. llvm-svn: 163086
* Only legalise a VSELECT in to bitwise operations if the vector mask bool is ↵Pete Cooper2012-09-011-1/+6
| | | | | | | | | zeros or all ones. A vector bool with just ones isn't suitable for masking with. No test case unfortunately as i couldn't find a target which fit all the conditions needed to hit this code. llvm-svn: 163075
* Revert "Take account of boolean vector contents when promoting a build ↵Pete Cooper2012-09-011-17/+1
| | | | | | | | | | | | | | vector from i1 to some other type. rdar://problem/12210060" This reverts commit 5dd9e214fb92847e947f9edab170f9b4e52b908f. Thanks to Duncan for explaining how this should have been done. Conflicts: test/CodeGen/X86/vec_select.ll llvm-svn: 163064
* Fix typo.Logan Chien2012-09-011-1/+1
| | | | llvm-svn: 163059
* Teach DAG combine a number of tricks to simplify FMA expressions in ↵Owen Anderson2012-09-011-0/+64
| | | | | | fast-math mode. llvm-svn: 163051
* Fix typoMichael Liao2012-09-011-1/+1
| | | | llvm-svn: 163049
* Add MachineInstr::tieOperands, remove setIsTied().Jakob Stoklund Olesen2012-08-312-12/+18
| | | | | | | | | | | Manage tied operands entirely internally to MachineInstr. This makes it possible to change the representation of tied operands, as I will do shortly. The constraint that tied uses and defs must be in the same order was too restrictive. llvm-svn: 163021
* Use CloneMachineInstr to make a new MI in commuteInstruction to make the ↵Craig Topper2012-08-311-10/+1
| | | | | | code tolerant of instructions with more than two input operands. llvm-svn: 163000
* Don't enforce ordered inline asm operands.Jakob Stoklund Olesen2012-08-311-10/+0
| | | | | | | | | I was too optimistic, inline asm can have tied operands that don't follow the def order. Fixes PR13742. llvm-svn: 162998
* Take account of boolean vector contents when promoting a build vector from ↵Pete Cooper2012-08-301-1/+17
| | | | | | i1 to some other type. rdar://problem/12210060 llvm-svn: 162960
* Teach the DAG combiner to turn chains of FADDs (x+x+x+x+...) into FMULs by ↵Owen Anderson2012-08-301-1/+122
| | | | | | constants. This is only enabled in unsafe FP math mode, since it does not preserve rounding effects for all such constants. llvm-svn: 162956
* Currently targets that do not support selects with scalar conditions and ↵Nadav Rotem2012-08-301-1/+65
| | | | | | | | | | | vector operands - scalarize the code. ARM is such a target because it does not support CMOV of vectors. To implement this efficientlyi, we broadcast the condition bit and use a sequence of NAND-OR to select between the two operands. This is the same sequence we use for targets that don't have vector BLENDs (like SSE2). rdar://12201387 llvm-svn: 162926
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