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* Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to ↵Evan Cheng2008-02-286-10/+92
| | | | | | 16-byte boundaries. llvm-svn: 47703
* Handle load/store of misaligned vectors that are the Dale Johannesen2008-02-271-19/+30
| | | | | | | | | | | | same size as an int type by doing a bitconvert of load/store of the int type (same algorithm as floating point). This makes them work for ppc Altivec. There was some code that purported to handle loads of (some) vectors by splitting them into two smaller vectors, but getExtLoad rejects subvector loads, so this could never have worked; the patch removes it. llvm-svn: 47696
* Fix a bug in dead spill slot elimination.Evan Cheng2008-02-271-0/+2
| | | | llvm-svn: 47687
* Remove the `else', at Evan's insistence.Dan Gohman2008-02-271-2/+1
| | | | llvm-svn: 47686
* Add a FIXME about the VECTOR_SHUFFLE evil hack.Duncan Sands2008-02-271-0/+2
| | | | llvm-svn: 47676
* LegalizeTypes support for EXTRACT_VECTOR_ELT. TheDuncan Sands2008-02-276-59/+363
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | approach taken is different to that in LegalizeDAG when it is a question of expanding or promoting the result type: for example, if extracting an i64 from a <2 x i64>, when i64 needs expanding, it bitcasts the vector to <4 x i32>, extracts the appropriate two i32's, and uses those for the Lo and Hi parts. Likewise, when extracting an i16 from a <4 x i16>, and i16 needs promoting, it bitcasts the vector to <2 x i32>, extracts the appropriate i32, twiddles the bits if necessary, and uses that as the promoted value. This puts more pressure on bitcast legalization, and I've added the appropriate cases. They needed to be added anyway since users can generate such bitcasts too if they want to. Also, when considering various cases (Legal, Promote, Expand, Scalarize, Split) it is a pain that expand can correspond to Expand, Scalarize or Split, so I've changed the LegalizeTypes enum so it lists those different cases - now Expand only means splitting a scalar in two. The code produced is the same as by LegalizeDAG for all relevant testcases, except for 2007-10-31-extractelement-i64.ll, where the code seems to have improved (see below; can an expert please tell me if it is better or not). Before < vs after >. < subl $92, %esp < movaps %xmm0, 64(%esp) < movaps %xmm0, (%esp) < movl 4(%esp), %eax < movl %eax, 28(%esp) < movl (%esp), %eax < movl %eax, 24(%esp) < movq 24(%esp), %mm0 < movq %mm0, 56(%esp) --- > subl $44, %esp > movaps %xmm0, 16(%esp) > pshufd $1, %xmm0, %xmm1 > movd %xmm1, 4(%esp) > movd %xmm0, (%esp) > movq (%esp), %mm0 > movq %mm0, 8(%esp) < subl $92, %esp < movaps %xmm0, 64(%esp) < movaps %xmm0, (%esp) < movl 12(%esp), %eax < movl %eax, 28(%esp) < movl 8(%esp), %eax < movl %eax, 24(%esp) < movq 24(%esp), %mm0 < movq %mm0, 56(%esp) --- > subl $44, %esp > movaps %xmm0, 16(%esp) > pshufd $3, %xmm0, %xmm1 > movd %xmm1, 4(%esp) > movhlps %xmm0, %xmm0 > movd %xmm0, (%esp) > movq (%esp), %mm0 > movq %mm0, 8(%esp) < subl $92, %esp < movaps %xmm0, 64(%esp) --- > subl $44, %esp < movl 16(%esp), %eax < movl %eax, 48(%esp) < movl 20(%esp), %eax < movl %eax, 52(%esp) < movaps %xmm0, (%esp) < movl 4(%esp), %eax < movl %eax, 60(%esp) < movl (%esp), %eax < movl %eax, 56(%esp) --- > pshufd $1, %xmm0, %xmm1 > movd %xmm1, 4(%esp) > movd %xmm0, (%esp) > movd %xmm1, 12(%esp) > movd %xmm0, 8(%esp) < subl $92, %esp < movaps %xmm0, 64(%esp) --- > subl $44, %esp < movl 24(%esp), %eax < movl %eax, 48(%esp) < movl 28(%esp), %eax < movl %eax, 52(%esp) < movaps %xmm0, (%esp) < movl 12(%esp), %eax < movl %eax, 60(%esp) < movl 8(%esp), %eax < movl %eax, 56(%esp) --- > pshufd $3, %xmm0, %xmm1 > movd %xmm1, 4(%esp) > movhlps %xmm0, %xmm0 > movd %xmm0, (%esp) > movd %xmm1, 12(%esp) > movd %xmm0, 8(%esp) llvm-svn: 47672
* LegalizeTypes support for legalizing the maskDuncan Sands2008-02-272-0/+56
| | | | | | | | | | | | | | | | | | | | operand of a VECTOR_SHUFFLE. The mask is a vector of constant integers. The code in LegalizeDAG doesn't bother to legalize the mask, since it's basically just storage for a bunch of constants, however LegalizeTypes is more picky. The problem is that there may not exist any legal vector-of-integers type with a legal element type, so it is impossible to create a legal mask! Unless of course you cheat by creating a BUILD_VECTOR where the operands have a different type to the element type of the vector being built... This is pretty ugly but works - all relevant tests in the testsuite pass, and produce the same assembler with and without LegalizeTypes. llvm-svn: 47670
* LegalizeTypes support for INSERT_VECTOR_ELT.Duncan Sands2008-02-273-6/+47
| | | | llvm-svn: 47669
* Don't track max alignment during stack object allocations since they can be ↵Evan Cheng2008-02-271-2/+1
| | | | | | deleted later. Let PEI compute it. llvm-svn: 47668
* Support for legalizing MEMBARRIER.Duncan Sands2008-02-273-2/+19
| | | | llvm-svn: 47667
* Final de-tabification.Bill Wendling2008-02-272-2/+2
| | | | llvm-svn: 47663
* Spiller now remove unused spill slots.Evan Cheng2008-02-275-22/+108
| | | | llvm-svn: 47657
* Teach Legalize how to expand an EXTRACT_ELEMENT.Dan Gohman2008-02-271-0/+6
| | | | llvm-svn: 47656
* Convert the last remaining users of the non-APInt form ofDan Gohman2008-02-271-35/+15
| | | | | | | ComputeMaskedBits to use the APInt form, and remove the non-APInt form. llvm-svn: 47654
* Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt.Dan Gohman2008-02-272-141/+153
| | | | | | | | Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
* Use a smallvector for inactiveCounts and initialize it lazily Chris Lattner2008-02-261-4/+10
| | | | | | | | instead of init'ing it maximally to zeros on entry. getFreePhysReg is pretty hot and only a few elements are typically used. This speeds up linscan by 5% on 176.gcc. llvm-svn: 47631
* Rename PrintableName to Name.Bill Wendling2008-02-2613-40/+39
| | | | llvm-svn: 47629
* Change "Name" to "AsmName" in the target register info. Gee, a refactoring toolBill Wendling2008-02-2613-41/+44
| | | | | | would have been a Godsend here! llvm-svn: 47625
* Enable -coalescer-commute-instrs by default.Evan Cheng2008-02-261-1/+1
| | | | llvm-svn: 47623
* Avoid aborting on invalid shift counts.Dan Gohman2008-02-261-4/+18
| | | | llvm-svn: 47612
* Fix PR2096, a regression introduced with my patch last night. ThisChris Lattner2008-02-261-1/+1
| | | | | | also fixes cfrac, flops, and 175.vpr llvm-svn: 47605
* Fix a nasty bug in LegalizeTypes (spotted inDuncan Sands2008-02-266-60/+70
| | | | | | | | | | | | | | | | | CodeGen/PowerPC/illegal-element-type.ll): suppose a node X is processed, and processing maps it to a node Y. Then X continues to exist in the DAG, but with no users. While processing some other node, a new node may be created that happens to be equal to X, and thus X will be reused rather than a truly new node. This can cause X to "magically reappear", and since it is in the Processed state in will not be reprocessed, so at the end of type legalization the illegal node X can still be present. The solution is to replace X with Y whenever X gets resurrected like this. llvm-svn: 47601
* De-tabify.Bill Wendling2008-02-261-1/+1
| | | | llvm-svn: 47598
* This is possible:Evan Cheng2008-02-261-2/+8
| | | | | | | | | vr1 = extract_subreg vr2, 3 ... vr3 = extract_subreg vr1, 2 The end result is vr3 is equal to vr2 with subidx 2. llvm-svn: 47592
* Fix isNegatibleForFree to not return true for ConstantFP nodes Chris Lattner2008-02-261-33/+47
| | | | | | | | | after legalize. Just because a constant is legal (e.g. 0.0 in SSE) doesn't mean that its negated value is legal (-0.0). We could make this stronger by checking to see if the negated constant is actually legal post negation, but it doesn't seem like a big deal. llvm-svn: 47591
* Refactor inline asm constraint matching code out of SDIsel into TargetLowering.Evan Cheng2008-02-262-93/+17
| | | | llvm-svn: 47587
* Make some static variables const.Dan Gohman2008-02-251-3/+3
| | | | llvm-svn: 47566
* Convert MaskedValueIsZero and all its users to use APInt. Also addDan Gohman2008-02-257-68/+97
| | | | | | a SignBitIsZero function to simplify a common use case. llvm-svn: 47561
* All remat'ed loads cannot be folded into two-address code. Not just argument ↵Evan Cheng2008-02-251-4/+4
| | | | | | loads. This change doesn't really have any impact on codegen. llvm-svn: 47557
* In debug builds check that the key property holds: allDuncan Sands2008-02-251-12/+30
| | | | | | result and operand types are legal. llvm-svn: 47546
* Correctly determine whether a argument load can be folded into its uses.Evan Cheng2008-02-251-45/+52
| | | | llvm-svn: 47545
* Add support to LegalizeTypes for building legal vectorsDuncan Sands2008-02-243-1/+103
| | | | | | | | | out of illegal elements (BUILD_VECTOR). Uses and beefs up BUILD_PAIR, though it didn't really have to. Like most of LegalizeTypes, does not support soft-float. This cures all "make check" vector building failures. llvm-svn: 47537
* Some platforms use the same name for 32-bit and 64-bit registers (likeBill Wendling2008-02-241-4/+4
| | | | | | | | | %r3 on PPC) in their ASM files. However, it's hard for humans to read during debugging. Adding a new field to the register data that lets you specify a different name to be printed than the one that goes into the ASM file -- %x3 instead of %r3, for instance. llvm-svn: 47534
* Rematerialization logic was overly conservative when it comes to loads from ↵Evan Cheng2008-02-231-20/+6
| | | | | | fixed stack slots. llvm-svn: 47529
* If remating a machine instr with virtual register operand, make sure the vr ↵Evan Cheng2008-02-231-2/+1
| | | | | | is avaliable at all uses regardless of whether it would be folded. llvm-svn: 47526
* Recognize loads of arguments as re-materializable first. Therefore if ↵Evan Cheng2008-02-231-24/+26
| | | | | | isReallyTriviallyReMaterializable() returns true it doesn't confuse it as a "normal" re-materializable instruction. llvm-svn: 47520
* Fix spill weight updating bug.Evan Cheng2008-02-231-15/+27
| | | | llvm-svn: 47507
* Same isPhysRegAvailable bug as local register allocator.Evan Cheng2008-02-221-1/+1
| | | | llvm-svn: 47500
* Really really bad local register allocator bug. On X86, it was never using ↵Evan Cheng2008-02-221-1/+1
| | | | | | | | ESI, EDI, and EBP because of a bug in RALocal::isPhysRegAvailable(). For example, when it checks if ESI is available, it then looks at registers aliases to ESI. SIL is marked -2 (not allocatable) but isPhysRegAvailable() incorrectly assumes it is in use and returns false for ESI. llvm-svn: 47499
* Add debugging printfs.Evan Cheng2008-02-221-0/+2
| | | | llvm-svn: 47496
* Make sure reload of implicit uses are issued before remat's.Evan Cheng2008-02-221-3/+15
| | | | llvm-svn: 47492
* Pass alignment on ByVal parameters, from FE, allDale Johannesen2008-02-221-0/+9
| | | | | | the way through. It is now used for codegen. llvm-svn: 47484
* Enable re-materialization of instructions which have virtual register ↵Evan Cheng2008-02-222-39/+187
| | | | | | | | operands if the definition of the operand also reaches its uses. llvm-svn: 47475
* Fix compiler warning.Evan Cheng2008-02-221-1/+1
| | | | llvm-svn: 47468
* Fix a regression in 403.gcc and 186.crafty introduced in 47383. To testDan Gohman2008-02-222-28/+30
| | | | | | | that a value is >= 32, check that all of the high bits are zero, not just one or more. llvm-svn: 47467
* Make the clobber analysis a bit more smart: we only are careful about Chris Lattner2008-02-211-3/+13
| | | | | | | early clobbers if the clobber list contains a *register* not some thing like {memory}, {dirflag} etc. llvm-svn: 47457
* Treat clobber operands like early clobbers: if we haveChris Lattner2008-02-211-0/+16
| | | | | | | | | any, we force sdisel to do all regalloc for an asm. This leads to gross but correct codegen. This fixes the rest of PR2078. llvm-svn: 47454
* Clear PhysRegPartUse for the sub register as well.Bill Wendling2008-02-211-1/+1
| | | | llvm-svn: 47453
* Adjust the MaxAlignment for the special register scavenging spill slot.Bill Wendling2008-02-211-0/+3
| | | | llvm-svn: 47452
* Help testing.Evan Cheng2008-02-211-0/+7
| | | | llvm-svn: 47448
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