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* revert bill's patches in an attempt to fix the buildbot.Chris Lattner2010-07-154-27/+22
| | | | llvm-svn: 108419
* Fix headers.Bill Wendling2010-07-152-1/+1
| | | | llvm-svn: 108413
* Use std::vector instead of a hard-coded array. The length of that array couldBill Wendling2010-07-152-17/+20
| | | | | | get *very* large, but we only need it to be the size of the number of pregs. llvm-svn: 108412
* Use std::vector instead of a hard-coded array. The length of that array couldBill Wendling2010-07-152-6/+8
| | | | | | get *very* large, but we only need it to be the size of thenumber of pregs. llvm-svn: 108411
* a more graceful fix for test/Other/inline-asm-newline-terminator.ll,Chris Lattner2010-07-152-15/+1
| | | | | | follow on to r103765 llvm-svn: 108390
* 80-col.Eric Christopher2010-07-141-2/+3
| | | | llvm-svn: 108381
* Make the order in which variables are described in debug informationDan Gohman2010-07-141-0/+23
| | | | | | | | independent of the order that isel happens to visit the dbg_declare intrinsics. This fixes a bug in which the formal arguments were being printed in reverse order, now that fast isel is going bottom up. llvm-svn: 108369
* Properly restore DebugLoc after leaving the local constant area.Dan Gohman2010-07-141-1/+2
| | | | llvm-svn: 108364
* Delete fast-isel's trivial load optimization; it breaks debugging becauseDan Gohman2010-07-141-31/+0
| | | | | | it can look past points where a debugger might modify user variables. llvm-svn: 108336
* Teach ProcessImplicitDefs to transform more COPY instructions into ↵Evan Cheng2010-07-142-20/+43
| | | | | | IMPLICIT_DEF (and subsequently eliminate them). This allows machine LICM to hoist IMPLICIT_DEF's. PR7620. llvm-svn: 108304
* Don't propagate debug locations to instructions for materializingDan Gohman2010-07-141-5/+8
| | | | | | | constants, since they may not be emited near the other instructions which get the same line, and this confuses debug info. llvm-svn: 108302
* Print VNInfo flags.Jakob Stoklund Olesen2010-07-131-0/+4
| | | | llvm-svn: 108277
* In inline asm treat indirect 'X' constraint as 'm'.Dale Johannesen2010-07-131-3/+5
| | | | | | | This may not be right in all cases, but it's better than asserting which it was doing before. PR 7528. llvm-svn: 108268
* Add an assertion to make PR7542 fail consistently.Jakob Stoklund Olesen2010-07-131-0/+1
| | | | | | | | | | LiveInterval::overlapsFrom dereferences end() if it is called on an empty interval. It would be reasonable to just return false - an empty interval doesn't overlap anything, but I want to know who is doing it first. llvm-svn: 108264
* Fix LiveInterval::overlaps so it doesn't claim touching intervals overlap.Jakob Stoklund Olesen2010-07-131-10/+2
| | | | | | Also, one binary search is enough. llvm-svn: 108261
* Don't add memory operands to storeRegToStackSlot / loadRegFromStackSlot results,Jakob Stoklund Olesen2010-07-131-38/+32
| | | | | | | | | | | they already have one. This fixes the himenobmtxpa miscompilation on ARM. The PostRA scheduler got confused by the double memoperand and hoisted a stack slot load above a store to the same slot. llvm-svn: 108219
* Fix a typo and fit in 80 columns. Found by Bob Wilson.Rafael Espindola2010-07-121-1/+2
| | | | llvm-svn: 108164
* Convert some tab stops into spaces.Duncan Sands2010-07-124-31/+31
| | | | llvm-svn: 108130
* Convert the last use of getPhysicalRegisterRegClass and remove it.Rafael Espindola2010-07-121-1/+5
| | | | | | | | | | | | AggressiveAntiDepBreaker should not be using getPhysicalRegisterRegClass. An instruction might be using a register that can only be replaced with one from a subclass of getPhysicalRegisterRegClass. With this patch we use getMinimalPhysRegClass. This is correct, but conservative. We should check the uses of the register and select the largest register class that can be used in all of them. llvm-svn: 108122
* Don't use getPhysicalRegisterRegClass in PBQP. The existing checks that theRafael Espindola2010-07-121-15/+10
| | | | | | | | | | physical register can be allocated in the class of the virtual are sufficient. I think that the test for virtual registers is more strict than it needs to be, it should be possible to coalesce two virtual registers the class of one is a subclass of the other. llvm-svn: 108118
* Convert the last getPhysicalRegisterRegClass in VirtRegRewriter.cpp toRafael Espindola2010-07-121-1/+1
| | | | | | | | | getMinimalPhysRegClass. It was used to produce spills, and it is better to use the most specific class if possible. Update getLoadStoreRegOpcode to handle GR32_AD. llvm-svn: 108115
* change machinelicm to use MachineInstr::isSafeToMove. NoChris Lattner2010-07-121-18/+8
| | | | | | | | intended functionality change. The avoidance of hoistiing implicitdef seems wrong though. llvm-svn: 108109
* Remove TargetInstrInfo::copyRegToReg entirely.Jakob Stoklund Olesen2010-07-111-17/+0
| | | | | | | Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no longer a default implementation forwarding to copyRegToReg. llvm-svn: 108095
* Convert uses of getPhysicalRegisterRegClass in VirtRegRewriter.cpp.Rafael Espindola2010-07-111-2/+2
| | | | | | | | | | | | The first one was used just to call isSafeToMoveRegClassDefs. In general, using a more specific reg class is better, in practice only x86 implements that method and the results are always the same. The second one is in FindFreeRegister and is used to check if a register is in a register class, a much more direct call to contains is better as it should cover more cases and is faster. llvm-svn: 108093
* Remove two other uses of ATTRIBUTE_UNUSED for variables only used withinChandler Carruth2010-07-111-3/+2
| | | | | | | | assert()s, switching to void-casts. Removed an unneeded Compiler.h include as a result. There are two other uses in LLVM, but they're not due to assert()s, so I've left them alone. llvm-svn: 108088
* Use COPY for fast-isel bitconvert, but don't create cross-class copies.Jakob Stoklund Olesen2010-07-111-7/+6
| | | | | | This doesn't change the behavior of SelectBitcast for X86. llvm-svn: 108073
* Fix va_arg for doubles. With this patch VAARG nodes always contain theRafael Espindola2010-07-116-9/+12
| | | | | | | | | | | | | | | correct alignment information, which simplifies ExpandRes_VAARG a bit. The patch introduces a new alignment information to TargetLoweringInfo. This is needed since the two natural candidates cannot be used: * The 's' in target data: If this is set to the minimal alignment of any argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for example. * The getTransientStackAlignment method. It is possible for an architecture to have argument less aligned than what we maintain the stack pointer. llvm-svn: 108072
* Use COPY for extracting ImplicitDef'ed values from fast-isel instructions.Jakob Stoklund Olesen2010-07-111-30/+12
| | | | | | | This assumes that the registers can be copied which is probably a safe assumption. llvm-svn: 108070
* Use COPY in FastISel everywhere it is safe and trivial.Jakob Stoklund Olesen2010-07-111-8/+4
| | | | | | | The remaining copyRegToReg calls actually check the return value (shock!), so we cannot trivially replace them with COPY instructions. llvm-svn: 108069
* Replace copyRegToReg with COPY everywhere in lib/CodeGen except for FastISel.Jakob Stoklund Olesen2010-07-107-98/+62
| | | | llvm-svn: 108062
* Only collect subreg extracting copies for later coalescing.Jakob Stoklund Olesen2010-07-101-1/+1
| | | | | | This also avoids fatal copies from physregs. llvm-svn: 108061
* Fix a bug in the code which re-inserts DBG_VALUE nodes after scheduling;Dan Gohman2010-07-101-1/+3
| | | | | | | | if a block is split (by a custom inserter), the insert point may be in a different block than it was originally. This fixes 32-bit llvm-gcc bootstrap builds, and I haven't been able to reproduce it otherwise. llvm-svn: 108060
* Emit COPY instructions instead of using copyRegToReg in InstrEmitter,Jakob Stoklund Olesen2010-07-104-53/+21
| | | | | | | | | ScheduleDAGEmit, TwoAddressLowering, and PHIElimination. This switches the bulk of register copies to using COPY, but many less used copyRegToReg calls remain. llvm-svn: 108050
* Insert IMPLICIT_DEF instructions at the current insert position, notDan Gohman2010-07-101-1/+1
| | | | | | at the end of the block. llvm-svn: 108045
* Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman2010-07-109-263/+383
| | | | | | | | | - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
* Update DBG_VALUE to refer appropriate stack slot in case of a spill.Devang Patel2010-07-091-2/+19
| | | | llvm-svn: 108023
* Fix small bug in isMoveInstr -> COPY translationJakob Stoklund Olesen2010-07-091-3/+4
| | | | llvm-svn: 108013
* Automatically fold COPY instructions into stack load/store.Jakob Stoklund Olesen2010-07-091-9/+75
| | | | llvm-svn: 108012
* Remat uncoalescable COPY instrsJakob Stoklund Olesen2010-07-091-0/+11
| | | | llvm-svn: 108010
* Clarify what mysterious check means.Bill Wendling2010-07-091-0/+3
| | | | llvm-svn: 108005
* Fix MachineLICM to actually visit inner loops.Dan Gohman2010-07-091-3/+11
| | | | llvm-svn: 108001
* Change TII::foldMemoryOperand API to require the machine instruction to beJakob Stoklund Olesen2010-07-095-31/+32
| | | | | | | | | | | | | | inserted in a MBB, and return an already inserted MI. This target API change is necessary to allow foldMemoryOperand to call storeToStackSlot and loadFromStackSlot when folding a COPY to a stack slot reference in a target independent way. The foldMemoryOperandImpl hook is going to change in the same way, but I'll wait until COPY folding is actually implemented. Most targets only fold copies and won't need to specialize this hook at all. llvm-svn: 107991
* --- Reverse-merging r107947 into '.':Bob Wilson2010-07-099-383/+263
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h llvm-svn: 107987
* cache result of operator*Gabor Greif2010-07-091-4/+8
| | | | llvm-svn: 107980
* Avoid creating %physreg:subidx operands in ↵Jakob Stoklund Olesen2010-07-091-1/+4
| | | | | | | | SimpleRegisterCoalescing::RemoveCopyByCommutingDef. This fixes PR7602. llvm-svn: 107957
* Deal with a few remaining spots that assume physical registers have live ↵Jakob Stoklund Olesen2010-07-091-2/+4
| | | | | | | | intervals. This fixes PR7601. llvm-svn: 107955
* Fix broken isCopy handling in TrimLiveIntervalToLastUse.Jakob Stoklund Olesen2010-07-091-3/+7
| | | | llvm-svn: 107950
* Handle COPY in VirtRegRewriter.Jakob Stoklund Olesen2010-07-091-0/+28
| | | | llvm-svn: 107949
* Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emittingDan Gohman2010-07-099-263/+383
| | | | | | a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL. llvm-svn: 107943
* Reenable DAG combining for vector shuffles. It looks like it was temporarilyBob Wilson2010-07-091-2/+0
| | | | | | | | disabled and then never turned back on again. Adjust some tests, one because this change avoids an unnecessary instruction, and the other to make it continue testing what it was intended to test. llvm-svn: 107941
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