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* [SelectionDAG] Provide default expansion for rotatesKrzysztof Parzyszek2018-06-122-2/+52
| | | | | | | | | | | | | Implement default legalization of rotates: either in terms of the rotation in the opposite direction (if legal), or in terms of shifts and ors. Implement generating of rotate instructions for Hexagon. Hexagon only supports rotates by an immediate value, so implement custom lowering of ROTL/ROTR on Hexagon. If a rotate is not legal, use the default expansion. Differential Revision: https://reviews.llvm.org/D47725 llvm-svn: 334497
* DAG: Fix extract_subvector combine for a single elementMatt Arsenault2018-06-111-3/+12
| | | | | | | | | | | | | | | | This would fail before because 1x vectors aren't legal, so instead just use the scalar type. Avoids regressions in a future AMDGPU commit to add v4i16/v4f16 as legal types. Test update is just the one test that this triggers on in tree now. It wasn't checking anything before. The result is completely changed since the selects are eliminated. Not sure if it's considered better or not. llvm-svn: 334440
* [CodeView] Omit forward references for unnamed structs and unionsBrock Wyma2018-06-111-10/+40
| | | | | | | | | | Codeview references to unnamed structs and unions are expected to refer to the complete type definition instead of a forward reference so Visual Studio can resolve the type properly. Differential Revision: https://reviews.llvm.org/D32498 llvm-svn: 334382
* [DAGCombiner] match vector compare and select sizes with extload operand ↵Sanjay Patel2018-06-101-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | (PR37427) This patch started off much more general and ambitious, but it's been a nightmare seeing all the ways x86 vector codegen can go wrong. So the code is still structured to allow extending easily, but it's currently limited in several ways: 1. Only handle cases with an extending load. 2. Only handle cases with a zero constant compare. 3. Ignore setcc with vector bitmask (SetCCWidth != 1) - so AVX512 should be unaffected. The motivating case from PR37427: https://bugs.llvm.org/show_bug.cgi?id=37427 ...is the 1st test, and that shows the expected win - we eliminated the unnecessary intermediate cast. There's a clear regression in the last test (sgt_zero_fp_select) because we longer recognize a 'SHRUNKBLEND' opportunity. I think that general problem is also present in sgt_zero, so I'll try to fix that in a follow-up. We need to match a sign-bit setcc from a sign-extended operand and remove it. Differential Revision: https://reviews.llvm.org/D47330 llvm-svn: 334378
* Use SmallPtrSet instead of SmallSet in places where we iterate over the set.Craig Topper2018-06-091-1/+1
| | | | | | | | SmallSet forwards to SmallPtrSet for pointer types. SmallPtrSet supports iteration, but a normal SmallSet doesn't. So if it wasn't for the forwarding, this wouldn't work. These places were found by hiding the begin/end methods in the SmallSet forwarding llvm-svn: 334343
* [DAGCombiner] clean up comments; NFCSanjay Patel2018-06-081-8/+5
| | | | llvm-svn: 334312
* Utilize new SDNode flag functionality to expand current support for fsubMichael Berg2018-06-081-17/+23
| | | | | | | | | | | | | | Summary: This patch originated from D46562 and is a proper subset, with some issues addressed for fsub. Reviewers: spatel, hfinkel, wristow, arsenm Reviewed By: spatel Subscribers: wdng Differential Revision: https://reviews.llvm.org/D47910 llvm-svn: 334306
* [DAGCombine] Fix for PR37667Sam Parker2018-06-081-0/+16
| | | | | | | | | | While trying to propagate AND masks back to loads, we currently allow one non-load node to be included as a leaf in chain. This fix now limits that node to produce only a single data value. Differential Revision: https://reviews.llvm.org/D47878 llvm-svn: 334268
* propagate fast math flags via IR on fma and sub expressionsMichael Berg2018-06-072-47/+56
| | | | | | | | | | | | | | Summary: This change uses fmf subflags to guard fma optimizations as well as unsafe. These changes originated from D46483 and have been simplified via getNode. Reviewers: spatel, arsenm, hfinkel, javed.absar Reviewed By: spatel Subscribers: nemanjai, wdng Differential Revision: https://reviews.llvm.org/D47388 llvm-svn: 334242
* DAG: Avoid bitcast/ext/build_vector combineMatt Arsenault2018-06-071-1/+4
| | | | | | | | | | | | | | | | | | | | | This avoids regressions in a future AMDGPU change to make v4i16/v4f16 legal. For these types, build_vector is implemented as bitcasted operations on v2i32. This combine was creating v4i16s out of what would have been already been a v2i32 build_vector, creating a mess of nodes that never get cleaned up. I'm not sure this is the right condition to check. I initially tried just checking for the legality of the new build_vector. This works for my case, but breaks dozens of x86 tests. A Mips test seems to show some improvement or at least a neutral change. I don't want to think about how long it would take to analyze the set of different x86 vector operations impacted. Test included in future commit. llvm-svn: 334218
* [BranchFolding] Fix live-in's when hoisting codeKarl-Johan Karlsson2018-06-071-22/+3
| | | | | | | | | | | | | | | | | | | | | Summary: When the branch folder hoist code into a predecessor it adjust live-in's in the blocks it hoist code from. However it fail to handle hoisted code that contain a defed register that originally is live-in in the block through a super register. This is fixed by replacing the live-in handling code with calls to utility functions in LivePhysRegs. Reviewers: kparzysz, gberry, MatzeB, uweigand, aprantl Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47529 llvm-svn: 334163
* guard fsqrt with fmf sub flagsMichael Berg2018-06-061-5/+4
| | | | | | | | | | | | | | | | | Summary: This change uses fmf subflags to guard optimizations as well as unsafe. These changes originated from D46483. It contains only context for fsqrt. Reviewers: spatel, hfinkel, arsenm Reviewed By: spatel Subscribers: hfinkel, wdng, andrew.w.kaylor, wristow, efriedma, nemanjai Differential Revision: https://reviews.llvm.org/D47749 llvm-svn: 334113
* [GlobalMerge] Set the alignment on merged global structsDavid Green2018-06-061-0/+5
| | | | | | | | | | If no alignment is set, the abi/preferred alignment of structs will be used which may be higher than required. This can lead to extra padding and in the end an increase in data size. Differential Revision: https://reviews.llvm.org/D47633 llvm-svn: 334099
* [CodeGen] assume max/default throughput for unspecified instructionsSanjay Patel2018-06-052-12/+12
| | | | | | | | | | | | | This is a fix for the problem arising in D47374 (PR37678): https://bugs.llvm.org/show_bug.cgi?id=37678 We may not have throughput info because it's not specified in the model or it's not available with variant scheduling, so assume that those instructions can execute/complete at max-issue-width. Differential Revision: https://reviews.llvm.org/D47723 llvm-svn: 334055
* [CodeGenPrepare] Move Extension Instructions Through Logical And Shift ↵Guozhi Wei2018-06-051-0/+41
| | | | | | | | | | | | Instructions CodeGenPrepare pass move extension instructions close to load instructions in different BB, so they can be combined later. But the extension instructions can't move through logical and shift instructions in current implementation. This patch enables this enhancement, so we can eliminate more extension instructions. Differential Revision: https://reviews.llvm.org/D45537 This is re-commit of r331783, which was reverted by r333305. The performance regression was caused by some unlucky alignment, not a code generation problem. llvm-svn: 334049
* guard fneg with fmf sub flagsMichael Berg2018-06-051-3/+3
| | | | | | | | | | | | | | Summary: This change uses fmf subflags to guard optimizations as well as unsafe. These changes originated from D46483. Reviewers: spatel, hfinkel Reviewed By: spatel Subscribers: nemanjai Differential Revision: https://reviews.llvm.org/D47389 llvm-svn: 334037
* DAG: Stop dropping invariant/dereferencableMatt Arsenault2018-06-051-4/+3
| | | | | | | | | | | | | When legalizing illegal FP load results, this was for some reason dropping the invariant and dereferencable memory flags. There doesn't seem to be any reason for this, and the equivalent isn't done for integer loads. Fixes an issue in a future AMDGPU commit where some identical loads fail to merge because one of the loads ends up dropping the flags. llvm-svn: 334020
* [RegAllocGreedy] Use simpler map class for EvicteeInfo. NFCI.Nirav Dave2018-06-051-1/+1
| | | | | | | | RegAlloc keeps a insertion-time ordered map of evictee information, but we only use membership. Replace MapVector with contextually equivalent DenseMap which is smaller and faster. llvm-svn: 333981
* Use MF instead of Fn for MachineFunction references. NFCFrancis Visoiu Mistrih2018-06-051-97/+97
| | | | llvm-svn: 333973
* [ShrinkWrap] Add optimization remarks to the shrink-wrapping passFrancis Visoiu Mistrih2018-06-051-6/+27
| | | | | | | | Start by emitting remarks for very basic unsupported cases such as irreducible CFGs and EHFunclets. The end goal is to be able to cover all the cases where we give up with an explanation. llvm-svn: 333972
* [MIRParser] Add parser support for 'true' and 'false' i1s.Amara Emerson2018-06-051-2/+5
| | | | | | | | | We already output true and false in the printer, but the parser isn't able to read it. Differential Revision: https://reviews.llvm.org/D47424 llvm-svn: 333970
* Fix -Wcovered-switch-default warning and clang-format itReid Kleckner2018-06-041-10/+8
| | | | llvm-svn: 333967
* Move Analysis/Utils/Local.h back to TransformsDavid Blaikie2018-06-045-5/+5
| | | | | | | | | | Review feedback from r328165. Split out just the one function from the file that's used by Analysis. (As chandlerc pointed out, the original change only moved the header and not the implementation anyway - which was fine for the one function that was used (since it's a template/inlined in the header) but not in general) llvm-svn: 333954
* [MachineOutliner] NFC - Move intermediate data structures to MachineOutliner.hJessica Paquette2018-06-041-191/+48
| | | | | | | | | | | | | | | | | | | | | This is setting up to fix bug 37573 cleanly. This moves data structures that are technically both used in some way by the target and the general-purpose outlining algorithm into MachineOutliner.h. In particular, the `Candidate` class is of importance. Before, the outliner passed the locations of `Candidates` to the target, which would then make some decisions about the prospective outlined function. This change allows us to just pass `Candidates` along to the target. This will allow the target to discard `Candidates` that would be considered unsafe before cost calculation. Thus, we will be able to remove the unsafe candidates described in the bug without resorting to torching the entire prospective function. Also, as a side-effect, it makes the outliner a bit cleaner. https://bugs.llvm.org/show_bug.cgi?id=37573 llvm-svn: 333952
* [CodeGen] Always update divergence in SelectionDAG::UpdateNodeOperandsScott Linder2018-06-041-0/+2
| | | | | | | | Some overloads failed to update divergence. Differential Revision: https://reviews.llvm.org/D47148 llvm-svn: 333947
* [DAGcombine] Teach the combiner about -a = ~a + 1Amaury Sechet2018-06-041-1/+60
| | | | | | | | | | | | Summary: This include variant for add, uaddo and addcarry. usubo and subcarry require the carry to be flipped to preserve semantic, but we chose to do the transform anyway in that case as to push the transform down the carry chain. Reviewers: efriedma, spatel, RKSimon, zvi, bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46505 llvm-svn: 333943
* Get rid of SETCCEAmaury Sechet2018-06-045-52/+12
| | | | | | | | | | | | Summary: It has been deprecated in favor of SETCCCARRY for a year now and isn't used by any in tree backend. Reviewers: efriedma, craig.topper, dblaikie, bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47685 llvm-svn: 333939
* [SelectionDAG] Add missing closing parentheses in comments, NFCKrzysztof Parzyszek2018-06-041-6/+6
| | | | llvm-svn: 333907
* Add a debug dump for DbgValueHistoryMapVedant Kumar2018-06-013-0/+37
| | | | | | | | | This makes it easier to inspect the results of DbgValueHistoryCalculator. Differential Revision: https://reviews.llvm.org/D47663 llvm-svn: 333801
* [DAG] Avoid checking for consecutive stores in store merge. NFCI.Nirav Dave2018-06-011-319/+340
| | | | llvm-svn: 333766
* [DAG] Simplify Expression. NFC.Nirav Dave2018-06-011-9/+3
| | | | llvm-svn: 333765
* [DAG] Remove untriggerable check. NFCI.Nirav Dave2018-06-011-10/+0
| | | | | | Candidate check precludes this check. llvm-svn: 333764
* [DAG] Prune store merge legal store check to stop invalid size. NFCI.Nirav Dave2018-06-011-0/+15
| | | | | | Do not consider store sizes large than the maximum legal store size. llvm-svn: 333763
* [SelectionDAG] Expand UADDO/USUBO into ADD/SUBCARRY if legal for targetKrzysztof Parzyszek2018-06-012-9/+25
| | | | | | | | | Additionally, implement handling of ADD/SUBCARRY on Hexagon, utilizing the UADDO/USUBO expansion. Differential Revision: https://reviews.llvm.org/D47559 llvm-svn: 333751
* Set ADDE/ADDC/SUBE/SUBC to expand by defaultAmaury Sechet2018-06-011-0/+6
| | | | | | | | | | | | | | | Summary: They've been deprecated in favor of UADDO/ADDCARRY or USUBO/SUBCARRY for a while. Target that uses these opcodes are changed in order to ensure their behavior doesn't change. Reviewers: efriedma, craig.topper, dblaikie, bkramer Subscribers: jholewinski, arsenm, jyknight, sdardis, nemanjai, nhaehnle, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, mgrang, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D47422 llvm-svn: 333748
* [AArch64][GlobalISel] Zero-extend s1 values when returning.Amara Emerson2018-06-011-11/+1
| | | | | | | | | | | Before we were relying on the any extend of the s1 to s32, but for AAPCS we need to zero-extend it to at least s8. Fixes PR36719 Differential Revision: https://reviews.llvm.org/D47425 llvm-svn: 333747
* NFC Avoid a warning in WasmEHPrepare.cppGabor Buella2018-06-011-1/+1
| | | | | | | | | | ``` ../lib/CodeGen/WasmEHPrepare.cpp:166:30: warning: extra ‘;’ [-Wpedantic] false, false); ^ ``` llvm-svn: 333732
* Change ambiguous uses of term 'funclet' to 'EH scopes'. NFC.Heejin Ahn2018-06-014-48/+51
| | | | | | | | | | | | | | | | | | Summary: `getEHScopeMembership()` function is used not only for funclet-based EHs; they apply to all EH schemes that use the scoped IR (catchpad/cleanuppad/...). D47005 (rL333045) changed some of the uses of the term 'funclet' to 'EH scopes' in case they apply to all scoped EH, and this fixes more of them. For `FuncletLayout` pass, I left it as is because the pass is only used for funclet-based EH. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47611 llvm-svn: 333711
* [WebAssembly] Support instruction selection for catching exceptionsHeejin Ahn2018-05-311-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This lowers exception catching-related instructions: 1. Lowers `wasm.catch` intrinsic to `catch` instruction 2. Removes `catchpad` and `cleanuppad` instructions; they are not necessary after isel phase. (`MachineBasicBlock::isEHFuncletEntry()` or `MachineBasicBlock::isEHPad()` can be used instead.) 3. Lowers `catchret` and `cleanupret` instructions to pseudo `catchret` and `cleanupret` instructions in isel, which will be replaced with other instructions in `WebAssemblyExceptionPrepare` pass. 4. Adds 'WebAssemblyExceptionPrepare` pass, which is for running various transformation for EH. Currently this pass only replaces `catchret` and `cleanupret` instructions into appropriate wasm instructions to make this patch successfully run until the end. Currently this does not handle lowering of intrinsics related to LSDA info generation (`wasm.landingpad.index` and `wasm.lsda`), because they cannot be tested without implementing `EHStreamer`'s wasm-specific handlers. They are marked as TODO, which is needed to make isel pass. Also this does not generate `try` and `end_try` markers yet, which will be handled in later patches. This patch is based on the first wasm EH proposal. (https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md) Reviewers: dschuff, majnemer Subscribers: jfb, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D44090 llvm-svn: 333705
* [WebAssembly] Add Wasm exception handling prepare passHeejin Ahn2018-05-315-6/+358
| | | | | | | | | | | | | | | | Summary: This adds a pass that transforms a program to be prepared for Wasm exception handling. This is using Windows EH instructions and based on the previous Wasm EH proposal. (https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md) Reviewers: dschuff, majnemer Subscribers: jfb, mgorny, sbc100, jgravelle-google, JDevlieghere, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D43746 llvm-svn: 333696
* [ADT] Make escaping fn conform to coding guidelinesJonas Devlieghere2018-05-311-1/+1
| | | | | | | | As noted by Adrian on llvm-commits, PrintHTMLEscaped and PrintEscaped in StringExtras did not conform to the LLVM coding guidelines. This commit rectifies that. llvm-svn: 333669
* [MCSchedule] Add the ability to compute the latency and throughput ↵Andrea Di Biagio2018-05-312-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | information for MCInst. This patch extends the MCSchedModel API with new methods that can be used to obtain the latency and reciprocal througput information for an MCInst. Scheduling models have recently gained the ability to resolve variant scheduling classes associated with MCInst objects. Before, models were only able to resolve a variant scheduling class from a MachineInstr object. This patch is mainly required by D47374 to avoid regressing a pair of x86 specific -print-schedule tests for btver2. Patch D47374 introduces a new variant class to teach the btver scheduling model (x86 target) how to correctly compute the latency profile for some zero-idioms using the new scheduling predicates. The new methods added by this patch would be mainly used by llc when flag -print-schedule is specified. In particular, tests that contain inline assembly require that code is parsed at code emission stage into a sequence of MCInst. That forces the print-schedule functionality to query the latency/rthroughput information for MCInst instructions too. If we don't expose this new API, then we lose "-print-schedule" test coverage as soon as variant scheduling classes are added to the x86 models. The tablegen SubtargetEmitter changes teaches how to query latency profile information using a object that derives from TargetSubtargetInfo. Note that this should really have been part of r333286. To avoid code duplication, the logic that "resolves" variant scheduling classes for MCInst, has been moved to a common place in MC. That logic is used by the "resolveVariantSchedClass" methods redefined in override by the tablegen'd GenSubtargetInfo classes. Differential Revision: https://reviews.llvm.org/D47536 llvm-svn: 333650
* [GlobalISel][Legalizer] LegalizerInfo verifier: Making ↵Roman Tereshin2018-05-311-0/+3
| | | | | | | | | | | | LegalizerInfo::verify(...) errors fatal Reviewers: aemerson, qcolombet Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D46339 llvm-svn: 333619
* [GlobalISel][Legalizer] LegalizerInfo verifier: check rules cover type indicesRoman Tereshin2018-05-301-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a simple verifier that tracks type indices being touched by legalization rules' builders. Every target will now have an opportunity to call LegalizerInfo::verify(...) at the end of its derived LegalizerInfo's constructor and check there are no obvious mistakes like checking only first type for an opcode that has more than one type index and therefore implicitly declaring any type for the second (and higher) type index legal. The check is only ran in assert builds and should have very minor performance impact in assert builds and none in release builds. This commit does not add LegalizerInfo::verify(...) calls to target-specific legalizers, look for separate commits for that. This commit also doesn't make the verification errors fatal, only produces an error message, look for a later commit that does. Reviewers: aemerson, qcolombet Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D46338 llvm-svn: 333576
* DAG: Remove redundant version of getRegisterTypeForCallingConvMatt Arsenault2018-05-291-4/+4
| | | | | | | | | | | There seems to be no real reason to have these separate copies. The existing implementations just copy each other for x86. For Mips there is a subtle difference, which is just a bug since it changes based on the context where which one was called. Dropping this version, all tests pass. If I try to merge them to match the removed version, a test fails. llvm-svn: 333440
* [StrictFP] Make getStrictFPOpcodeAction(...) more accessibleCameron McInally2018-05-291-32/+2
| | | | | | | | NFCI. This function will be reused in upcoming patches. Differential Revision: https://reviews.llvm.org/D47380 llvm-svn: 333433
* StackColoring: better handling of statically unreachable codeThan McIntosh2018-05-291-2/+5
| | | | | | | | | | | | | | | | Summary: Avoid assert/crash during liveness calculation in situations where the incoming machine function has statically unreachable BBs. Second attempt at submitting; this version of the change includes a revised testcase. Fixes PR37130. Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47372 llvm-svn: 333416
* [CodeGenPrepare] Revert r331783Guozhi Wei2018-05-251-41/+0
| | | | | | The patch r331783 caused regression in one of our internal application. So revert it now, will investigate it further. llvm-svn: 333305
* [RegUsageInfoCollector] Bugfix for callee saved registers.Jonas Paulsson2018-05-251-11/+59
| | | | | | | | | | | | | | | | | | | | | | | Previously, this pass would look at the (static) set returned by getCallPreservedMask() and add those back as preserved in the case when isSafeForNoCSROpt() returns false. A problem is that a target may have to save some registers even when NoCSROpt takes place. For instance, on SystemZ, the return register is needed upon return from a function. Furthermore, getCallPreservedMask() only includes the registers that the target actually wishes to emit save/restore instructions for. This means that subregs and (fully saved) superregs are missing. This patch instead takes the (dynamic) set returned by target for the function from determineCalleeSaves() and then adds sub/super regs to build the set to be used when building the RegMask for the function. Review: Quentin Colombet, Ulrich Weigand https://reviews.llvm.org/D46315 llvm-svn: 333261
* [DebugInfo] Maintain DI when converting GEP to bitcastVedant Kumar2018-05-241-0/+1
| | | | | | | | | | | When a GEP with all zero indices is converted to bitcast, its DI wasn't copied over to the newly created instruction. This patch fixes that bug. Patch by Kareem Ergawy! Differential Revision: https://reviews.llvm.org/D47347 llvm-svn: 333235
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