summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
* Make machine verifier check the first instruction of the last bundle instead ofAkira Hatanaka2012-06-141-8/+8
| | | | | | the last instruction of a basic block. llvm-svn: 158468
* Make comment slightly more helpful.Lang Hames2012-06-141-1/+1
| | | | llvm-svn: 158467
* misched: disable SSA check pending PR13112.Andrew Trick2012-06-141-2/+4
| | | | llvm-svn: 158461
* sched: fix latency of memory dependence chain edges for consistency.Andrew Trick2012-06-131-13/+21
| | | | | | | | | | | For store->load dependencies that may alias, we should always use TrueMemOrderLatency, which may eventually become a subtarget hook. In effect, we should guarantee at least TrueMemOrderLatency on at least one DAG path from a store to a may-alias load. This should fix the standard mode as well as -enable-aa-sched-mi". llvm-svn: 158380
* sched: Avoid trivially redundant DAG edges. Take the one with higher latency.Andrew Trick2012-06-131-3/+20
| | | | llvm-svn: 158379
* misched: When querying RegisterPressureTracker, always save current and max ↵Andrew Trick2012-06-111-2/+8
| | | | | | pressure. llvm-svn: 158340
* misched: regpressure getMaxPressureDelta, revert accidental checkin.Andrew Trick2012-06-111-8/+2
| | | | llvm-svn: 158339
* Allocate the contents of DwarfDebug's StringMaps in a single big ↵Benjamin Kramer2012-06-092-5/+6
| | | | | | BumpPtrAllocator. llvm-svn: 158265
* Register pressure: added getPressureAfterInstr.Andrew Trick2012-06-091-33/+80
| | | | llvm-svn: 158256
* Sketch a LiveRegMatrix analysis pass.Jakob Stoklund Olesen2012-06-093-0/+296
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The LiveRegMatrix represents the live range of assigned virtual registers in a Live interval union per register unit. This is not fundamentally different from the interference tracking in RegAllocBase that both RABasic and RAGreedy use. The important differences are: - LiveRegMatrix tracks interference per register unit instead of per physical register. This makes interference checks cheaper and assignments slightly more expensive. For example, the ARM D7 reigster has 24 aliases, so we would check 24 physregs before assigning to one. With unit-based interference, we check 2 units before assigning to 2 units. - LiveRegMatrix caches regmask interference checks. That is currently duplicated functionality in RABasic and RAGreedy. - LiveRegMatrix is a pass which makes it possible to insert target-dependent passes between register allocation and rewriting. Such passes could tweak the register assignments with interference checking support from LiveRegMatrix. Eventually, RABasic and RAGreedy will be switched to LiveRegMatrix. llvm-svn: 158255
* Also compute MBB live-in lists in the new rewriter pass.Jakob Stoklund Olesen2012-06-096-89/+32
| | | | | | | | | This deduplicates some code from the optimizing register allocators, and it means that it is now possible to change the register allocators' solutions simply by editing the VirtRegMap between the register allocator pass and the rewriter. llvm-svn: 158249
* Reintroduce VirtRegRewriter.Jakob Stoklund Olesen2012-06-087-78/+121
| | | | | | | | | | | | | | | | | | OK, not really. We don't want to reintroduce the old rewriter hacks. This patch extracts virtual register rewriting as a separate pass that runs after the register allocator. This is possible now that CodeGen/Passes.cpp can configure the full optimizing register allocator pipeline. The rewriter pass uses register assignments in VirtRegMap to rewrite virtual registers to physical registers, and it inserts kill flags based on live intervals. These finalization steps are the same for the optimizing register allocators: RABasic, RAGreedy, and PBQP. llvm-svn: 158244
* Start implementing pre-ra if-converter: using speculation and selects to ↵Evan Cheng2012-06-081-6/+15
| | | | | | eliminate branches. llvm-svn: 158234
* TargetInstrInfo hooks implemented in codegen should be declared pure virtual.Andrew Trick2012-06-081-13/+13
| | | | llvm-svn: 158233
* Fix Target->Codegen dependence.Andrew Trick2012-06-081-0/+200
| | | | | | | | | | | | | | | | | Bulk move of TargetInstrInfo implementation into TargetInstrInfoImpl. This is dirty because the code isn't part of TargetInstrInfoImpl class, nor should it be, because the methods are not target hooks. However, it's the current mechanism for keeping libTarget useful outside the backend. You'll get a not-so-nice link error if you invoke a TargetInstrInfo method that depends on CodeGen. The TargetInstrInfoImpl class should probably be removed since it doesn't really solve this problem. To really fix this, we probably need separate interfaces for the CodeGen/nonCodeGen sides of TargetInstrInfo. llvm-svn: 158212
* Move terminator machine verification to check ↵Pete Cooper2012-06-071-11/+11
| | | | | | MachineBasicBlock::instr_iterator instead of MBB::iterator llvm-svn: 158154
* Revert r157755.Manman Ren2012-06-061-1/+0
| | | | | | | | The commit is intended to fix rdar://11540023. It is implemented as part of peephole optimization. We can actually implement this in the SelectionDAG lowering phase. llvm-svn: 158122
* Properly verify liveness with bundled machine instructions.Jakob Stoklund Olesen2012-06-061-13/+34
| | | | | | | | Bundles should be treated as one atomic transaction when checking liveness. That is how the register allocator (and VLIW targets) treats bundles. llvm-svn: 158116
* Move RegisterClassInfo.h.Andrew Trick2012-06-0611-143/+11
| | | | | | Allow targets to access this API. It's required for RegisterPressure. llvm-svn: 158102
* Move RegisterPressure.h.Andrew Trick2012-06-064-258/+3
| | | | | | Make it a general utility for use by Targets. llvm-svn: 158097
* Round 2 of dead private variable removal.Benjamin Kramer2012-06-062-4/+1
| | | | | | | | LLVM is now -Wunused-private-field clean except for - lib/MC/MCDisassembler/Disassembler.h. Not sure why it keeps all those unaccessible fields. - gtest. llvm-svn: 158096
* Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer2012-06-066-8/+5
| | | | | | | | There are some that I didn't remove this round because they looked like obvious stubs. There are dead variables in gtest too, they should be fixed upstream. llvm-svn: 158090
* Remove dead debug option -disable-rematerialization.Jakob Stoklund Olesen2012-06-061-4/+0
| | | | | | | Remat has been stable for years, and it isn't done by LiveIntervalAnalysis any longer. (See LiveRangeEdit). llvm-svn: 158079
* Stop leaking RegScavengers from TailDuplication.Benjamin Kramer2012-06-061-3/+4
| | | | llvm-svn: 158069
* Move LiveUnionArray into LiveIntervalUnion.hJakob Stoklund Olesen2012-06-054-47/+54
| | | | | | It is useful outside RegAllocBase. llvm-svn: 158041
* Don't print register names in LiveIntervalUnion::print().Jakob Stoklund Olesen2012-06-053-5/+2
| | | | | | | | Soon we'll be making LiveIntervalUnions for register units as well. This was the only place using the RepReg member, so just remove it. llvm-svn: 158038
* Suppress -Wunused-variable in -Asserts buildMatt Beaumont-Gay2012-06-051-0/+1
| | | | llvm-svn: 158037
* Simplify LiveInterval::print().Jakob Stoklund Olesen2012-06-054-48/+19
| | | | | | | | | | Don't print out the register number and spill weight, making the TRI argument unnecessary. This allows callers to interpret the reg field. It can currently be a virtual register, a physical register, a spill slot, or a register unit. llvm-svn: 158031
* Add experimental support for register unit liveness.Jakob Stoklund Olesen2012-06-051-0/+130
| | | | | | | | | | | | | | | | Instead of computing a live interval per physreg, LiveIntervals can compute live intervals per register unit. This makes impossible the confusing situation where aliasing registers could have overlapping live intervals. It should also make fixed interferernce checking cheaper since registers have fewer register units than aliases. Live intervals for regunits are computed on demand, using MRI use-def chains and the new LiveRangeCalc class. Only regunits live in to ABI blocks are precomputed during LiveIntervals::runOnMachineFunction(). The regunit liveness computations don't depend on LiveVariables. llvm-svn: 158029
* Implement LiveRangeCalc::extendToUses() and createDeadDefs().Jakob Stoklund Olesen2012-06-053-2/+103
| | | | | | | These LiveRangeCalc methods are to be used when computing a live range from scratch. llvm-svn: 158027
* MachineInstr::eraseFromParent fix for removing bundled instrs.Andrew Trick2012-06-051-1/+2
| | | | | | Patch by Ivan Llopard. llvm-svn: 158025
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-054-99/+100
| | | | | | | Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. llvm-svn: 158021
* Add a new intrinsic: llvm.fmuladd. This intrinsic represents a multiply-addLang Hames2012-06-051-0/+21
| | | | | | | | | | | | expression (a * b + c) that can be implemented as a fused multiply-add (fma) if the target determines that this will be more efficient. This intrinsic will be used to implement FP_CONTRACT support and an aggressive FMA formation mode. If your target has a fast FMA instruction you should override the isFMAFasterThanMulAndAdd method in TargetLowering to return true. llvm-svn: 158014
* misched: Added MultiIssueItineraries.Andrew Trick2012-06-052-5/+5
| | | | | | | | This allows a subtarget to explicitly specify the issue width and other properties without providing pipeline stage details for every instruction. llvm-svn: 157979
* sdsched: Use the right heuristics when -mcpu is not provided and we have no ↵Andrew Trick2012-06-051-13/+12
| | | | | | | | itinerary. Use ILP heuristics for long latency instrs if no scoreboard exists. llvm-svn: 157978
* misched: Allow disabling scoreboard hazard checking for subtargets with aAndrew Trick2012-06-051-6/+12
| | | | | | | | valid itinerary but no pipeline stages. An itinerary can contain useful scheduling information without specifying pipeline stages for each instruction. llvm-svn: 157977
* misched: comments from code review.Andrew Trick2012-06-051-3/+3
| | | | llvm-svn: 157975
* Remove the last remat-related code from LiveIntervalAnalysis.Jakob Stoklund Olesen2012-06-051-95/+0
| | | | | | Rematerialization is handled by LiveRangeEdit now. llvm-svn: 157974
* Stop using LiveIntervals::isReMaterializable().Jakob Stoklund Olesen2012-06-051-9/+24
| | | | | | | | | | It is an old function that does a lot more than required by CalcSpillWeights, which was the only remaining caller. The isRematerializable() function never actually sets the isLoad argument, so don't try to compute that. llvm-svn: 157973
* Delete dead code.Jakob Stoklund Olesen2012-06-041-8/+0
| | | | llvm-svn: 157963
* Switch LiveIntervals member variable to LLVM naming standards.Jakob Stoklund Olesen2012-06-041-57/+57
| | | | | | No functional change. llvm-svn: 157957
* Pass context pointers to LiveRangeCalc::reset().Jakob Stoklund Olesen2012-06-043-55/+45
| | | | | | | Remove the same pointers from all the other LiveRangeCalc functions, simplifying the interface. llvm-svn: 157941
* Remove the "-promote-elements" flag. This flag is now enabled by default.Nadav Rotem2012-06-041-12/+1
| | | | llvm-svn: 157925
* Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer2012-06-029-14/+14
| | | | llvm-svn: 157885
* PR1255: case ranges.Stepan Dyatkovskiy2012-06-021-3/+3
| | | | | | IntRange converted from struct to class. So main change everywhere is replacement of ".Low/High" with ".getLow/getHigh()" llvm-svn: 157884
* PR1255: case ranges.Stepan Dyatkovskiy2012-06-021-1/+1
| | | | | | IntegersSubsetGeneric, IntegersSubsetMapping: added IntTy template parameter, that allows use either APInt or IntItem. This change allows to write unittest for these classes. llvm-svn: 157880
* Fix a bug in the code which custom-lowers truncating stores in LegalizeDAG.Akira Hatanaka2012-06-021-2/+3
| | | | | | | Check that the SDValue TargetLowering::LowerOperation returns is not null before replacing the original node with the returned node. llvm-svn: 157873
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-0130-203/+180
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* Remove physreg support from adjustCopiesBackFrom and removeCopyByCommutingDef.Jakob Stoklund Olesen2012-06-011-29/+3
| | | | | | | After physreg coalescing was disabled, these functions can't do anything useful with physregs anyway. llvm-svn: 157849
* Simplify some more getAliasSet callers.Jakob Stoklund Olesen2012-06-013-27/+15
| | | | | | MCRegAliasIterator can include Reg itself in the list. llvm-svn: 157848
OpenPOWER on IntegriCloud