summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
...
* Switch some getAliasSet clients to MCRegAliasIterator.Jakob Stoklund Olesen2012-06-015-80/+36
| | | | | | | MCRegAliasIterator can optionally visit the register itself, allowing for simpler code. llvm-svn: 157837
* ARM: properly handle alignment for struct byval.Manman Ren2012-06-011-0/+24
| | | | | | | | | Factor out the expansion code into a function. This change is to be enabled in clang. rdar://9877866 llvm-svn: 157830
* PR1255: case ranges.Stepan Dyatkovskiy2012-06-011-1/+1
| | | | | | | IntegersSubset devided into IntegersSubsetGeneric and into IntegersSubset itself. The first has no references to ConstantInt and works with IntItem only. IntegersSubsetMapping also made generic. Here added second template parameter "IntegersSubsetTy" that allows to use on of two IntegersSubset types described below. llvm-svn: 157815
* quick fix for PR13006, will check in testcase later.Chris Lattner2012-06-011-1/+3
| | | | llvm-svn: 157813
* enhance the logic for looking through tailcalls to look through transparent ↵Chris Lattner2012-06-011-1/+21
| | | | | | | | | casts in multiple-return value scenarios, like what happens on X86-64 when returning small structs. llvm-svn: 157800
* enhance getNoopInput to know about vector<->vector bitcasts of legalChris Lattner2012-06-011-10/+38
| | | | | | | | types, as well as int<->ptr casts. This allows us to tailcall functions with some trivial casts between the call and return (i.e. because the return types disagree). llvm-svn: 157798
* rearrange some logic, no functionality change.Chris Lattner2012-06-011-24/+32
| | | | llvm-svn: 157796
* Add support for enum forward declarations.Eric Christopher2012-06-011-6/+7
| | | | | | Part of rdar://11570854 llvm-svn: 157786
* X86: replace SUB with CMP if possibleManman Ren2012-05-311-0/+1
| | | | | | | | | | | | | | | | | This patch will optimize the following movq %rdi, %rax subq %rsi, %rax cmovsq %rsi, %rdi movq %rdi, %rax to cmpq %rsi, %rdi cmovsq %rsi, %rdi movq %rdi, %rax Perform this optimization if the actual result of SUB is not used. rdar: 11540023 llvm-svn: 157755
* Prioritize smaller register classes for urgent evictions.Jakob Stoklund Olesen2012-05-301-1/+7
| | | | | | | | | | | | | | It helps compile exotic inline asm. In the test case, normal GR32 virtual registers use up eax-edx so the final GR32_ABCD live range has no registers left. Since all the live ranges were tiny, we had no way of prioritizing the smaller register class. This patch allows tiny unspillable live ranges to be evicted by tiny unspillable live ranges from a smaller register class. <rdar://problem/11542429> llvm-svn: 157715
* Switch the canonical FMA term operand order to match both the comment I ↵Owen Anderson2012-05-301-1/+1
| | | | | | wrote and the usual LLVM convention. llvm-svn: 157708
* Teach DAGCombine to canonicalize the position of a constant in the term ↵Owen Anderson2012-05-301-0/+4
| | | | | | operands of an FMA node. llvm-svn: 157707
* Remove extra space.Chad Rosier2012-05-301-1/+1
| | | | llvm-svn: 157706
* Remove some redundant tests.Jakob Stoklund Olesen2012-05-301-3/+1
| | | | | | | An empty list is not represented as a null pointer. Let TRI do its own shortcuts. llvm-svn: 157702
* Teach taildup to update livein set. rdar://11538365Evan Cheng2012-05-301-0/+25
| | | | llvm-svn: 157663
* If-converter models predicated defs as read + write. The read should be ↵Evan Cheng2012-05-301-1/+2
| | | | | | marked as 'undef' since it may not already be live. This appeases -verify-machineinstrs. llvm-svn: 157662
* Add an insertPass API to TargetPassConfig. <rdar://problem/11498613>Bob Wilson2012-05-303-0/+49
| | | | | | | | | | Besides adding the new insertPass function, this patch uses it to enhance the existing -print-machineinstrs so that the MachineInstrs after a specific pass can be printed. Patch by Bin Zeng! llvm-svn: 157655
* Optional def can be either a def or a use (of reg0).Evan Cheng2012-05-291-1/+1
| | | | llvm-svn: 157640
* Clear the entering, exiting and internal ranges of a bundle before collectingLang Hames2012-05-291-0/+3
| | | | | | | | | | ranges for the instruction about to be bundled. This fixes a bug in an external project where an assertion was triggered due to spurious 'multiple defs' within the bundle. Patch by Ivan Llopard. Thanks Ivan! llvm-svn: 157632
* ConstantRangesSet renamed to IntegersSubset. CRSBuilder renamed to ↵Stepan Dyatkovskiy2012-05-291-2/+2
| | | | | | IntegersSubsetMapping. llvm-svn: 157612
* Add llvm.fabs intrinsic.Peter Collingbourne2012-05-281-0/+5
| | | | llvm-svn: 157594
* PR1255: Case RangesStepan Dyatkovskiy2012-05-281-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | Implemented IntItem - the wrapper around APInt. Why not to use APInt item directly right now? 1. It will very difficult to implement case ranges as series of small patches. We got several large and heavy patches. Each patch will about 90-120 kb. If you replace ConstantInt with APInt in SwitchInst you will need to changes at the same time all Readers,Writers and absolutely all passes that uses SwitchInst. 2. We can implement APInt pool inside and save memory space. E.g. we use several switches that works with 256 bit items (switch on signatures, or strings). We can avoid value duplicates in this case. 3. IntItem can be easyly easily replaced with APInt. 4. Currenly we can interpret IntItem both as ConstantInt and as APInt. It allows to provide SwitchInst methods that works with ConstantInt for non-updated passes. Why I need it right now? Currently I need to update SimplifyCFG pass (EqualityComparisons). I need to work with APInts directly a lot, so peaces of code ConstantInt *V = ...; if (V->getValue().ugt(AnotherV->getValue()) { ... } will look awful. Much more better this way: IntItem V = ConstantIntVal->getValue(); if (AnotherV < V) { } Of course any reviews are welcome. P.S.: I'm also going to rename ConstantRangesSet to IntegersSubset, and CRSBuilder to IntegersSubsetMapping (allows to map individual subsets of integers to the BasicBlocks). Since in future these classes will founded on APInt, it will possible to use them in more generic ways. llvm-svn: 157576
* Have getOrCreateSubprogramDIE store the DIE for a subprogramPeter Collingbourne2012-05-271-5/+5
| | | | | | | | | definition in the map before calling itself to retrieve the DIE for the declaration. Without this change, if this causes getOrCreateSubprogramDIE to be recursively called on the definition, it will create multiple DIEs for that definition. Fixes PR12831. llvm-svn: 157541
* Missed parens.Benjamin Kramer2012-05-271-1/+1
| | | | llvm-svn: 157527
* r157525 didn't work, just disable iterator checking.Benjamin Kramer2012-05-271-1/+1
| | | | | | | This is obviosly right but I don't see how to do this with proper vector iterators without building a horrible mess of workarounds. llvm-svn: 157526
* SDAGBuilder: Avoid iterator invalidation harder.Benjamin Kramer2012-05-271-1/+1
| | | | | | vector.begin()-1 is invalid too. llvm-svn: 157525
* SDAGBuilder: Don't create an invalid iterator when there is only one switch ↵Benjamin Kramer2012-05-261-2/+2
| | | | | | | | case. Found by libstdc++'s debug mode. llvm-svn: 157522
* SelectionDAGBuilder: When emitting small compare chains for switches order ↵Benjamin Kramer2012-05-261-3/+18
| | | | | | | | | | | | | | them by using edge weights. SimplifyCFG tends to form a lot of 2-3 case switches when merging branches. Move the most likely condition to the front so it is checked first and the others can be skipped. This is currently not as effective as it could be because SimplifyCFG destroys profiling metadata when merging branches and switches. Merging branch weight metadata is tricky though. This code touches at most 3 cases so I didn't use a proper sorting algorithm. llvm-svn: 157521
* ScoreboardHazardRecognizer: Remove dead conditional in debug code.Benjamin Kramer2012-05-261-2/+1
| | | | | | Negative cycles are filtered out earlier. llvm-svn: 157514
* Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCallJustin Holewinski2012-05-255-81/+91
| | | | | | | | | | to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB llvm-svn: 157479
* misched: trace formattingAndrew Trick2012-05-252-7/+7
| | | | llvm-svn: 157455
* Simplify code for calling a function where CanLowerReturn fails, fixing a ↵Eli Friedman2012-05-252-35/+11
| | | | | | small bug in the process. llvm-svn: 157446
* Silence unused variable warnings from when assertions are disabled.Kaelyn Uhrain2012-05-241-0/+2
| | | | llvm-svn: 157438
* misched: Use the same scheduling heuristics with -misched-topdown/bottomup.Andrew Trick2012-05-241-2/+16
| | | | | | (except the part about choosing direction) llvm-svn: 157437
* misched: Trace regpressure.Andrew Trick2012-05-241-2/+4
| | | | llvm-svn: 157429
* misched: Give each ReadyQ a unique IDAndrew Trick2012-05-241-36/+45
| | | | llvm-svn: 157428
* misched: Added ScoreboardHazardRecognizer.Andrew Trick2012-05-242-49/+240
| | | | | | | | | | | | | | | | | | | The Hazard checker implements in-order contraints, or interlocked resources. Ready instructions with hazards do not enter the available queue and are not visible to other heuristics. The major code change is the addition of SchedBoundary to encapsulate the state at the top or bottom of the schedule, including both a pending and available queue. The scheduler now counts cycles in sync with the hazard checker. These are minimum cycle counts based on known hazards. Targets with no itinerary (x86_64) currently remain at cycle 0. To fix this, we need to provide some maximum issue width for all targets. We also need to add the concept of expected latency vs. minimum latency. llvm-svn: 157427
* misched: Release bottom roots in reverse order.Andrew Trick2012-05-241-9/+23
| | | | llvm-svn: 157426
* misched: rename ReadyQ classAndrew Trick2012-05-241-8/+9
| | | | llvm-svn: 157425
* misched: copy comments so compareRPDelta is readable by itself.Andrew Trick2012-05-241-1/+4
| | | | llvm-svn: 157424
* regpressure: Added RegisterPressure::dumpAndrew Trick2012-05-242-0/+20
| | | | llvm-svn: 157423
* regpressure: physreg livein/out fixAndrew Trick2012-05-241-2/+2
| | | | llvm-svn: 157422
* Mark some static arrays as const.Craig Topper2012-05-241-1/+1
| | | | llvm-svn: 157377
* Add a last resort tryInstructionSplit() to RAGreedy.Jakob Stoklund Olesen2012-05-231-1/+65
| | | | | | | | | | | | | Live ranges with a constrained register class may benefit from splitting around individual uses. It allows the remaining live range to use a larger register class where it may allocate. This is like spilling to a different register class. This is only attempted on constrained register classes. <rdar://problem/11438902> llvm-svn: 157354
* Forgot to reverse conditional.Bill Wendling2012-05-231-1/+1
| | | | llvm-svn: 157349
* Reduce indentation by early detection of 'continue'. No functionality change.Bill Wendling2012-05-231-79/+87
| | | | llvm-svn: 157348
* Correctly deal with identity copies in RegisterCoalescer.Jakob Stoklund Olesen2012-05-231-7/+18
| | | | | | | | | | | | | | | | | Now that the coalescer keeps live intervals and machine code in sync at all times, it needs to deal with identity copies differently. When merging two virtual registers, all identity copies are removed right away. This means that other identity copies must come from somewhere else, and they are going to have a value number. Deal with such copies by merging the value numbers before erasing the copy instruction. Otherwise, we leave dangling value numbers in the live interval. This fixes PR12927. llvm-svn: 157340
* Small fix for the debug output from PBQP (PR12822).Patrik Hägglund2012-05-231-3/+4
| | | | llvm-svn: 157319
* Add support for C++11 enum classes in llvm.Eric Christopher2012-05-231-0/+5
| | | | | | Part of rdar://11496790 llvm-svn: 157303
* Untabify and 80-col.Eric Christopher2012-05-221-17/+17
| | | | llvm-svn: 157274
OpenPOWER on IntegriCloud