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* Revert r288212 due to lldb failure.Paul Robinson2016-11-293-54/+11
| | | | llvm-svn: 288216
* Emit 'no line' information for interesting 'orphan' instructions.Paul Robinson2016-11-293-11/+54
| | | | | | | | | | | | DWARF specifies that "line 0" really means "no appropriate source location" in the line table. Use this for branch targets and some other cases that have no specified source location, to prevent inheriting unfortunate line numbers from physically preceding instructions (which might be from completely unrelated source). Differential Revision: http://reviews.llvm.org/D24180 llvm-svn: 288212
* [LiveRangeEdit] Handle instructions with no defs correctly.Geoff Berry2016-11-291-1/+2
| | | | | | | | | | | | | | | | Summary: The code in LiveRangeEdit::eliminateDeadDef() that computes isOrigDef doesn't handle instructions in which operand 0 is not a def (e.g. KILL) correctly. Add a check that operand 0 is a def before doing the rest of the isOrigDef computation. Reviewers: qcolombet, MatzeB, wmi Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D27174 llvm-svn: 288189
* Test commit. Comment changes. NFC.Warren Ristow2016-11-291-5/+5
| | | | llvm-svn: 288100
* Recognize ${:uid} escapes in intel syntax inline asmReid Kleckner2016-11-291-0/+17
| | | | | | | | It looks like this logic was duplicated long ago and the GCC side of things has grown additional functionality. We need ${:uid} at least to generate unique MS inline asm labels (PR23715), so expose these. llvm-svn: 288092
* [DAG] clean up foldSelectCCToShiftAnd(); NFCISanjay Patel2016-11-281-35/+35
| | | | llvm-svn: 288088
* [DAG] add helper function for selectcc --> and+shift transforms; NFCSanjay Patel2016-11-281-42/+51
| | | | llvm-svn: 288073
* [DebugInfo] Add support for DW_AT_main_subprogram on subprogramsDavid Blaikie2016-11-281-0/+3
| | | | | | Patch by Tom Tromey! (for use with Rust) llvm-svn: 288068
* MachineScheduler: Export function to construct "default" scheduler.Matthias Braun2016-11-281-20/+12
| | | | | | | | | | | | | | | | | | This makes the createGenericSchedLive() function that constructs the default scheduler available for the public API. This should help when you want to get a scheduler and the default list of DAG mutations. This also shrinks the list of default DAG mutations: {Load|Store}ClusterDAGMutation and MacroFusionDAGMutation are no longer added by default. Targets can easily add them if they need them. It also makes it easier for targets to add alternative/custom macrofusion or clustering mutations while staying with the default createGenericSchedLive(). It also saves the callback back and forth in TargetInstrInfo::enableClusterLoads()/enableClusterStores(). Differential Revision: https://reviews.llvm.org/D26986 llvm-svn: 288057
* Revert r287553: [CodeGenPrep] Skip merging empty case blocksJoerg Sonnenberger2016-11-281-135/+32
| | | | | | | It results in assertions in lib/Analysis/BlockFrequencyInfoImpl.cpp line 670 ("Expected irreducible CFG"). llvm-svn: 288052
* Revert "[DAG] Improve loads-from-store forwarding to handle TokenFactor"Nirav Dave2016-11-281-13/+2
| | | | | | This reverts commit r287773 which caused issues with ppc64le builds. llvm-svn: 288035
* Use SDValue helpers instead of explicitly going via SDValue::getNode(). NFCISimon Pilgrim2016-11-251-7/+7
| | | | llvm-svn: 287941
* [DAGCombine] Teach DAG combine that if both inputs of a vselect are the ↵Craig Topper2016-11-241-0/+4
| | | | | | | | same, then the condition doesn't matter and the vselect can be removed. Selects with scalar condition already handle this correctly. llvm-svn: 287904
* Test commit access.Serge Rogatch2016-11-241-0/+1
| | | | llvm-svn: 287898
* TRI: Add hook to pass scavenger during frame eliminationMatt Arsenault2016-11-241-4/+11
| | | | | | | | | | | | The scavenger was not passed if requiresFrameIndexScavenging was enabled. I need to be able to test for the availability of an unallocatable register here, so I can't create a virtual register for it. It might be better to just always use the scavenger and stop creating virtual registers. llvm-svn: 287843
* Rely on a single DWARF version instead of having two copiesGreg Clayton2016-11-236-16/+21
| | | | | | | | This patch makes AsmPrinter less reliant on DwarfDebug by relying on the DWARF version in the AsmPrinter's MCStreamer's MCContext. This allows us to remove the redundant DWARF version from DwarfDebug. It also lets us change code that used to access the AsmPrinter's DwarfDebug just to get to the DWARF version by changing the DWARF version accessor on AsmPrinter so that it grabs the version from its MCStreamer's MCContext. Differential Revision: https://reviews.llvm.org/D27032 llvm-svn: 287839
* [SelectionDAG] Early-out in TargetLowering::expandMUL (NFC)Nicolai Haehnle2016-11-231-77/+80
| | | | | | | | | | | | Summary: Reduce indentation level; preparation for D24956. Reviewers: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D27063 llvm-svn: 287831
* [X86] Allow folding of stack reloads when loading a subreg of the spilled regMichael Kuperstein2016-11-232-7/+33
| | | | | | | | | | | | | We did not support subregs in InlineSpiller:foldMemoryOperand() because targets may not deal with them correctly. This adds a target hook to let the spiller know that a target can handle subregs, and actually enables it for x86 for the case of stack slot reloads. This fixes PR30832. Differential Revision: https://reviews.llvm.org/D26521 llvm-svn: 287792
* [DAG] Improve loads-from-store forwarding to handle TokenFactorNirav Dave2016-11-231-2/+13
| | | | | | | | | | | | | Forward store values to matching loads down through token factors. Factored from D14834. Reviewers: jyknight, hfinkel Subscribers: hfinkel, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D26080 llvm-svn: 287773
* [DAGCombiner] Fix infinite loop in vector mul/shl combiningJohn Brawn2016-11-232-18/+15
| | | | | | | | | | | | | | | | | | | | | | We have the following DAGCombiner transformations: (mul (shl X, c1), c2) -> (mul X, c2 << c1) (mul (shl X, C), Y) -> (shl (mul X, Y), C) (shl (mul x, c1), c2) -> (mul x, c1 << c2) Usually the constant shift is optimised by SelectionDAG::getNode when it is constructed, by SelectionDAG::FoldConstantArithmetic, but when we're dealing with vectors and one of those vector constants contains an undef element FoldConstantArithmetic does not fold and we enter an infinite loop. Fix this by making FoldConstantArithmetic use getNode to decide how to fold each vector element, the same as FoldConstantVectorArithmetic does, and rather than adding the constant shift to the work list instead only apply the transformation if it's already been folded into a constant, as if it's not we're going to loop endlessly. Additionally add missing NoOpaques to one of those transformations, which I noticed when writing the tests for this. Differential Revision: https://reviews.llvm.org/D26605 llvm-svn: 287766
* Type legalization for compressstore and expandload intrinsics. Elena Demikhovsky2016-11-233-29/+57
| | | | | | | | Implemented widening (v2f32) and splitting (v16f64). On splitting, I use "popcnt" to calculate memory increment. More type legalization work will come in the next patches. llvm-svn: 287761
* TargetSubtargetInfo: Move implementation to lib/CodeGen; NFCMatthias Braun2016-11-222-0/+55
| | | | | | | | | | | | TargetSubtargetInfo is filled with CodeGen specific interfaces nowadays (getInstrInfo(), getFrameLowering(), getSelectionDAGInfo()) most of the tuning flags like enablePostRAScheduler(), getAntiDepBreakMode(), enableRALocalReassignment(), ... also do not seem to be universal enough to make sense outside of CodeGen. Differential Revision: https://reviews.llvm.org/D26948 llvm-svn: 287708
* Restructure DwarfDebug::beginInstruction(). [NFC]Paul Robinson2016-11-221-21/+26
| | | | | | | | Will help a pending patch. Differential Revision: http://reviews.llvm.org/D26982 llvm-svn: 287686
* CodeGen: simplify TargetMachine::getSymbol interface. NFC.Tim Northover2016-11-222-12/+11
| | | | | | | | | No-one actually had a mangler handy when calling this function, and getSymbol itself went most of the way towards getting its own mangler (with a local TLOF variable) so forcing all callers to supply one was just extra complication. llvm-svn: 287645
* [SelectionDAG] ComputeNumSignBits of TRUNCATE operationsSimon Pilgrim2016-11-221-3/+7
| | | | | | | | | | Add basic ComputeNumSignBits support for TRUNCATE ops for cases where the source's number of sign bits overlaps with the truncated size. Improves X86 SIGN_EXTEND_IN_REG vector cases which were needlessly sign extending boolean vector results. Differential Revision: https://reviews.llvm.org/D26851 llvm-svn: 287635
* DAG: Ignore call site attributes when emitting target intrinsicMatt Arsenault2016-11-211-2/+6
| | | | | | | | | | A target intrinsic may be defined as possibly reading memory, but the call site may have additional knowledge that it doesn't read memory. The intrinsic lowering will expect the pessimistic assumption of the intrinsic definition, so the chain should still be used. llvm-svn: 287593
* [CodeGenPrepare] Don't sink non-cheap addrspacecasts.Justin Lebar2016-11-211-0/+8
| | | | | | | | | | | | | | | | | | | | Summary: Previously, CGP would unconditionally sink addrspacecast instructions, even going so far as to sink them into a loop. Now we check that the cast is "cheap", as defined by TLI. We introduce a new "is-cheap" function to TLI rather than using isNopAddrSpaceCast because some GPU platforms want the ability to ask for non-nop casts to be sunk. Reviewers: arsenm, tra Subscribers: jholewinski, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D26923 llvm-svn: 287591
* [CodeGenPrepare] Rewrite a loop in terms of llvm::none_of. NFC.Justin Lebar2016-11-211-11/+3
| | | | | | | | | | Reviewers: arsenm Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D26924 llvm-svn: 287590
* Check proper live range in extendPHIRangesKrzysztof Parzyszek2016-11-212-7/+17
| | | | | | | | | | | | | The function extendPHIRanges checks the main range of the original live interval, even when dealing with a subrange. This could also lead to an assert when the subrange is not live at the extension point, but the main range is. To avoid this, check the corresponding subrange of the original live range, instead of always checking the main range. Review (as a part of a bigger set of changes): https://reviews.llvm.org/D26359 llvm-svn: 287571
* [AsmPrinter] Enable codeview for windows-itaniumShoaib Meenai2016-11-211-1/+2
| | | | | | | | | | Enable codeview emission for windows-itanium targets. Co-opt an existing test (which is derived from a C source file and should therefore be identical across the Itanium and MS ABIs). Differential Revision: https://reviews.llvm.org/D26693 llvm-svn: 287567
* [VectorLegalizer] Remove EVT::getSizeInBits code duplications. NFCI.Simon Pilgrim2016-11-211-8/+6
| | | | | | We were calling SVT.getSizeInBits() several times in a row - just call it once and reuse the result. llvm-svn: 287556
* [CodeGenPrep] Skip merging empty case blocksJun Bum Lim2016-11-211-32/+135
| | | | | | | | | | | | | | | | Summary: Merging an empty case block into the header block of switch could cause ISel to add COPY instructions in the header of switch, instead of the case block, if the case block is used as an incoming block of a PHI. This could potentially increase dynamic instructions, especially when the switch is in a loop. I added a test case which was reduced from the benchmark I was targetting. Reviewers: t.p.northover, mcrosier, manmanren, wmi, davidxl Subscribers: qcolombet, danielcdh, hfinkel, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D22696 llvm-svn: 287553
* [SelectionDAG] Add ComputeNumSignBits support for CONCAT_VECTORS opcodeSimon Pilgrim2016-11-211-0/+7
| | | | llvm-svn: 287541
* Fix comment typos. NFC.Simon Pilgrim2016-11-203-4/+4
| | | | | | Identified by Pedro Giffuni in PR27636. llvm-svn: 287490
* Fix spelling mistakes in SelectionDAG comments. NFC.Simon Pilgrim2016-11-204-5/+5
| | | | | | Identified by Pedro Giffuni in PR27636. llvm-svn: 287487
* [SelectionDAG] Add knowbits support for CONCAT_VECTOR opcodeSimon Pilgrim2016-11-181-0/+18
| | | | llvm-svn: 287387
* Timer: Track name and description.Matthias Braun2016-11-186-44/+76
| | | | | | | | | | | | | The previously used "names" are rather descriptions (they use multiple words and contain spaces), use short programming language identifier like strings for the "names" which should be used when exporting to machine parseable formats. Also removed a unused TimerGroup from Hexxagon. Differential Revision: https://reviews.llvm.org/D25583 llvm-svn: 287369
* [MIRPrinter] Print raw branch probabilities as expected by MIRParserGeoff Berry2016-11-182-2/+6
| | | | | | | | | | | | Fixes PR28751. Reviewers: MatzeB, qcolombet Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D26775 llvm-svn: 287368
* GlobalISel: Fix unconditional fallback with global isel abort is disabledTom Stellard2016-11-181-1/+1
| | | | | | | | | | Reviewers: t.p.northover, ab, qcolombet Subscribers: mehdi_amini, vkalintiris, wdng, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D26765 llvm-svn: 287344
* MachineOperand: Add dump() methodMatthias Braun2016-11-181-0/+6
| | | | llvm-svn: 287302
* Fix spelling in comment. NFC.Simon Pilgrim2016-11-171-1/+1
| | | | llvm-svn: 287222
* Delete dead code and add asserts instead; NFCSanjoy Das2016-11-171-7/+3
| | | | llvm-svn: 287214
* [ImplicitNullCheck] Fix an edge case where we were hoisting incorrectlySanjoy Das2016-11-171-1/+19
| | | | | | | | | | | | | | | ImplicitNullCheck keeps track of one instruction that the memory operation depends on that it also hoists with the memory operation. When hoisting this dependency, it would sometimes clobber a live-in value to the basic block we were hoisting the two things out of. Fix this by explicitly looking for such dependencies. I also noticed two redundant checks on `MO.isDef()` in IsMIOperandSafe. They're redundant since register MachineOperands are either Defs or Uses -- there is no third kind. I'll change the checks to asserts in a later commit. llvm-svn: 287213
* [XRay] Support AArch64 in LLVMDean Michael Berris2016-11-171-0/+1
| | | | | | | | | | | | | | | | | | This patch adds XRay support in LLVM for AArch64 targets. This patch is one of a series: Clang: https://reviews.llvm.org/D26415 compiler-rt: https://reviews.llvm.org/D26413 Author: rSerge Reviewers: rengolin, dberris Subscribers: amehsan, aemerson, llvm-commits, iid_iunknown Differential Revision: https://reviews.llvm.org/D26412 llvm-svn: 287209
* [CMake] NFC. Updating CMake dependency specificationsChris Bieneman2016-11-175-10/+15
| | | | | | This patch updates a bunch of places where add_dependencies was being explicitly called to add dependencies on intrinsics_gen to instead use the DEPENDS named parameter. This cleanup is needed for a patch I'm working on to add a dependency debugging mode to the build system. llvm-svn: 287206
* [CodeGen] Pass references, not pointers, to MMI helpers. NFC.Ahmed Bougacha2016-11-164-13/+13
| | | | | | While there, rename them to follow the coding style. llvm-svn: 287169
* Revert "Get GlobalISel to build on Linux after r286407"Ahmed Bougacha2016-11-161-1/+1
| | | | | | | | | This reverts commit r286962. We want to avoid depending on SelectionDAG, and AddLandingPadInfo lives in CodeGen now. llvm-svn: 287168
* [CodeGen] Pull MMI helpers from FunctionLoweringInfo to MMI. NFC.Ahmed Bougacha2016-11-163-57/+51
| | | | | | | | | | | They're not SelectionDAG- or FunctionLoweringInfo-specific. They are, however, specific to building MMI from IR. We could make them members, but it's nice having MMI be a "simple" data structure and this logic kept separate. This also lets us reuse them from GlobalISel. llvm-svn: 287167
* [CodeGen] Cleanup MachineModuleInfo doxygen comments. NFC.Ahmed Bougacha2016-11-161-39/+7
| | | | | | Remove redundant names and only keep header comments. llvm-svn: 287166
* [ImplicitNullChecks] Do not not handle call MachineInstrsSanjoy Das2016-11-161-1/+4
| | | | | | | | | | | We don't track callee clobbered registers correctly, so avoid hoisting across calls. Note: for this bug to trigger we need a `readonly` call target, since we already have logic to not hoist across potentially storing instructions either. llvm-svn: 287159
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