| Commit message (Collapse) | Author | Age | Files | Lines |
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checking whether AnalyzeBranch disagrees with the CFG
directly, rather than looking for EH_LABEL instructions.
EH_LABEL instructions aren't always at the end of the
block, due to FP_REG_KILL and other things. This fixes
an infinite loop compiling MultiSource/Benchmarks/Bullet.
llvm-svn: 96611
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Russell Wallace.
llvm-svn: 96580
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out by Russell Wallace.
llvm-svn: 96579
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Transform br (xor (x, y)) -> br (x != y)
Transform br (xor (xor (x,y), 1)) -> br (x == y)
Also normalize (and (X, 1) == / != 1 -> (and (X, 1)) != / == 0 to match to "test on x86" and "tst on arm"
llvm-svn: 96556
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CSE'd or otherwise combined with temporal MemSDNodes.
llvm-svn: 96505
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llvm-svn: 96496
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and add a sparc implementation that knows about delay slots. Patch by
Nathan Keynes!
llvm-svn: 96492
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tblgen splatted code into the implementation.
llvm-svn: 96460
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live-in sets or run the rewriter.
llvm-svn: 96450
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existing scope end marker, if any. Scope must begin before it ends and nested inlined scope do not truncate surrounding scope.
llvm-svn: 96445
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and T->isPointerTy(). Convert most instances of the first form to the second form.
Requested by Chris.
llvm-svn: 96344
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elimination. Before a DBG_VALUE could affect codegen.
The solution here is imperfect and not final.
llvm-svn: 96318
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at older buildbot messages, I see the failure predates
this patch.
llvm-svn: 96307
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but it's harder to believe it's the other candidate,
so reverting. Temporarily I hope.
llvm-svn: 96303
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llvm-svn: 96295
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llvm-svn: 96294
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llvm-svn: 96292
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llvm-svn: 96290
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llvm-svn: 96288
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early beginning! The "z" CIE augmentation mark indicates that there is an extra word containing the size of augmentation section. However, even for frames w/o any augmentation data we emitted size uleb! (this is the case of "unwinding through C code"). Thus frame moves information was emitterd completely wrong.
llvm-svn: 96287
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Personality / FDE / LSDA / TType encoding depending on target / options (e.g. code model / relocation model) - MCIzation of Dwarf EH printer to use encoding information - Stub generation for ELF target (needed for indirect references) - Some other small changes here and there
llvm-svn: 96285
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A virtual register can be used before it is defined in the same MBB if the MBB
is part of a loop. Teach the implicit-def pass about this case.
llvm-svn: 96279
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IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.
This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.
llvm-svn: 96255
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llvm-svn: 96240
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llvm-svn: 96226
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isInteger, we now have isFloatTy and isIntegerTy. Requested by Chris!
llvm-svn: 96223
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llvm-svn: 96207
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When coalescing with a physreg, remember to add imp-def and imp-kill when
dealing with sub-registers.
Also fix a related bug in VirtRegRewriter where substitutePhysReg may
reallocate the operand list on an instruction and invalidate the reg_iterator.
This can happen when a register is mentioned twice on the same instruction.
llvm-svn: 96072
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created. This ensures it's updated at all time. It means targets which perform
dynamic stack alignment would know whether it is required and whether frame
pointer register cannot be made available register allocation.
This is a fix for rdar://7625239. Sorry, I can't create a reasonably sized test
case.
llvm-svn: 96069
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phi cycles. Adjust a few tests to keep dead instructions from being optimized
away. This (together with my previous change for phi cycles) fixes Apple
radar 7627077.
llvm-svn: 96057
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llvm-svn: 96038
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didn't handle
X =
Y<dead> = use X
DBG_VALUE(X)
I was hoping to avoid this approach as it's slower,
but I don't think it can be done.
llvm-svn: 95996
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bug fixes, and with improved heuristics for analyzing foreign-loop
addrecs.
This change also flattens IVUsers, eliminating the stride-oriented
groupings, which makes it easier to work with.
llvm-svn: 95975
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costs.
* Enabled R1/R2 application for nodes with infinite spill costs in the Briggs heuristic (made
safe by the changes to the normalization proceedure).
* Removed a redundant header.
llvm-svn: 95973
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reduce down to a single value. InstCombine already does this transformation
but DAG legalization may introduce new opportunities. This has turned out to
be important for ARM where 64-bit values are split up during type legalization:
InstCombine is not able to remove the PHI cycles on the 64-bit values but
the separate 32-bit values can be optimized. I measured the compile time
impact of this (running llc on 176.gcc) and it was not significant.
llvm-svn: 95951
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This time with fixed test cases.
llvm-svn: 95938
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llvm-svn: 95921
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tiny interval.
Also avoid division by zero.
llvm-svn: 95917
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same dead instruction.
llvm-svn: 95890
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llvm-svn: 95889
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Use SmallVector instead of std::vector for better speed when indirectbr has
few successors.
llvm-svn: 95879
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llvm-svn: 95871
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llvm-svn: 95840
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almost always comments afterwards that need printing.
llvm-svn: 95839
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Calling RemoveOperand is very expensive on huge PHI instructions. This makes
early tail duplication run twice as fast on the Firefox JavaScript
interpreter.
llvm-svn: 95832
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machine CFG.
This makes early tail duplication run 60 times faster when compiling the Firefox
JavaScript interpreter, see PR6186.
llvm-svn: 95831
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on custom
lowering and requires that certain types exist in ValueTypes.h. Modified widening to
check if an op can trap and if so, the widening algorithm will apply only the op on
the defined elements. It is safer to do this in widening because the optimizer can't
guarantee removing unused ops in some cases.
llvm-svn: 95823
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llvm-svn: 95819
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legalization even when the IR-level optimizer has removed dead phis, such
as when the high half of an i64 value is unused on a 32-bit target.
I had to adjust a few test cases that had dead phis.
This is a partial fix for Radar 7627077.
llvm-svn: 95816
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llvm-svn: 95814
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