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* Add a flag to addPassesToEmit* to disable the Verifier pass runDan Gohman2010-02-281-8/+18
| | | | | | after LSR, so that clients can opt in. llvm-svn: 97357
* Don't unconditionally suppress hoisting of instructions with implicitDan Gohman2010-02-281-26/+4
| | | | | | | | defs or uses. The regular def and use checking below covers them, and can be more precise. It's safe to hoist an instruction with a dead implicit def if the register isn't live into the loop header. llvm-svn: 97352
* Re-apply 97040 with fix. This survives a ppc self-host llvm-gcc bootstrap.Evan Cheng2010-02-272-9/+86
| | | | llvm-svn: 97310
* The TType is always absptr on Mach-O...at least for now.Bill Wendling2010-02-271-1/+1
| | | | llvm-svn: 97295
* A much cleaner (and less code!) way of inserting the correct amount of paddingBill Wendling2010-02-261-50/+6
| | | | | | | | for alignment into the LSDA. If the TType base offset is emitted, then put the padding there. Otherwise, put it in the call site table length. There will be no conflict between the two sites when placing the padding in one place. llvm-svn: 97277
* Comment typo.Bill Wendling2010-02-261-1/+1
| | | | llvm-svn: 97269
* Use the right floating point load/store instructions in ↵Jakob Stoklund Olesen2010-02-261-2/+4
| | | | | | | | | | | | | | | | | | PPCInstrInfo::foldMemoryOperandImpl(). The PowerPC floating point registers can represent both f32 and f64 via the two register classes F4RC and F8RC. F8RC is considered a subclass of F4RC to allow cross-class coalescing. This coalescing only affects whether registers are spilled as f32 or f64. Spill slots must be accessed with load/store instructions corresponding to the class of the spilled register. PPCInstrInfo::foldMemoryOperandImpl was looking at the instruction opcode which is wrong. X86 has similar floating point register classes, but doesn't try to fold memory operands, so there is no problem there. llvm-svn: 97262
* Remove dead codeJakob Stoklund Olesen2010-02-261-4/+0
| | | | llvm-svn: 97261
* Move dbg_value generation to target-independent FastISel,Dale Johannesen2010-02-261-0/+28
| | | | | | as X86 is currently the only FastISel target. Per review. llvm-svn: 97255
* Remove unused "NoPRE" parameter in GVN and createGVNPass().Bob Wilson2010-02-261-1/+1
| | | | llvm-svn: 97235
* Fix comments.Bill Wendling2010-02-261-3/+3
| | | | llvm-svn: 97200
* Add another (and hopefully the last) exception case, where once we recalculateBill Wendling2010-02-261-3/+11
| | | | | | | the alignment requirement, if it no longer makes the TType base offset overflow into extra bytes, then we need to pad to those bytes ourselves. llvm-svn: 97196
* And should use the correct variable.Bill Wendling2010-02-261-1/+1
| | | | llvm-svn: 97193
* Got assertion check backwards.Bill Wendling2010-02-261-1/+1
| | | | llvm-svn: 97192
* Catch a corner case where adding the padding to the "TType base offset" fieldBill Wendling2010-02-251-2/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | will eliminate the need for padding in the "Call site table length". E.g., if we have this: GCC_except_table1: Lexception1: .byte 0xff ## @LPStart Encoding = omit .byte 0x9b ## @TType Encoding = indirect pcrel sdata4 .byte 0x7f ## @TType base offset .byte 0x03 ## Call site Encoding = udata4 .byte 0x89 ## Call site table length with padding of 1. We want to emit the padding like this: GCC_except_table1: Lexception1: .byte 0xff ## @LPStart Encoding = omit .byte 0x9b ## @TType Encoding = indirect pcrel sdata4 .byte 0xff ## @TType base offset .space 1,0 ## Padding .byte 0x03 ## Call site Encoding = udata4 .byte 0x89 ## Call site table length and not with padding on the "Call site table length" entry. llvm-svn: 97183
* Make comment more meaningful.Bill Wendling2010-02-251-1/+2
| | | | llvm-svn: 97169
* Fix ExpandVectorBuildThroughStack for the case where theDan Gohman2010-02-251-3/+3
| | | | | | | operands are themselves vectors. Based on a patch by Micah Villmow for PR6338. llvm-svn: 97165
* Revert r97064. Duncan pointed out that bitcasts are defined inDan Gohman2010-02-253-23/+12
| | | | | | | | terms of store and load, which means bitcasting between scalar integer and vector has endian-specific results, which undermines this whole approach. llvm-svn: 97137
* MC'ize padding when padding the ULEB128 value.Bill Wendling2010-02-251-7/+5
| | | | llvm-svn: 97087
* LLVM puts padding bytes in the __gcc_except_tab section after theBill Wendling2010-02-243-41/+52
| | | | | | | | | | GCC_except_table label but before the Lexception, which the FDE references. This causes problems as the FDE does not point to the start of an LSDA chunk. Use an unnormalized uleb128 for the call-site table length that includes the padding. llvm-svn: 97078
* clean up various VT manipulations, patch by Micah Villmow! PR6337Chris Lattner2010-02-241-9/+6
| | | | llvm-svn: 97072
* Make getTypeSizeInBits work correctly for array types; it should returnDan Gohman2010-02-243-12/+23
| | | | | | | | | | | | | | | the number of value bits, not the number of bits of allocation for in-memory storage. Make getTypeStoreSize and getTypeAllocSize work consistently for arrays and vectors. Fix several places in CodeGen which compute offsets into in-memory vectors to use TargetData information. This fixes PR1784. llvm-svn: 97064
* convert cycle checker to smallptrset, add comments and make itChris Lattner2010-02-241-20/+20
| | | | | | more elegant. llvm-svn: 97059
* revert david's patch which does not even build.Chris Lattner2010-02-241-4/+4
| | | | llvm-svn: 97057
* Use a SmallPtrSet as suggested by Chris.David Greene2010-02-241-4/+4
| | | | llvm-svn: 97056
* Speculatively revert r97011, "Re-apply 96540 and 96556 with fixes.", again inDaniel Dunbar2010-02-242-86/+9
| | | | | | the hopes of fixing PPC bootstrap. llvm-svn: 97040
* When forming SSE min and max nodes for UGE and ULE comparisons, it'sDan Gohman2010-02-241-0/+23
| | | | | | | | | | | necessary to swap the operands to handle NaN and negative zero properly. Also, reintroduce logic for checking for NaN conditions when forming SSE min and max instructions, fixed to take into consideration NaNs and negative zeros. This allows forming min and max instructions in more cases. llvm-svn: 97025
* Change the scheduler from adding nodes in allnodes orderChris Lattner2010-02-241-2/+14
| | | | | | | | | | | | | | | | | | to adding them in a determinstic order (bottom up from the root) based on the structure of the graph itself. This updates tests for some random changes, interesting bits: CodeGen/Blackfin/promote-logic.ll no longer crashes. I have no idea why, but that's good right? CodeGen/X86/2009-07-16-LoadFoldingBug.ll also fails, but now compiles to have one fewer constant pool entry, making the expected load that was being folded disappear. Since it is an unreduced mass of gnast, I just removed it. This fixes PR6370 llvm-svn: 97023
* add node #'s to debug dumps.Chris Lattner2010-02-241-3/+3
| | | | llvm-svn: 97019
* Re-apply 96540 and 96556 with fixes.Evan Cheng2010-02-242-9/+86
| | | | llvm-svn: 97011
* make selectnodeto set the nodeid to -1. This makes it more akin toChris Lattner2010-02-231-1/+4
| | | | | | creating a new node then replacing uses. llvm-svn: 97000
* Remember to handle sub-registers when moving imp-defs to a rematted instruction.Jakob Stoklund Olesen2010-02-231-2/+17
| | | | llvm-svn: 96995
* Keep track of phi join registers explicitly in LiveVariables.Jakob Stoklund Olesen2010-02-233-52/+36
| | | | | | | | Previously, LiveIntervalAnalysis would infer phi joins by looking for multiply defined registers. That doesn't work if the phi join is implicitly defined in all but one of the predecessors. llvm-svn: 96994
* fix a bug in findNonImmUse (used by IsLegalToFold) where nodes withChris Lattner2010-02-231-2/+14
| | | | | | | | | | no id's would cause early exit allowing IsLegalToFold to return true instead of false, producing a cyclic dag. This was striking the new isel because it isn't using SelectNodeTo yet, which theoretically is just an optimization. llvm-svn: 96972
* Print node ID's in dumps and views if set.Chris Lattner2010-02-231-0/+3
| | | | llvm-svn: 96971
* use OutStreamer.EmitCodeAlignment for alignment in the textChris Lattner2010-02-231-4/+3
| | | | | | segment. llvm-svn: 96967
* Speed up cycle checking significantly by caching results.David Greene2010-02-231-3/+9
| | | | llvm-svn: 96956
* Dead code eliminationJakob Stoklund Olesen2010-02-232-14/+0
| | | | llvm-svn: 96837
* Updated version of r96634 (which was reverted due to failing 176.gcc andJim Grosbach2010-02-221-3/+4
| | | | | | | | 126.gcc nightly tests. These failures uncovered latent bugs that machine DCE could remove one half of a stack adjust down/up pair, causing PEI to assert. This update fixes that, and the tests now pass. llvm-svn: 96822
* Fix various doxygen warnings.Dan Gohman2010-02-221-2/+2
| | | | llvm-svn: 96779
* It turned out that we failed to emit proper symbol stubs on non-x86/darwin ↵Anton Korobeynikov2010-02-211-1/+29
| | | | | | | | | for ages (we emitted a reference to a stub, but no stub was emitted). The code inside x86-32/macho target objfile lowering should actually be the generic one - move it there. This (I really, really hope) should fix EH issues on ppc/darwin and arm/darwin. llvm-svn: 96755
* Enable assertion to detect cyclic valno references.Jakob Stoklund Olesen2010-02-211-1/+1
| | | | | | This changes the stack overflow in PR6363 to an assertion failure. llvm-svn: 96744
* Revert 96634. It causes assertion failures for 126.gcc and 176.gcc inBob Wilson2010-02-191-4/+3
| | | | | | the armv6 nightly tests. llvm-svn: 96691
* Add support for the 'alignstack' attribute to the x86 backend. Fixes PR5254.Charles Davis2010-02-191-0/+3
| | | | | | Also, FileCheck'ize a test. llvm-svn: 96686
* Revert Anton's most recent EH patch (r96637), since it breaks a lot ofBob Wilson2010-02-191-17/+0
| | | | | | ARM and Thumb tests. llvm-svn: 96680
* Revert commits 96556 and 96640, because commit 96556 breaks theDuncan Sands2010-02-192-80/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dragonegg self-host build. I reverted 96640 in order to revert 96556 (96640 goes on top of 96556), but it also looks like with both of them applied the breakage happens even earlier. The symptom of the 96556 miscompile is the following crash: llvm[3]: Compiling AlphaISelLowering.cpp for Release build cc1plus: /home/duncan/tmp/tmp/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:4982: void llvm::SelectionDAG::ReplaceAllUsesWith(llvm::SDNode*, llvm::SDNode*, llvm::SelectionDAG::DAGUpdateListener*): Assertion `(!From->hasAnyUseOfValue(i) || From->getValueType(i) == To->getValueType(i)) && "Cannot use this version of ReplaceAllUsesWith!"' failed. Stack dump: 0. Running pass 'X86 DAG->DAG Instruction Selection' on function '@_ZN4llvm19AlphaTargetLowering14LowerOperationENS_7SDValueERNS_12SelectionDAGE' g++: Internal error: Aborted (program cc1plus) This occurs when building LLVM using LLVM built by LLVM (via dragonegg). Probably LLVM has miscompiled itself, though it may have miscompiled GCC and/or dragonegg itself: at this point of the self-host build, all of GCC, LLVM and dragonegg were built using LLVM. Unfortunately this kind of thing is extremely hard to debug, and while I did rummage around a bit I didn't find any smoking guns, aka obviously miscompiled code. Found by bisection. r96556 | evancheng | 2010-02-18 03:13:50 +0100 (Thu, 18 Feb 2010) | 5 lines Some dag combiner goodness: Transform br (xor (x, y)) -> br (x != y) Transform br (xor (xor (x,y), 1)) -> br (x == y) Also normalize (and (X, 1) == / != 1 -> (and (X, 1)) != / == 0 to match to "test on x86" and "tst on arm" r96640 | evancheng | 2010-02-19 01:34:39 +0100 (Fri, 19 Feb 2010) | 16 lines Transform (xor (setcc), (setcc)) == / != 1 to (xor (setcc), (setcc)) != / == 1. e.g. On x86_64 %0 = icmp eq i32 %x, 0 %1 = icmp eq i32 %y, 0 %2 = xor i1 %1, %0 br i1 %2, label %bb, label %return => testl %edi, %edi sete %al testl %esi, %esi sete %cl cmpb %al, %cl je LBB1_2 llvm-svn: 96672
* Transform (xor (setcc), (setcc)) == / != 1 toEvan Cheng2010-02-191-3/+13
| | | | | | | | | | | | | | | | | | | (xor (setcc), (setcc)) != / == 1. e.g. On x86_64 %0 = icmp eq i32 %x, 0 %1 = icmp eq i32 %y, 0 %2 = xor i1 %1, %0 br i1 %2, label %bb, label %return => testl %edi, %edi sete %al testl %esi, %esi sete %cl cmpb %al, %cl je LBB1_2 llvm-svn: 96640
* Use the same encoding for EH stuff uniformly on all MachO targets.Anton Korobeynikov2010-02-191-0/+17
| | | | | | This hopefulyl should unbreak EH on PPC/Darwin. llvm-svn: 96637
* Radar 7636153. In the presence of large call frames, it's not sufficientJim Grosbach2010-02-191-3/+4
| | | | | | | | | for ARM to just check if a function has a FP to determine if it's safe to simplify the stack adjustment pseudo ops prior to eliminating frame indices. Allow targets to override the default behavior and does so for ARM and Thumb2. llvm-svn: 96634
* Always normalize spill weights, also for intervals created by spilling.Jakob Stoklund Olesen2010-02-182-4/+10
| | | | | | | | | | | | | | Moderate the weight given to very small intervals. The spill weight given to new intervals created when spilling was not normalized in the same way as the original spill weights calculated by CalcSpillWeights. That meant that restored registers would tend to hang around because they had a much higher spill weight that unspilled registers. This improves the runtime of a few tests by up to 10%, and there are no significant regressions. llvm-svn: 96613
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