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* Replace some code for aggressive-remat with MachineInstr::isInvariantLoad, andDan Gohman2009-10-071-23/+28
| | | | | | teach it how to recognize invariant physical registers. llvm-svn: 83476
* Replace TargetInstrInfo::isInvariantLoad and its target-specificDan Gohman2009-10-074-7/+48
| | | | | | | | | implementations with a new MachineInstr::isInvariantLoad, which uses MachineMemOperands and is target-independent. This brings MachineLICM and other functionality to targets which previously lacked an isInvariantLoad implementation. llvm-svn: 83475
* Add a few simple MachineVerifier checks for MachineMemOperands.Dan Gohman2009-10-071-0/+10
| | | | llvm-svn: 83474
* Add register-reuse to frame-index register scavenging. When a target usesJim Grosbach2009-10-073-22/+129
| | | | | | | | | | | | | | | | | | | | a virtual register to eliminate a frame index, it can return that register and the constant stored there to PEI to track. When scavenging to allocate for those registers, PEI then tracks the last-used register and value, and if it is still available and matches the value for the next index, reuses the existing value rather and removes the re-materialization instructions. Fancier tracking and adjustment of scavenger allocations to keep more values live for longer is possible, but not yet implemented and would likely be better done via a different, less special-purpose, approach to the problem. eliminateFrameIndex() is modified so the target implementations can return the registers they wish to be tracked for reuse. ARM Thumb1 implements and utilizes the new mechanism. All other targets are simply modified to adjust for the changed eliminateFrameIndex() prototype. llvm-svn: 83467
* Fix this comment. The loop header is the loop entry point.Dan Gohman2009-10-071-2/+2
| | | | llvm-svn: 83437
* Add support to handle debug info attached to an instruction.Devang Patel2009-10-064-6/+25
| | | | | | This is not yet enabled. llvm-svn: 83400
* Instead of printing unnecessary basic block labels as labels inDan Gohman2009-10-061-2/+10
| | | | | | | | | | verbose-asm mode, print comments instead. This eliminates a non-comment difference between verbose-asm mode and non-verbose-asm mode. Also, factor out the relevant code out of all the targets and into target-independent code. llvm-svn: 83392
* Introduce and use convenience methods for getting pointer typesDuncan Sands2009-10-065-15/+15
| | | | | | | where the element is of a basic builtin type. For example, to get an i8* use getInt8PtrTy. llvm-svn: 83379
* grammarJim Grosbach2009-10-061-1/+1
| | | | llvm-svn: 83378
* Fix cut-n-pasto.Devang Patel2009-10-061-1/+1
| | | | llvm-svn: 83367
* Update processDebugLoc() so that it can be used to process debug info before ↵Devang Patel2009-10-061-6/+8
| | | | | | and after printing an instruction. llvm-svn: 83363
* Remove dead code.Devang Patel2009-10-062-23/+0
| | | | llvm-svn: 83362
* Add utility routine to set begin and end labels for DbgScopes.Devang Patel2009-10-062-0/+31
| | | | | | This will be used by processDebugLoc(). llvm-svn: 83361
* Remove unintentional function decl.Devang Patel2009-10-061-1/+0
| | | | llvm-svn: 83356
* Add utility routine to collect variable debug info. This is not yet used.Devang Patel2009-10-062-0/+17
| | | | llvm-svn: 83355
* Set default location for the function if it is not already set.Devang Patel2009-10-061-0/+2
| | | | | | This code is not yet enabled. llvm-svn: 83349
* Existence of a compile unit for input source file is a good indicator to ↵Devang Patel2009-10-061-10/+1
| | | | | | check debug info's presence in a module. llvm-svn: 83348
* If subprogram die is not available then construct new one.Devang Patel2009-10-051-0/+4
| | | | | | This can happen if debug info is processed lazily. llvm-svn: 83347
* Adjust context for the global variables that are not at file scope, e.g.Devang Patel2009-10-052-2/+22
| | | | | | | void foo() { static int bar = 42; } Here, foo's DIE is parent of bar's DIE. llvm-svn: 83344
* Set address while constructing DIE.Devang Patel2009-10-051-7/+8
| | | | llvm-svn: 83343
* In Thumb1, the register scavenger is not always able to use an emergencyJim Grosbach2009-10-051-9/+15
| | | | | | | | spill slot. When frame references are via the frame pointer, they will be negative, but Thumb1 load/store instructions only allow positive immediate offsets. Instead, Thumb1 will spill to R12. llvm-svn: 83336
* Gracefully handle various scopes while recording source line info.Devang Patel2009-10-051-4/+21
| | | | llvm-svn: 83317
* strength reduce a ton of type equality tests to check the typeid (ThroughChris Lattner2009-10-053-12/+17
| | | | | | | | the new predicates I added) instead of going through a context and doing a pointer comparison. Besides being cheaper, this allows a smart compiler to turn the if sequence into a switch. llvm-svn: 83297
* stop MachineFunctionPass from claiming that it preserves LoopDependence info,Chris Lattner2009-10-051-2/+0
| | | | | | which causes dependence info to be linked into lli. llvm-svn: 83289
* Whitespace and formatting.Jakob Stoklund Olesen2009-10-041-42/+16
| | | | llvm-svn: 83285
* Oops. Renamed remaining MachineInstrIndex references.Lang Hames2009-10-036-21/+21
| | | | llvm-svn: 83255
* Renamed MachineInstrIndex to LiveIndex.Lang Hames2009-10-0310-264/+264
| | | | llvm-svn: 83254
* Fix a use-after-free in post-ra-scheduling.Benjamin Kramer2009-10-021-1/+3
| | | | | | | MI->addOperand invalidates references to it's operands, avoid touching the operand after a new one was added. llvm-svn: 83249
* All callee-saved registers are live-out of a return block.David Goodwin2009-10-011-18/+21
| | | | llvm-svn: 83223
* Remove neonfp attribute and instead set default based on CPU string. Add ↵David Goodwin2009-10-011-1/+1
| | | | | | -arm-use-neon-fp to override the default. llvm-svn: 83218
* Restore the -post-RA-scheduler flag as an override for the target ↵David Goodwin2009-10-011-5/+17
| | | | | | specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string. llvm-svn: 83215
* Add support to extract lexical scope information from DebugLoc attached with ↵Devang Patel2009-10-012-1/+143
| | | | | | | | an machine instruction. This is not yet enabled. llvm-svn: 83210
* Use MachineFrameInfo.getPristineRegs() to determine which callee-saved ↵David Goodwin2009-10-011-47/+30
| | | | | | registers are available for anti-dependency breaking. Some cleanup. llvm-svn: 83208
* Record first and last instruction of a scope in DbgScope.Devang Patel2009-10-011-2/+8
| | | | llvm-svn: 83207
* Observe hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. Do not changeEvan Cheng2009-10-011-18/+55
| | | | | | operands of instructions with these properties while breaking anti-dep. llvm-svn: 83198
* Add another MDNode into DebugLocTuple. This will be used to keep track of ↵Devang Patel2009-10-011-1/+1
| | | | | | inlined functions. llvm-svn: 83190
* If location info is attached with an instruction then keep track of alloca ↵Devang Patel2009-10-011-3/+9
| | | | | | slots used by a variable. This info will be used by AsmPrinter to emit debug info for variables. llvm-svn: 83189
* Use MachineInstr as an processDebugLoc() argument.Devang Patel2009-09-301-2/+2
| | | | | | This will allow processDebugLoc() to handle scopes for DWARF debug info. llvm-svn: 83183
* Use MDNode * directly as an RecordSourceLine() argument.Devang Patel2009-09-305-12/+11
| | | | llvm-svn: 83182
* Remove dead code.Devang Patel2009-09-301-17/+0
| | | | llvm-svn: 83181
* Add a new virtual EmitStartOfAsmFile method to the AsmPrinter and use thisBob Wilson2009-09-301-2/+4
| | | | | | | | | | | | | | | | to emit target-specific things at the beginning of the asm output. This fixes a problem for PPC, where the text sections are not being kept together as expected. The base class doInitialization code calls DW->BeginModule() which emits a bunch of DWARF section directives. The PPC doInitialization code then emits all the TEXT section directives, with the intention that they will be kept together. But as I understand it, the Darwin assembler treats the default TEXT section as a special case and moves it to the beginning of the file, which means that all those DWARF sections are in the middle of the text. With this change, the EmitStartOfAsmFile hook is called before the DWARF section directives are emitted, so that all the PPC text section directives come out right at the beginning of the file. llvm-svn: 83176
* Fix a comment.Bob Wilson2009-09-301-1/+1
| | | | llvm-svn: 83171
* Silence comparison always false warning in -Asserts mode.Reid Kleckner2009-09-301-4/+4
| | | | llvm-svn: 83164
* Add additional assert() to verify no extraneous use of a scavenged register.Jim Grosbach2009-09-301-2/+9
| | | | llvm-svn: 83163
* Fix integer overflow in instruction scheduling. This can happen if we haveReid Kleckner2009-09-305-20/+33
| | | | | | | | | | basic blocks that are so long that their size overflows a short. Also assert that overflow does not happen in the future, as requested by Evan. This fixes PR4401. llvm-svn: 83159
* Add a target hook to add pre- post-regalloc scheduling passes.Evan Cheng2009-09-301-0/+4
| | | | llvm-svn: 83144
* replace TRI->isVirtualRegister() with TargetRegisterInfo::isVirtualRegister()Jim Grosbach2009-09-302-5/+4
| | | | | | per customary usage llvm-svn: 83137
* fix compiler warningJim Grosbach2009-09-301-1/+1
| | | | llvm-svn: 83132
* Simplify.Devang Patel2009-09-301-6/+0
| | | | llvm-svn: 83123
* Remove -post-RA-schedule flag and add a TargetSubtarget method to enable ↵David Goodwin2009-09-302-9/+7
| | | | | | post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. llvm-svn: 83122
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