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* [MIR] Change the token name for '<' and '>' to be consitent with the LLVM IR ↵Quentin Colombet2016-03-082-4/+4
| | | | | | | | parser. Thanks to Ahmed Bougacha for noticing! llvm-svn: 262899
* [GlobalISel] Introduce initializer method to support start/stop-after features.Quentin Colombet2016-03-084-25/+33
| | | | llvm-svn: 262896
* [MIR] Teach the parser/printer that generic virtual registers do not need a ↵Quentin Colombet2016-03-082-8/+20
| | | | | | register class. llvm-svn: 262893
* Revert "SelectionDAG: Store SDNode operands in an ArrayRecycler"Justin Bogner2016-03-081-118/+143
| | | | | | | | | Looks like the largest SDNode is different between 32 and 64 bit now, so this is breaking 32 bit bots. Reverting while I figure out a fix. This reverts r262886. llvm-svn: 262892
* [MIR] Teach the parser how to parse complex types of generic machine ↵Quentin Colombet2016-03-083-14/+35
| | | | | | | | instructions. By complex types, I mean aggregate or vector types. llvm-svn: 262890
* SelectionDAG: Store SDNode operands in an ArrayRecyclerJustin Bogner2016-03-081-143/+118
| | | | | | | | | | | | | | | | | | | | | | | Currently some SDNode operands are malloc'd, some are stored inline in subclasses of SDNode, and some are thrown into a BumpPtrAllocator. This scheme is complex, inconsistent, and makes refactoring SDNodes fairly difficult. Instead, we can allocate all of the operands using an ArrayRecycler that wraps a BumpPtrAllocator. This keeps the cache locality when iterating operands, improves locality when iterating SDNodes without looking at operands, and vastly simplifies the ownership semantics. It also means we stop overallocating SDNodes by 2-3x and will make it simpler to fix the rampant undefined behaviour we have in how we mutate SDNodes from one kind to another (See llvm.org/pr26808). This is NFC other than the changes in memory behaviour, and I ran some LNT tests to make sure this didn't hurt compile time. Not many tests changed: there were a couple of 1-2% regressions reported, but there were more improvements (of up to 4%) than regressions. llvm-svn: 262886
* [MIR] Teach the printer how to print complex types for generic machine ↵Quentin Colombet2016-03-081-1/+2
| | | | | | | | | | | | | instructions. Before this change, we would get the type definition in the middle of the instruction. E.g., %0(48) = G_ADD %struct_alias = type { i32, i16 } %edi, %edi Now, we have just the expected type name: %0(48) = G_ADD %struct_alias %edi, %edi llvm-svn: 262885
* [MIR] Print the type of generic machine instructions.Quentin Colombet2016-03-081-0/+4
| | | | llvm-svn: 262880
* [MIR] Teach the mir parser about types on generic machine instructions.Quentin Colombet2016-03-081-0/+33
| | | | llvm-svn: 262879
* [MachineInstr] Get rid of some GlobalISel ifdefs.Quentin Colombet2016-03-071-5/+24
| | | | | | | | Now the type API is always available, but when global-isel is not built the implementation does nothing. Note: The implementation free of ifdefs is WIP and tracked here in PR26576. llvm-svn: 262873
* [MIR] Teach the MIPrinter about size for generic virtual registers.Quentin Colombet2016-03-071-4/+12
| | | | llvm-svn: 262867
* [MIR] Teach the parser how to handle the size of generic virtual registers.Quentin Colombet2016-03-071-8/+36
| | | | llvm-svn: 262862
* [MachineRegisterInfo] Add a method to set the size of a virtual register a ↵Quentin Colombet2016-03-071-0/+4
| | | | | | | | posteriori. This is required for mir testing. llvm-svn: 262861
* [MachineRegisterInfo] Get rid of the global-isel ifdefs.Quentin Colombet2016-03-071-6/+3
| | | | | | | One additional pointer is not a big deal size-wise and it makes the code much nicer! llvm-svn: 262856
* DAGCombiner: Check legality before creating extract_vector_eltMatt Arsenault2016-03-071-1/+3
| | | | | | Problem not hit by any in tree target. llvm-svn: 262852
* [CodeGen] Add space-optimized EmitMergeInputChains1_2 to the DAG isel ↵Craig Topper2016-03-071-2/+3
| | | | | | matching tables. Shaves about 5100 bytes from the X86 matcher table. NFC llvm-svn: 262815
* Add DAG mutation interface to the post-RA schedulerKrzysztof Parzyszek2016-03-052-6/+24
| | | | | | Differential Revision: http://reviews.llvm.org/D17868 llvm-svn: 262774
* RegisterCoalescer: Remap subregister lanemasks before exchanging operandsMatthias Braun2016-03-051-1/+6
| | | | | | | | | | Rematerializing and merging into a bigger register class at the same time, requires the subregister range lanemasks getting remapped to the new register class. This fixes http://llvm.org/PR26805 llvm-svn: 262768
* RegisterCoalescer: Need to check DstReg+SrcReg for missing undef flagsMatthias Braun2016-03-051-20/+50
| | | | | | | | copy coalescing with enabled subregister liveness can reveal undef uses, previously this was only checked for the SrcReg in updateRegDefsUses() but we need to check DstReg as well. llvm-svn: 262767
* RegisterPressure: Small cleanupMatthias Braun2016-03-051-11/+6
| | | | llvm-svn: 262766
* [DAGCombine] Fix divrem combine not to assume div/rem type is simple.Michael Kuperstein2016-03-041-1/+4
| | | | | | | | | | | | | The divrem combine assumed the type of the div/rem is simple, which isn't necessarily true. This probably worked fine until r250825, since it only saw legal types, but now breaks when it runs as a pre-type-legalization combine. This fixes PR26835. Differential Revision: http://reviews.llvm.org/D17878 llvm-svn: 262746
* [ARM] Merging 64-bit divmod lib calls into oneRenato Golin2016-03-041-4/+8
| | | | | | | | | | | | | | | | | | | | | When div+rem calls on the same arguments are found, the ARM back-end merges the two calls into one __aeabi_divmod call for up to 32-bits values. However, for 64-bit values, which also have a lib call (__aeabi_ldivmod), it wasn't merging the calls, and thus calling ldivmod twice and spilling the temporary results, which generated pretty bad code. This patch legalises 64-bit lib calls for divmod, so that now all the spilling and the second call are gone. It also relaxes the DivRem combiner a bit on the legal type check, since it was already checking for isLegalOrCustom on every value, so the extra check for isTypeLegal was redundant. Second attempt, creating TLI.isOperationCustom like isOperationExpand, to make sure we only emit valid types or the ones that were explicitly marked as custom. Now, passing check-all and test-suite on x86, ARM and AArch64. This patch fixes PR17193 (and a long time FIXME in the tests). llvm-svn: 262738
* Change split code gen to use ThreadPoolTeresa Johnson2016-03-041-32/+40
| | | | | | Part of D15390. llvm-svn: 262719
* Make headers self-contained again.Benjamin Kramer2016-03-041-0/+1
| | | | llvm-svn: 262702
* [X86][SSE] Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREGSimon Pilgrim2016-03-031-1/+18
| | | | | | | | Generalise the existing SIGN_EXTEND to SIGN_EXTEND_VECTOR_INREG combine to support zero extension as well and get rid of a lot of unnecessary ANY_EXTEND + mask patterns. Differential Revision: http://reviews.llvm.org/D17691 llvm-svn: 262599
* Revert "[ARM] Merging 64-bit divmod lib calls into one"Renato Golin2016-03-031-2/+1
| | | | | | This reverts commit r262507, which broke some ARM buildbots. llvm-svn: 262594
* [BranchFolding] Change function name related with merging MMOs. NFCJunmo Park2016-03-031-7/+5
| | | | | | | | | | | Summary: Removing MMOs is not our prefer behavior any more. Reviewers: mcrosier, reames Differential Revision: http://reviews.llvm.org/D17668 llvm-svn: 262580
* [MBP] Renaming a confusing variable and add clarifying commentsPhilip Reames2016-03-031-19/+24
| | | | | | Was discussed as part of http://reviews.llvm.org/D17830 llvm-svn: 262571
* [MBP] Avoid placing random blocks between loop preheader and headerPhilip Reames2016-03-031-1/+2
| | | | | | | | | | If we have a loop with a rarely taken path, we will prune that from the blocks which get added as part of the loop chain. The problem is that we weren't then recognizing the loop chain as schedulable when considering the preheader when forming the function chain. We'd then fall to various non-predecessors before finally scheduling the loop chain (as if the CFG was unnatural.) The net result was that there could be lots of garbage between a loop preheader and the loop, even though we could have directly fallen into the loop. It also meant we separated hot code with regions of colder code. The particular reason for the rejection of the loop chain was that we were scanning predecessor of the header, seeing the backedge, believing that was a globally more important predecessor (true), but forgetting to account for the fact the backedge precessor was already part of the existing loop chain (oops!. Differential Revision: http://reviews.llvm.org/D17830 llvm-svn: 262547
* [X86] Don't give catch objects a displacement of zeroDavid Majnemer2016-03-032-24/+47
| | | | | | | | | | | | | | | | | | Catch objects with a displacement of zero do not initialize a catch object. The displacement is relative to %rsp at the end of the function's prologue for x86_64 targets. If we place an object at the top-of-stack, we will end up wit a displacement of zero resulting in our catch object remaining uninitialized. Address this by creating our catch objects as fixed objects. We will ensure that the UnwindHelp object is created after the catch objects so that no catch object will have a displacement of zero. Differential Revision: http://reviews.llvm.org/D17823 llvm-svn: 262546
* [MBP] Remove overly verbose debug outputPhilip Reames2016-03-021-5/+2
| | | | llvm-svn: 262531
* [MBP] Adjust debug output to be more focused and approachablePhilip Reames2016-03-021-18/+9
| | | | llvm-svn: 262522
* [ARM] Merging 64-bit divmod lib calls into oneRenato Golin2016-03-021-1/+2
| | | | | | | | | | | | | | | | | When div+rem calls on the same arguments are found, the ARM back-end merges the two calls into one __aeabi_divmod call for up to 32-bits values. However, for 64-bit values, which also have a lib call (__aeabi_ldivmod), it wasn't merging the calls, and thus calling ldivmod twice and spilling the temporary results, which generated pretty bad code. This patch legalises 64-bit lib calls for divmod, so that now all the spilling and the second call are gone. It also relaxes the DivRem combiner a bit on the legal type check, since it was already checking for isLegalOrCustom on every value, so the extra check for isTypeLegal was redundant. This patch fixes PR17193 (and a long time FIXME in the tests). llvm-svn: 262507
* SelectionDAG: Use correctly sized allocation functions for SDNodesJustin Bogner2016-03-021-116/+86
| | | | | | | | | | | | | | | | The placement new calls here were all calling the allocation function in RecyclingAllocator/Recycler for SDNode, instead of the function for the specific subclass we were constructing. Since this particular allocator always overallocates it more or less worked, but would hide what we're actually doing from any memory tools. Also, if you tried to change this allocator so something like a BumpPtrAllocator or MallocAllocator, the compiler would crash horribly all the time. Part of llvm.org/PR26808. llvm-svn: 262500
* DAGCombiner: Make sure an integer is being truncatedMatt Arsenault2016-03-021-1/+1
| | | | llvm-svn: 262446
* DAGCombiner: Turn truncate of a bitcasted vector to an extractMatt Arsenault2016-03-011-0/+16
| | | | | | | | | | | On AMDGPU where operations i64 operations are often bitcasted to v2i32 and back, this pattern shows up regularly where it breaks some expected combines on i64, such as load width reducing. This fixes some test failures in a future commit when i64 loads are changed to promote. llvm-svn: 262397
* Revert "[mips] Promote the result of SETCC nodes to GPR width."Vasileios Kalintiris2016-03-014-16/+6
| | | | | | | | | This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
* [NVPTX] Use different, convergent MIs for convergent calls.Justin Lebar2016-03-011-3/+5
| | | | | | | | | | | | | | | | | | | | | | | Summary: Calls sometimes need to be convergent. This is already handled at the LLVM IR level, but it also needs to be handled at the MI level. Ideally we'd propagate convergence from instructions, down through the selection DAG, and into MIs. But this is Hard, and would affect optimizations in the SDNs -- right now only SDNs with two operands have any flags at all. Instead, here's a much simpler hack: Add new opcodes for NVPTX for convergent calls, and generate these when lowering convergent LLVM calls. Reviewers: jholewinski Subscribers: jholewinski, chandlerc, joker.eph, jhen, tra, llvm-commits Differential Revision: http://reviews.llvm.org/D17423 llvm-svn: 262373
* DAGCombiner: Turn extract of bitcasted integer into truncateMatt Arsenault2016-03-011-0/+8
| | | | | | | This reduces the number of bitcast nodes and generally cleans up the DAG when bitcasting between integers and vectors everywhere. llvm-svn: 262358
* Refactor duplicated code for linking with pthread.Rafael Espindola2016-03-011-6/+1
| | | | llvm-svn: 262344
* [mips] Promote the result of SETCC nodes to GPR width.Vasileios Kalintiris2016-03-014-6/+16
| | | | | | | | | | | | | | | | | | | | Summary: This patch modifies the existing comparison, branch, conditional-move and select patterns, and adds new ones where needed. Also, the updated SLT{u,i,iu} set of instructions generate a GPR width result. The majority of the code changes in the Mips back-end fix the wrong assumption that the result of SETCC nodes always produce an i32 value. The changes in the common code path account for the fact that in 64-bit MIPS targets, i1 is promoted to i32 instead of i64. Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D10970 llvm-svn: 262316
* LegalizeDAG: Use correct ptr type when expanding unaligned load/storeMatt Arsenault2016-03-011-14/+21
| | | | | | | This fixes regressions exposed in existing AMDGPU tests in a future commit when all loads are custom lowered. llvm-svn: 262299
* [WinEH] Allocate the registration node before the catch objectsDavid Majnemer2016-03-012-0/+13
| | | | | | | | | | | | | | | | | | | | The CatchObjOffset is relative to the end of the EH registration node for 32-bit x86 WinEH targets. A special sentinel value, 0, is used to indicate that no catch object should be initialized. This means that a catch object allocated immediately before the registration node would be assigned a CatchObjOffset of 0, leading the runtime to believe that a catch object should not be initialized. To handle this, allocate the registration node prior to any other frame object. This will ensure that catch objects will not be allocated before the registration node. This fixes PR26757. Differential Revision: http://reviews.llvm.org/D17689 llvm-svn: 262294
* Improve the debug output of DwarfDebug::buildLocationList().Adrian Prantl2016-02-292-1/+15
| | | | llvm-svn: 262265
* Fix PR26585 by improving the promotion of DBG_VALUEs to DW_AT_locations.Adrian Prantl2016-02-291-2/+17
| | | | | | | | | | | | | | | When a variable is described by a single DBG_VALUE instruction we can often use a more efficient inline DW_AT_location instead of using a location list. This commit makes the heuristic that decides when to apply this optimization stricter by also verifying that the DBG_VALUE is live at the entry of the function (instead of just checking that it is valid until the end of the function). <rdar://problem/24611008> llvm-svn: 262247
* fix typo in commentAdrian Prantl2016-02-291-1/+1
| | | | llvm-svn: 262236
* CodeGen: Remove an iterator => pointer conversion, NFCDuncan P. N. Exon Smith2016-02-271-2/+2
| | | | | | Part of PR26753. llvm-svn: 262154
* CodeGen: Use MachineInstr& in InlineSpiller::rematerializeFor()Duncan P. N. Exon Smith2016-02-271-16/+15
| | | | | | | | InlineSpiller::rematerializeFor() never uses its parameter as an iterator, so take it by reference instead. This removes an implicit conversion from MachineBasicBlock::iterator to MachineInstr*. llvm-svn: 262152
* CodeGen: Update LiveIntervalAnalysis API to use MachineInstr&, NFCDuncan P. N. Exon Smith2016-02-275-40/+41
| | | | | | These parameters aren't expected to be null, so take them by reference. llvm-svn: 262151
* CodeGen: Change MachineInstr to use MachineInstr&, NFCDuncan P. N. Exon Smith2016-02-275-20/+20
| | | | | | | | Change MachineInstr API to prefer MachineInstr& over MachineInstr* whenever the parameter is expected to be non-null. Slowly inching toward being able to fix PR26753. llvm-svn: 262149
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