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* Disable Visual C++ 2013 Debug mode assert on null pointer in some STL ↵Yaron Keren2015-08-211-1/+1
| | | | | | | | | | | | | | | algorithms, such as std::equal on the third argument. This reverts previous workarounds. Predefining _DEBUG_POINTER_IMPL disables Visual C++ 2013 headers from defining it to a function performing the null pointer check. In practice, it's not that bad since any function actually using the nullptr will seg fault. The other iterator sanity checks remain enabled in the headers. Reviewed by Aaron Ballmanþ and Duncan P. N. Exon Smith. llvm-svn: 245711
* [DAGCombiner] Fold together mul and shl when both are by a constantJohn Brawn2015-08-211-0/+8
| | | | | | | | | | This is intended to improve code generation for GEPs, as the index value is shifted by the element size and in GEPs of multi-dimensional arrays the index of higher dimensions is multiplied by the lower dimension size. Differential Revision: http://reviews.llvm.org/D12197 llvm-svn: 245689
* Make helper functions static. NFC.Benjamin Kramer2015-08-201-1/+1
| | | | llvm-svn: 245549
* MIR Serialization: Use the global value syntax for global value memory operands.Alex Lorenz2015-08-202-5/+15
| | | | | | | | | | | This commit modifies the serialization syntax so that the global IR values in machine memory operands use the global value '@<name>' syntax instead of the current '%ir.<name>' syntax. The unnamed global IR values are handled by this commit as well, as the existing global value parsing method can parse the unnamed globals already. llvm-svn: 245527
* MIR Serialization: Change syntax for the call entry pseudo source values.Alex Lorenz2015-08-204-14/+24
| | | | | | | | | | | | The global IR values in machine memory operands should use the global value '@<name>' syntax instead of the current '%ir.<name>' syntax. However, the global value call entry pseudo source values use the global value syntax already. Therefore, the syntax for the call entry pseudo source values has to be changed so that the global values and call entry global value PSVs can be parsed without ambiguities. llvm-svn: 245526
* Fix test failure introduced by r245521.Alex Lorenz2015-08-191-0/+6
| | | | | | | | | Machine memory operands can contain pointer values that are constants, and the 'getLocalSlot' method requires non-constant values. The constant pointer values will have to be serialized in a different patch. llvm-svn: 245523
* MIR Serialization: Serialize unnamed local IR values in memory operands.Alex Lorenz2015-08-194-7/+51
| | | | llvm-svn: 245521
* MIR Parser: parseIRValue should take in a constant pointer. NFC.Alex Lorenz2015-08-191-3/+3
| | | | llvm-svn: 245520
* MIR Printer: Extract the code that prints IR slots to a separate function. NFC.Alex Lorenz2015-08-191-4/+8
| | | | | | This code can be reused when printing references to unnamed local IR values. llvm-svn: 245519
* [DAGCombiner] Added SMAX/SMIN/UMAX/UMIN constant foldingSimon Pilgrim2015-08-192-1/+38
| | | | | | | | | | We still need to add constant folding of vector comparisons to fold the tests for targets that don't support the respective min/max nodes I needed to update 2011-12-06-AVXVectorExtractCombine to load a vector instead of using a constant vector to prevent it folding Differential Revision: http://reviews.llvm.org/D12118 llvm-svn: 245503
* [DAGCombiner] Fold CONCAT_VECTORS of EXTRACT_SUBVECTOR (or undef) to ↵Simon Pilgrim2015-08-191-5/+79
| | | | | | | | | | VECTOR_SHUFFLE. Check to see if this is a CONCAT_VECTORS of a bunch of EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector inputs come from at most two distinct vectors the same size as the result, attempt to turn this into a legal shuffle. Differential Revision: http://reviews.llvm.org/D12125 llvm-svn: 245490
* MIR Parser: Rename 'MachineOperandWithLocation' to 'ParsedMachineOperand'. NFC.Alex Lorenz2015-08-191-14/+13
| | | | | | | Besides storing the operand's source range, this structure now stores other attributes as well, so the name should reflect this fact. llvm-svn: 245483
* MIR Serialization: Serialize instruction's register ties.Alex Lorenz2015-08-194-19/+119
| | | | | | | | This commit serializes the machine instruction's register operand ties. The ties are printed out only when the instructon has register ties that are different from the ties that are specified in the instruction's description. llvm-svn: 245482
* MIR Serialization: Serialize defined registers that require 'def' register flag.Alex Lorenz2015-08-194-6/+17
| | | | | | | | | The defined registers are already serialized - they are represented by placing them before the '=' in a machine instruction. However, certain instructions like INLINEASM can have defined register operands after the '=', so this commit introduces the 'def' register flag for such operands. llvm-svn: 245480
* [PeepholeOptimizer] Look through PHIs to find additional register sourcesBruno Cardoso Lopes2015-08-191-85/+285
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reintroduce r245442. Remove an overly conservative assertion introduced in r245442. We could replace the assertion to use `shareSameRegisterFile` instead, but in that point in `insertPHI` we already lost the original Def subreg to check against. So drop the assertion completely. Original commit message: - Teaches the ValueTracker in the PeepholeOptimizer to look through PHI instructions. - Add findNextSourceAndRewritePHI method to lookup into multiple sources returnted by the ValueTracker and rewrite PHIs with new sources. With these changes we can find more register sources and rewrite more copies to allow coaslescing of bitcast instructions. Hence, we eliminate unnecessary VR64 <-> GR64 copies in x86, but it could be extended to other archs by marking "isBitcast" on target specific instructions. The x86 example follows: A: psllq %mm1, %mm0 movd %mm0, %r9 jmp C B: por %mm1, %mm0 movd %mm0, %r9 jmp C C: movd %r9, %mm0 pshufw $238, %mm0, %mm0 Becomes: A: psllq %mm1, %mm0 jmp C B: por %mm1, %mm0 jmp C C: pshufw $238, %mm0, %mm0 Differential Revision: http://reviews.llvm.org/D11197 rdar://problem/20404526 llvm-svn: 245479
* Revert "[PeepholeOptimizer] Look through PHIs to find additional register ↵Bruno Cardoso Lopes2015-08-191-288/+85
| | | | | | | | | sources" Revert r245442 while investigating a fix. An assertion hit in http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_build/11380 llvm-svn: 245446
* [PeepholeOptimizer] Look through PHIs to find additional register sourcesBruno Cardoso Lopes2015-08-191-85/+288
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reapply r243486. - Teaches the ValueTracker in the PeepholeOptimizer to look through PHI instructions. - Add findNextSourceAndRewritePHI method to lookup into multiple sources returnted by the ValueTracker and rewrite PHIs with new sources. With these changes we can find more register sources and rewrite more copies to allow coaslescing of bitcast instructions. Hence, we eliminate unnecessary VR64 <-> GR64 copies in x86, but it could be extended to other archs by marking "isBitcast" on target specific instructions. The x86 example follows: A: psllq %mm1, %mm0 movd %mm0, %r9 jmp C B: por %mm1, %mm0 movd %mm0, %r9 jmp C C: movd %r9, %mm0 pshufw $238, %mm0, %mm0 Becomes: A: psllq %mm1, %mm0 jmp C B: por %mm1, %mm0 jmp C C: pshufw $238, %mm0, %mm0 Differential Revision: http://reviews.llvm.org/D11197 rdar://problem/20404526 llvm-svn: 245442
* Emit <regmask R1 R2 R3 ...> instead of just <regmask> in IR dumps.Daniel Sanders2015-08-191-2/+25
| | | | | | | | | | Reviewers: qcolombet Subscribers: kparzysz, qcolombet, llvm-commits Differential Revision: http://reviews.llvm.org/D11644 llvm-svn: 245433
* [TLI] Refactor "is integer division cheap" queries.Michael Kuperstein2015-08-192-7/+7
| | | | | | | | | | | | | This removes the isPow2SDivCheap() query, as it is not currently used in any meaningful way. isIntDivCheap() no longer relies on a state variable (as all in-tree target set it to false), but the interface allows querying based on the type optimization level. NFC. Differential Revision: http://reviews.llvm.org/D12082 llvm-svn: 245430
* MIR Serialization: Serialize MMI's variable debug information.Alex Lorenz2015-08-194-2/+111
| | | | llvm-svn: 245396
* Fix backward operands in call to isTruncateFree() and improve comments.Steve King2015-08-181-2/+2
| | | | llvm-svn: 245385
* MIR Parser: Return true on error when parsing standalone registers.Alex Lorenz2015-08-181-2/+2
| | | | llvm-svn: 245384
* MIR Serialization: Serialize the operand's bit mask target flags.Alex Lorenz2015-08-182-9/+84
| | | | | | | | | This commit adds support for bit mask target flag serialization to the MIR printer and the MIR parser. It also adds support for the machine operand's target flag serialization to the AArch64 target. Reviewers: Duncan P. N. Exon Smith llvm-svn: 245383
* Fix three typos in comments; "easilly" -> "easily".Nick Lewycky2015-08-181-1/+1
| | | | llvm-svn: 245379
* MIR Serialization: Serialize the frame information's stack protector index.Alex Lorenz2015-08-184-2/+48
| | | | llvm-svn: 245372
* MIR Parser: Extract the code that parses stack object references into a newAlex Lorenz2015-08-181-2/+11
| | | | | | | | | | method. This commit extracts the code that parses the stack object references into a new method named 'parseStackFrameIndex', so that it can be reused when parsing standalone stack object references. llvm-svn: 245370
* DAGCombiner: Improve DAGCombiner select normalizationMatthias Braun2015-08-181-20/+30
| | | | | | | | | | | | | | | | The current code normalizes select(C0, x, select(C1, x, y)) towards select(C0|C1, x, y) if the targets prefers that form. This patch adds an additional rule that if the select(C1, x, y) part already exists in the function then we want to normalize into the other direction because the effects of reusing the existing value are bigger than transforming into the target preferred form. This addresses regressions following r238793, see also: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20150727/290272.html Differential Revision: http://reviews.llvm.org/D11616 llvm-svn: 245350
* DAGCombiner: Optimize SELECTs first before turning them into SELECT_CCMatthias Braun2015-08-181-32/+32
| | | | | | | This is part of http://reviews.llvm.org/D11616 - I just decided to split this up into a separate commit. llvm-svn: 245349
* [WinEH] Calculate state numbers for the new EH representationDavid Majnemer2015-08-184-14/+158
| | | | | | | | | | | State numbers are calculated by performing a walk from the innermost funclet to the outermost funclet. Rudimentary support for the new EH constructs has been added to the assembly printer, just enough to test the new machinery. Differential Revision: http://reviews.llvm.org/D12098 llvm-svn: 245331
* MachineRegisterInfo: Introduce isPhysRegUsed()Matthias Braun2015-08-182-7/+18
| | | | | | | | | | | | | | | | This method checks whether a physical regiser or any of its aliases are used in the function. Using this function in SIRegisterInfo::findUnusedReg() should also fix this reported failure: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20150803/292143.html http://reviews.llvm.org/rL242173#inline-533 The report doesn't come with a testcase and I don't know enough about AMDGPU to create one myself. llvm-svn: 245329
* MIR Parser: Implicit register verifier should accept unexpected implicitAlex Lorenz2015-08-181-0/+13
| | | | | | subregister operands. llvm-svn: 245315
* use minSize wrapper; NFCISanjay Patel2015-08-181-2/+1
| | | | | | | These were missed when other uses were switched over: http://llvm.org/viewvc/llvm-project?view=revision&revision=243994 llvm-svn: 245311
* Align SP adjustment in function getSPAdjustGuozhi Wei2015-08-171-0/+1
| | | | | | | This commit adds a new function TargetFrameLowering::alignSPAdjust and calls it from TargetInstrInfo::getSPAdjust. It fixes PR24142. llvm-svn: 245253
* MIR Serialization: Serialize the local offsets for the stack objects.Alex Lorenz2015-08-172-0/+11
| | | | llvm-svn: 245249
* MIR Serialization: Serialize the memory operand's range metadata node.Alex Lorenz2015-08-174-5/+16
| | | | llvm-svn: 245247
* MIR Serialization: Serialize the memory operand's noalias metadata node.Alex Lorenz2015-08-174-3/+13
| | | | llvm-svn: 245246
* MIR Serialization: Serialize the memory operand's alias scope metadata node.Alex Lorenz2015-08-174-3/+12
| | | | llvm-svn: 245245
* MIR Serialization: Serialize the memory operand's TBAA metadata node.Alex Lorenz2015-08-174-11/+60
| | | | llvm-svn: 245244
* [WinEHPrepare] Replace unreasonable funclet terminators with unreachableDavid Majnemer2015-08-171-3/+33
| | | | | | | | | | It is possible to be in a situation where more than one funclet token is a valid SSA value. If we see a terminator which exits a funclet which doesn't use the funclet's token, replace it with unreachable. Differential Revision: http://reviews.llvm.org/D12074 llvm-svn: 245238
* [WinEHPrepare] Fix catchret successor phi demotionJoseph Tremoulet2015-08-171-0/+36
| | | | | | | | | | | | | | | | | | | | Summary: When demoting an SSA value that has a use on a phi and one of the phi's predecessors terminates with catchret, the edge needs to be split and the load inserted in the new block, else we'll still have a cross-funclet SSA value. Add a test for this, and for the similar case where a def to be spilled is on and invoke and a critical edge, which was already implemented but missing a test. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12065 llvm-svn: 245218
* Revert "Disable targetdatalayoutcheck"Tobias Grosser2015-08-171-0/+5
| | | | | | | I committed by accident a local hack that should not have made it upstream. Sorry for the noise. llvm-svn: 245212
* Disable targetdatalayoutcheckTobias Grosser2015-08-171-5/+0
| | | | llvm-svn: 245210
* Generate FMINNAN/FMINNUM/FMAXNAN/FMAXNUM from SDAGBuilder.James Molloy2015-08-171-12/+33
| | | | | | | | | | These only get generated if the target supports them. If one of the variants is not legal and the other is, and it is safe to do so, the other variant will be emitted. For example on AArch32 (V8), we have scalar fminnm but not fmin. Fix up a couple of tests while we're here - one now produces better code, and the other was just plain wrong to start with. llvm-svn: 245196
* [PM] Port ScalarEvolution to the new pass manager.Chandler Carruth2015-08-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change makes ScalarEvolution a stand-alone object and just produces one from a pass as needed. Making this work well requires making the object movable, using references instead of overwritten pointers in a number of places, and other refactorings. I've also wired it up to the new pass manager and added a RUN line to a test to exercise it under the new pass manager. This includes basic printing support much like with other analyses. But there is a big and somewhat scary change here. Prior to this patch ScalarEvolution was never *actually* invalidated!!! Re-running the pass just re-wired up the various other analyses and didn't remove any of the existing entries in the SCEV caches or clear out anything at all. This might seem OK as everything in SCEV that can uses ValueHandles to track updates to the values that serve as SCEV keys. However, this still means that as we ran SCEV over each function in the module, we kept accumulating more and more SCEVs into the cache. At the end, we would have a SCEV cache with every value that we ever needed a SCEV for in the entire module!!! Yowzers. The releaseMemory routine would dump all of this, but that isn't realy called during normal runs of the pipeline as far as I can see. To make matters worse, there *is* actually a key that we don't update with value handles -- there is a map keyed off of Loop*s. Because LoopInfo *does* release its memory from run to run, it is entirely possible to run SCEV over one function, then over another function, and then lookup a Loop* from the second function but find an entry inserted for the first function! Ouch. To make matters still worse, there are plenty of updates that *don't* trip a value handle. It seems incredibly unlikely that today GVN or another pass that invalidates SCEV can update values in *just* such a way that a subsequent run of SCEV will incorrectly find lookups in a cache, but it is theoretically possible and would be a nightmare to debug. With this refactoring, I've fixed all this by actually destroying and recreating the ScalarEvolution object from run to run. Technically, this could increase the amount of malloc traffic we see, but then again it is also technically correct. ;] I don't actually think we're suffering from tons of malloc traffic from SCEV because if we were, the fact that we never clear the memory would seem more likely to have come up as an actual problem before now. So, I've made the simple fix here. If in fact there are serious issues with too much allocation and deallocation, I can work on a clever fix that preserves the allocations (while clearing the data) between each run, but I'd prefer to do that kind of optimization with a test case / benchmark that shows why we need such cleverness (and that can test that we actually make it faster). It's possible that this will make some things faster by making the SCEV caches have higher locality (due to being significantly smaller) so until there is a clear benchmark, I think the simple change is best. Differential Revision: http://reviews.llvm.org/D12063 llvm-svn: 245193
* use SDValue bool operator; NFCISanjay Patel2015-08-161-4/+3
| | | | llvm-svn: 245181
* [DAGCombiner] Attempt to mask vectors before zero extension instead of after.Simon Pilgrim2015-08-151-14/+28
| | | | | | | | | | | | | | For cases where we TRUNCATE and then ZERO_EXTEND to a larger size (often from vector legalization), see if we can mask the source data and then ZERO_EXTEND (instead of after a ANY_EXTEND). This can help avoid having to generate a larger mask, and possibly applying it to several sub-vectors. (zext (truncate x)) -> (zext (and(x, m)) Includes a minor patch to SystemZ to better recognise 8/16-bit zero extension patterns from RISBG bit-extraction code. This is the first of a number of minor patches to help improve the conversion of byte masks to clear mask shuffles. Differential Revision: http://reviews.llvm.org/D11764 llvm-svn: 245160
* Remove redundant TargetFrameLowering::getFrameIndexOffset virtualJames Y Knight2015-08-152-12/+11
| | | | | | | | | | | function. This was the same as getFrameIndexReference, but without the FrameReg output. Differential Revision: http://reviews.llvm.org/D12042 llvm-svn: 245148
* MIR Serialization: Serialize the '.cfi_same_value' CFI directive.Alex Lorenz2015-08-144-0/+15
| | | | llvm-svn: 245103
* MIR Serialization: Serialize the external symbol call entry pseudo sourceAlex Lorenz2015-08-142-5/+10
| | | | | | values. llvm-svn: 245098
* MIR Serialization: Serialize the global value call entry pseudo source values.Alex Lorenz2015-08-142-1/+14
| | | | llvm-svn: 245097
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