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* Add a line number for the scope of the function (starting at the firstEric Christopher2012-04-031-3/+10
| | | | | | | | | | brace) so that we get more accurate line number information about the declaration of a given function and the line where the function first starts. Part of rdar://11026482 llvm-svn: 153916
* Fixes to r153903. Added missing explanation of behaviour when the ↵Pete Cooper2012-04-031-5/+5
| | | | | | VirtRegMap is NULL. Also changed it in this case to just avoid updating the map, but live ranges or intervals will still get updated and created llvm-svn: 153914
* Moved LiveRangeEdit.h so that it can be called from other parts of the ↵Pete Cooper2012-04-029-210/+8
| | | | | | backend, not just libCodeGen llvm-svn: 153906
* Allocate virtual registers in ascending order.Jakob Stoklund Olesen2012-04-021-2/+2
| | | | | | | | | This is just the fallback tie-breaker ordering, the main allocation order is still descending size. Patch by Shamil Kurmangaleev! llvm-svn: 153904
* Refactored the LiveRangeEdit interface so that MachineFunction, ↵Pete Cooper2012-04-028-93/+76
| | | | | | TargetInstrInfo, MachineRegisterInfo, LiveIntervals, and VirtRegMap are all passed into the constructor and stored as members instead of passed in to each method. llvm-svn: 153903
* Add predicates for checking whether targets have free FNEG and FABS ↵Owen Anderson2012-04-021-3/+5
| | | | | | operations, and prevent the DAGCombiner from turning them into bitwise operations if they do. llvm-svn: 153901
* During two-address lowering, rescheduling an instruction does not untieLang Hames2012-04-021-2/+2
| | | | | | | operands. Make TryInstructionTransform return false to reflect this. Fixes PR11861. llvm-svn: 153892
* Turn on the accelerator tables for Darwin.Eric Christopher2012-04-021-0/+6
| | | | llvm-svn: 153880
* Optimizing swizzles of complex shuffles may generate additional complex ↵Nadav Rotem2012-04-021-1/+9
| | | | | | | | | shuffles. Do not try to optimize swizzles of shuffles if the source shuffle has more than a single user, except when the source shuffle is also a swizzle. llvm-svn: 153864
* Make MCInstrInfo available to the MCInstPrinter. This will be used to remove ↵Craig Topper2012-04-021-0/+1
| | | | | | getInstructionName and the static data it contains since the same tables are already in MCInstrInfo. llvm-svn: 153860
* This commit contains a few changes that had to go in together.Nadav Rotem2012-04-011-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) (and also scalar_to_vector). 2. Xor/and/or are indifferent to the swizzle operation (shuffle of one src). Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A, B)) 3. Optimize swizzles of shuffles: shuff(shuff(x, y), undef) -> shuff(x, y). 4. Fix an X86ISelLowering optimization which was very bitcast-sensitive. Code which was previously compiled to this: movd (%rsi), %xmm0 movdqa .LCPI0_0(%rip), %xmm2 pshufb %xmm2, %xmm0 movd (%rdi), %xmm1 pshufb %xmm2, %xmm1 pxor %xmm0, %xmm1 pshufb .LCPI0_1(%rip), %xmm1 movd %xmm1, (%rdi) ret Now compiles to this: movl (%rsi), %eax xorl %eax, (%rdi) ret llvm-svn: 153848
* Fix typo.Lang Hames2012-04-011-1/+1
| | | | llvm-svn: 153846
* misched: Add finalizeScheduler to complete the target interface.Andrew Trick2012-04-011-0/+1
| | | | llvm-svn: 153827
* Teach CodeGen's version of computeMaskedBits to understand the range metadata.Rafael Espindola2012-03-314-11/+19
| | | | | | | | This is the CodeGen equivalent of r153747. I tested that there is not noticeable performance difference with any combination of -O0/-O2 /-g when compiling gcc as a single compilation unit. llvm-svn: 153817
* If we have a VLA that has a "use" in a metadata node that's then usedBill Wendling2012-03-301-1/+12
| | | | | | | | | | | | | | | | here but it has no other uses, then we have a problem. E.g., int foo (const int *x) { char a[*x]; return 0; } If we assign 'a' a vreg and fast isel later on has to use the selection DAG isel, it will want to copy the value to the vreg. However, there are no uses, which goes counter to what selection DAG isel expects. <rdar://problem/11134152> llvm-svn: 153705
* Add support for objc property decls according to the page at:Eric Christopher2012-03-292-0/+21
| | | | | | | | | | http://llvm.org/docs/SourceLevelDebugging.html#objcproperty including type and DECL. Expand the metadata needed accordingly. rdar://11144023 llvm-svn: 153639
* Enable machine code verification in the entire code generator.Jakob Stoklund Olesen2012-03-281-8/+3
| | | | | | | | | | Some targets still mess up the liveness information, but that isn't verified after MRI->invalidateLiveness(). The verifier can still check other useful things like register classes and CFG, so it should be enabled after all passes. llvm-svn: 153615
* Enable machine code verification after PreSched2 passes.Jakob Stoklund Olesen2012-03-282-2/+4
| | | | | | | | | | The late scheduler depends on accurate liveness information if it is breaking anti-dependencies, so we should be able to verify it. Relax the terminator checking in the machine code verifier so it can handle the basic blocks created by if conversion. llvm-svn: 153614
* Also verify after ExpandPostRAPseudos.Jakob Stoklund Olesen2012-03-281-1/+1
| | | | llvm-svn: 153599
* Enable machine code verification after the late machine optimization passes.Jakob Stoklund Olesen2012-03-281-3/+3
| | | | | | | Branch folding invalidates liveness and disables liveness verification on some targets. llvm-svn: 153597
* Skip liveness verification when MRI->tracksLiveness() is false.Jakob Stoklund Olesen2012-03-281-105/+112
| | | | | | | | | Extract the liveness verification into its own method. This makes it possible to run the machine code verifier after liveness information is no longer required to be valid. llvm-svn: 153596
* Allow removeLiveIn to be called with a register that isn't live-in.Jakob Stoklund Olesen2012-03-281-2/+2
| | | | | | | | | This avoids the silly double search: if (isLiveIn(Reg)) removeLiveIn(Reg); llvm-svn: 153592
* Fixed commuteInstructions bug where if its called pre-regalloc the subreg ↵Pete Cooper2012-03-281-6/+15
| | | | | | indices weren't commuted llvm-svn: 153579
* More debug output.Eric Christopher2012-03-281-1/+2
| | | | llvm-svn: 153571
* Fix the output of the DW_TAG_friend tag to include DW_AT_friendEric Christopher2012-03-282-8/+16
| | | | | | | | and not the rest of the member tag. Fixes PR11695 llvm-svn: 153570
* Use a SmallVector and linear lookup instead of a DenseSet - SourceMap valuesLang Hames2012-03-271-11/+16
| | | | | | | will always be tiny sets, so DenseSet is overkill (SmallSet won't work as we need iteration support). llvm-svn: 153529
* Use DW_AT_low_pc for a single entry point into a routine.Eric Christopher2012-03-271-3/+3
| | | | | | Fixes PR10105 llvm-svn: 153524
* Print SSA and liveness tracking flags in MF::print().Jakob Stoklund Olesen2012-03-271-1/+7
| | | | llvm-svn: 153518
* Branch folding may invalidate liveness.Jakob Stoklund Olesen2012-03-271-2/+9
| | | | | | | | Branch folding can use a register scavenger to update liveness information when required. Don't do that if liveness information is already invalid. llvm-svn: 153517
* fix what looks like a real logic bug, found by PVS-Studio (part of PR12357)Chris Lattner2012-03-271-2/+2
| | | | llvm-svn: 153513
* Add an MRI::tracksLiveness() flag.Jakob Stoklund Olesen2012-03-272-1/+6
| | | | | | | | | | | | | | | | | | | | Late optimization passes like branch folding and tail duplication can transform the machine code in a way that makes it expensive to keep the register liveness information up to date. There is a fuzzy line between register allocation and late scheduling where the liveness information degrades. The MRI::tracksLiveness() flag makes the line clear: While true, liveness information is accurate, and can be used for register scavenging. Once the flag is false, liveness information is not accurate, and can only be used as a hint. Late passes generally don't need the liveness information, but they will sometimes use the register scavenger to help update it. The scavenger enforces strict correctness, and we have to spend a lot of code to update register liveness that may never be used. llvm-svn: 153511
* Post-ra LICM should take care not to hoist an instruction that would clobber aEvan Cheng2012-03-271-4/+28
| | | | | | | | register that's read by the preheader terminator. rdar://11095580 llvm-svn: 153492
* During MachineCopyPropagation a register may be the source operand of multipleLang Hames2012-03-271-17/+26
| | | | | | | | | | copies being considered for removal. Make sure to track all of the copies, rather than just the most recent encountered, by holding a DenseSet instead of an unsigned in SrcMap. No test case - couldn't reduce something with a sane size. llvm-svn: 153487
* Add a debug option to dump PBQP graphs during register allocation.Lang Hames2012-03-261-0/+29
| | | | llvm-svn: 153483
* Use the file in the inlined die rather than the compile unit forEric Christopher2012-03-261-1/+2
| | | | | | | | | | | | | | backtrace locations. Testcase forthcoming, but I wanted to get some testing here. Should fix: PR12323 PR12314 rdar://11091100 llvm-svn: 153471
* No need to do an expensive stable sort for a bunch of integers.Benjamin Kramer2012-03-261-3/+3
| | | | llvm-svn: 153438
* Prune some includes and forward declarations.Craig Topper2012-03-261-3/+4
| | | | llvm-svn: 153429
* Add a debug statement.Eric Christopher2012-03-261-1/+3
| | | | llvm-svn: 153428
* Add the ability to promote legal integer VAARGs. This is required for the ↵Hal Finkel2012-03-241-1/+33
| | | | | | PPC64 SVR4 ABI. llvm-svn: 153372
* Pretty-printing comments for literal floating point in .s files.Jim Grosbach2012-03-231-2/+6
| | | | | | | Dump the hex representation to the comment stream as well as the float value. llvm-svn: 153346
* Add support for register masks to PBQP.Lang Hames2012-03-231-4/+38
| | | | llvm-svn: 153341
* Source order scheduler should not preschedule nodes with multiple uses. ↵Evan Cheng2012-03-221-7/+11
| | | | | | rdar://11096639 llvm-svn: 153270
* Assign node orders to target intrinsics which do not produce results. ↵Evan Cheng2012-03-221-0/+6
| | | | | | rdar://11096639 llvm-svn: 153269
* In erroneous inline assembly we could mistakenly try to access theEric Christopher2012-03-221-1/+5
| | | | | | | | | metadata operand as an actual operand, leading to an assert. Error out in this case. rdar://11007633 llvm-svn: 153234
* [fast-isel] Fold "urem x, pow2" -> "and x, pow2-1". This should fix the 271%Chad Rosier2012-03-221-0/+7
| | | | | | | | | execution-time regression for nsieve-bits on the ARMv7 -O0 -g nightly tester. This may also improve compile-time on architectures that would otherwise generate a libcall for urem (e.g., ARM) or fall back to the DAG selector. rdar://10810716 llvm-svn: 153230
* Checking a build_vector for an all-ones value.Jim Grosbach2012-03-211-5/+14
| | | | | | | | Type legalization can zero-extend the elements of the build_vector node, so, for example, we may have an <8 x i8> with i32 elements of value 255. That should return 'true' for the vector being all ones. llvm-svn: 153203
* misched: fix LiveInterval update for bottom-up schedulingAndrew Trick2012-03-211-3/+13
| | | | llvm-svn: 153162
* misched: trace LiveIntervals after scheduling.Andrew Trick2012-03-211-0/+1
| | | | llvm-svn: 153161
* misched: obvious iterator update fixes for bottom-up.Andrew Trick2012-03-211-0/+6
| | | | llvm-svn: 153160
* misched: cleanup main loopAndrew Trick2012-03-211-10/+14
| | | | llvm-svn: 153159
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