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* misched: handle scheduler that insert instructions at empty region boundaries.Andrew Trick2012-03-091-3/+12
| | | | | | And add comments, since this is obviously confusing. llvm-svn: 152445
* misched: handle scheduling region boundaries nicely.Andrew Trick2012-03-091-4/+11
| | | | llvm-svn: 152393
* misched interface: rename Begin/End to RegionBegin/RegionEnd since they are ↵Andrew Trick2012-03-093-15/+15
| | | | | | not private. llvm-svn: 152382
* misched commentsAndrew Trick2012-03-091-2/+3
| | | | llvm-svn: 152374
* revert 152356: verify misched changes using -misched=shuffle.Andrew Trick2012-03-091-3/+3
| | | | llvm-svn: 152373
* misched: allow the default scheduler to be one chosen by the target.Andrew Trick2012-03-091-16/+33
| | | | llvm-svn: 152360
* Cache MBB->begin. It's possible the scheduler / bundler may change MBB->begin().Evan Cheng2012-03-091-3/+3
| | | | llvm-svn: 152356
* Use uint16_t to store instruction implicit uses and defs. Reduces static data.Craig Topper2012-03-084-11/+11
| | | | llvm-svn: 152301
* Taken into account Duncan's comments for r149481 dated by 2nd Feb 2012:Stepan Dyatkovskiy2012-03-081-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20120130/136146.html Implemented CaseIterator and it solves almost all described issues: we don't need to mix operand/case/successor indexing anymore. Base iterator class is implemented as a template since it may be initialized either from "const SwitchInst*" or from "SwitchInst*". ConstCaseIt is just a read-only iterator. CaseIt is read-write iterator; it allows to change case successor and case value. Usage of iterator allows totally remove resolveXXXX methods. All indexing convertions done automatically inside the iterator's getters. Main way of iterator usage looks like this: SwitchInst *SI = ... // intialize it somehow for (SwitchInst::CaseIt i = SI->caseBegin(), e = SI->caseEnd(); i != e; ++i) { BasicBlock *BB = i.getCaseSuccessor(); ConstantInt *V = i.getCaseValue(); // Do something. } If you want to convert case number to TerminatorInst successor index, just use getSuccessorIndex iterator's method. If you want initialize iterator from TerminatorInst successor index, use CaseIt::fromSuccessorIndex(...) method. There are also related changes in llvm-clients: klee and clang. llvm-svn: 152297
* misched interface: Expose the MachineScheduler pass.Andrew Trick2012-03-081-144/+102
| | | | | | | | Allow targets to provide their own schedulers (subclass of ScheduleDAGInstrs) to the misched pass. Select schedulers using -misched=... llvm-svn: 152278
* Cleanup VLIWPacketizer to use the updated ScheduleDAGInstrs interface.Andrew Trick2012-03-071-18/+12
| | | | llvm-svn: 152262
* misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick2012-03-075-343/+4
| | | | | | implement their own MachineScheduler. llvm-svn: 152261
* misched prep: Remove LLVM_LIBRARY_VISIBILITY from ScheduleDAGInstrs.Andrew Trick2012-03-071-2/+2
| | | | llvm-svn: 152260
* misched prep: Comment the ScheduleDAGInstrs interface.Andrew Trick2012-03-072-9/+15
| | | | llvm-svn: 152259
* misched prep: Cleanup ScheduleDAGInstrs interface.Andrew Trick2012-03-072-75/+81
| | | | | | | | ScheduleDAGInstrs will be the main interface for MI-level schedulers. Make sure it's readable: one page of protected fields, one page of public methids. llvm-svn: 152258
* misched prep: remove extra "protected"Andrew Trick2012-03-071-2/+0
| | | | llvm-svn: 152257
* misched prep: rename InsertPos to End.Andrew Trick2012-03-074-22/+20
| | | | | | ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted. llvm-svn: 152256
* misched preparation: rename core scheduler methods for consistency.Andrew Trick2012-03-0712-101/+101
| | | | | | | We had half the API with one convention, half with another. Now was a good time to clean it up. llvm-svn: 152255
* Try to clarify this comment some.Chandler Carruth2012-03-071-4/+7
| | | | llvm-svn: 152221
* Remove another outbreak of customized (and completely broken) hashing.Chandler Carruth2012-03-071-20/+24
| | | | | | | | | | | | | | | This one is particularly annoying because the hashing algorithm is highly specialized, with a strange "equivalence" definition that subsets the fields involved. Still, this looks at the exact same set of data as the old code, but without bitwise or-ing over parts of it and other mixing badness. No functionality changed here. I've left a substantial fixme about the fact that there is a cleaner and more principled way to do this, but it requires making the equality definition actual stable for particular types... llvm-svn: 152218
* Where the BranchFolding pass removes a branch then adds another better branch,Bill Wendling2012-03-071-4/+27
| | | | | | | | the DebugLoc information can be maintained throughout by grabbing the DebugLoc before the RemoveBranch and then passing the result to the InsertBranch. Patch by Andrew Stanford-Jason! llvm-svn: 152212
* Fix cmakeAndrew Trick2012-03-071-1/+0
| | | | llvm-svn: 152210
* commentAndrew Trick2012-03-071-0/+2
| | | | llvm-svn: 152209
* misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick2012-03-079-90/+153
| | | | | | | | | | | | | | | | | | | ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation. ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class. ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target. Specific changes: - Removed driver code from ScheduleDAG. clearDAG is the only interface needed. - Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls. - Added ScheduleDAGInstrs::begin()/end() public API. - Moved Sequence into the driver layer, which is specific to the scheduling algorithm. llvm-svn: 152208
* ScheduleDAGInstrs commentsAndrew Trick2012-03-071-0/+2
| | | | llvm-svn: 152207
* misched preparation: modularize schedule emission.Andrew Trick2012-03-076-108/+87
| | | | | | ScheduleDAG has nothing to do with how the instructions are scheduled. llvm-svn: 152206
* misched preparation: modularize schedule printing.Andrew Trick2012-03-075-17/+35
| | | | | | ScheduleDAG will not refer to the scheduled instruction sequence. llvm-svn: 152205
* misched preparation: modularize schedule verification.Andrew Trick2012-03-077-14/+34
| | | | | | ScheduleDAG will not refer to the scheduled instruction sequence. llvm-svn: 152204
* whitespaceAndrew Trick2012-03-071-5/+5
| | | | llvm-svn: 152203
* Added -view-misched=dags options.Andrew Trick2012-03-071-0/+9
| | | | llvm-svn: 152178
* Cleanup in preparation for misched: Move DAG visualization logic.Andrew Trick2012-03-075-9/+23
| | | | | | Soon, ScheduleDAG will not refer to the BB. llvm-svn: 152177
* Added MachineBasicBlock::getFullName() to standardize/factor codegen ↵Andrew Trick2012-03-071-0/+12
| | | | | | diagnostics. llvm-svn: 152176
* whitespaceAndrew Trick2012-03-072-6/+6
| | | | llvm-svn: 152175
* Cleanup: DAG building is specific to either SD or MI scheduling. Not part of ↵Andrew Trick2012-03-072-2/+2
| | | | | | the target interface. llvm-svn: 152174
* misched commentsAndrew Trick2012-03-071-0/+2
| | | | llvm-svn: 152173
* misched: Use the StartBlock/FinishBlock hooksAndrew Trick2012-03-071-0/+2
| | | | llvm-svn: 152172
* Add the DW_AT_APPLE_runtime_class attribute to forward declarationsEric Christopher2012-03-071-5/+6
| | | | | | | | as well as completely defined classes. This fixes rdar://10956070 llvm-svn: 152171
* Extend r148086 to check for [r +/- reg] address mode. This fixes queens ↵Evan Cheng2012-03-061-4/+7
| | | | | | performance regression (due to increased register pressure from overly aggressive pre-inc formation). llvm-svn: 152162
* Hoist common code out of if statement.Jakob Stoklund Olesen2012-03-061-13/+8
| | | | llvm-svn: 152153
* Avoid finalizeBundles infinite looping.Evan Cheng2012-03-061-0/+2
| | | | llvm-svn: 152089
* Make it possible for a target to mark FSUB as Expand. This requires ↵Owen Anderson2012-03-062-16/+39
| | | | | | providing a default expansion (FADD+FNEG), and teaching DAGCombine not to form FSUBs post-legalize if they are not legal. llvm-svn: 152079
* Make MCRegisterInfo available to the the MCInstPrinter.Jim Grosbach2012-03-051-1/+2
| | | | | | | Used to allow context sensitive printing of super-register or sub-register references. llvm-svn: 152043
* Fix warnings about adding a bool to a string.Bill Wendling2012-03-051-2/+2
| | | | | | Patch by Sean Silva! llvm-svn: 152042
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-0514-52/+52
| | | | | | static data size. llvm-svn: 152016
* Stop fixing bad machine code in LiveIntervalAnalysis.Jakob Stoklund Olesen2012-03-041-15/+3
| | | | | | | | The first def of a virtual register cannot also read the register. Assert on such bad machine code instead of trying to fix it. TwoAddressInstructionPass should never create code like that. llvm-svn: 152010
* Stop adding <imp-def> operands when coalescing sub-registers.Jakob Stoklund Olesen2012-03-041-16/+0
| | | | | | | We are already setting <undef> flags, and that is good enough. The <imp-def> operands don't mean anything any more. llvm-svn: 152009
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-0424-57/+57
| | | | llvm-svn: 152001
* Use uint16_t instead of unsigned to store registers in reg classes. Reduces ↵Craig Topper2012-03-043-3/+3
| | | | | | static data size. llvm-svn: 151998
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-047-7/+7
| | | | | | size of static data. llvm-svn: 151996
* Grammar-o in function name.Eric Christopher2012-03-021-2/+2
| | | | llvm-svn: 151875
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