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* Add text explaining an assertion.Cameron Zwarich2010-12-291-1/+3
| | | | llvm-svn: 122617
* Simplify some code in MachineVerifier that was doing the correct thing, but notCameron Zwarich2010-12-281-10/+11
| | | | | | in the most obvious way. llvm-svn: 122610
* Revert the optimization in r122596. It is correct for all current targets, butCameron Zwarich2010-12-281-1/+8
| | | | | | it relies on assumptions that may not be true in the future. llvm-svn: 122608
* Avoid iterating every operand of an instruction in StrongPHIElimination, sinceCameron Zwarich2010-12-281-4/+3
| | | | | | | | we are only interested in the defs when discovering interferences. This is a 28% speedup running StrongPHIElimination on 403.gcc. llvm-svn: 122596
* Pacify the compiler. BestWeight cannot in fact be used uninitializedDuncan Sands2010-12-281-1/+1
| | | | | | | in this function, but the compiler was warning that it might be when doing a release build. llvm-svn: 122595
* Change an assertion to assert what the code actually relies upon.Cameron Zwarich2010-12-271-1/+1
| | | | llvm-svn: 122586
* Land a first cut at StrongPHIElimination. There are only 5 new test failuresCameron Zwarich2010-12-271-64/+590
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when running without the verifier, and I have not yet checked them to see if the new results are still correct. There are more verifier failures, but they all seem to be additional occurrences of verifier failures that occur with the existing PHIElimination pass. There are a few obvious issues with the code: 1) It doesn't properly update the register equivalence classes during copy insertion, and instead recomputes them before merging live intervals and renaming registers. I wanted to keep this first patch simple for debugging purposes, but it shouldn't be very hard to do this. 2) It doesn't mix the renaming and live interval merging with the copy insertion process, which leads to a lot of virtual register churn. Virtual registers and live intervals are created, only to later be merged into others. The code should be smarter and only create a new virtual register if there is no existing register in the same congruence class. 3) In one place the code uses a DenseMap per basic block, which is unnecessary heap allocation. There should be an inline storage version of DenseMap. I did a quick compile-time test of running llc on 403.gcc with and without StrongPHIElimination. It is slightly slower with StrongPHIElimination, because the small decrease in the coalescer runtime can't beat the increase in phi elimination runtime. Perhaps fixing the above performance issues will narrow the gap. I also haven't yet run any tests of the quality of the generated code. llvm-svn: 122582
* Add knowledge of phi-def and phi-kill valnos to MachineVerifier's predecessorCameron Zwarich2010-12-271-1/+17
| | | | | | | | | valno verification. The "Different value live out of predecessor" check is incorrect in the case of phi-def valnos, so just skip that check for phi-def valnos and instead check that all of the valnos for predecessors have phi-kill. Fixes PR8863. llvm-svn: 122581
* Minor cleanup related to my latest scheduler changes.Andrew Trick2010-12-241-3/+5
| | | | llvm-svn: 122545
* Fix a few cases where the scheduler is not checking for phys reg copies. The ↵Andrew Trick2010-12-242-4/+11
| | | | | | scheduling node may have a NULL DAG node, yuck. llvm-svn: 122544
* Various bits of framework needed for precise machine-level selectionAndrew Trick2010-12-248-129/+508
| | | | | | | | | | | | | | | | | | | | | | | | | | DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. llvm-svn: 122541
* whitespaceAndrew Trick2010-12-243-178/+178
| | | | llvm-svn: 122539
* Simplify a check for implicit defs and remove a FIXME.Cameron Zwarich2010-12-241-8/+6
| | | | llvm-svn: 122537
* flags -> glue for selectiondagChris Lattner2010-12-236-78/+77
| | | | llvm-svn: 122509
* sdisel flag -> glue.Chris Lattner2010-12-231-77/+76
| | | | llvm-svn: 122507
* Reorganize ListScheduleBottomUp in preparation for modeling machine cycles ↵Andrew Trick2010-12-231-130/+153
| | | | | | and instruction issue. llvm-svn: 122491
* Converted LiveRegCycles to LiveRegGens. It's easier to work with and allows ↵Andrew Trick2010-12-231-17/+18
| | | | | | multiple nodes per cycle. llvm-svn: 122474
* In CheckForLiveRegDef use TRI->getOverlaps.Andrew Trick2010-12-231-6/+9
| | | | llvm-svn: 122473
* Fixes PR8823: add-with-overflow-128.llAndrew Trick2010-12-231-12/+33
| | | | | | | | In the bottom-up selection DAG scheduling, handle two-address instructions that read/write unspillable registers. Treat the entire chain of two-address nodes as a single live range. llvm-svn: 122472
* Change all self assignments X=X to (void)X, so that we can turn on aJeffrey Yasskin2010-12-234-9/+9
| | | | | | | new gcc warning that complains on self-assignments and self-initializations. llvm-svn: 122458
* DAGCombine add (sext i1), X into sub X, (zext i1) if sext from i1 is ↵Benjamin Kramer2010-12-221-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | illegal. The latter usually compiles into smaller code. example code: unsigned foo(unsigned x, unsigned y) { if (x != 0) y--; return y; } before: _foo: ## @foo cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01] sbbl %eax, %eax ## encoding: [0x19,0xc0] notl %eax ## encoding: [0xf7,0xd0] addl 8(%esp), %eax ## encoding: [0x03,0x44,0x24,0x08] ret ## encoding: [0xc3] after: _foo: ## @foo cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01] movl 8(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08] adcl $-1, %eax ## encoding: [0x83,0xd0,0xff] ret ## encoding: [0xc3] llvm-svn: 122455
* When RegAllocGreedy decides to spill the interferences of the current register,Jakob Stoklund Olesen2010-12-221-37/+89
| | | | | | pick the victim with the lowest total spill weight. llvm-svn: 122445
* Include a shadow of the original CFG edges in the edge bundle graph.Jakob Stoklund Olesen2010-12-221-0/+4
| | | | llvm-svn: 122444
* Fix a bug in ReduceLoadWidth that wasn't handling extendingChris Lattner2010-12-221-1/+4
| | | | | | | | | | | | | | | | | | | | | loads properly. We miscompiled the testcase into: _test: ## @test movl $128, (%rdi) movzbl 1(%rdi), %eax ret Now we get a proper: _test: ## @test movl $128, (%rdi) movsbl (%rdi), %eax movzbl %ah, %eax ret This fixes PR8757. llvm-svn: 122392
* more cleanups, move a check for "roundedness" earlier to rejectChris Lattner2010-12-221-14/+20
| | | | | | unhanded cases faster and simplify code. llvm-svn: 122391
* reduce indentation and improve comments, no functionality change.Chris Lattner2010-12-221-51/+53
| | | | llvm-svn: 122389
* In DelayForLiveRegsBottomUp, handle instructions that read and writeAndrew Trick2010-12-211-15/+4
| | | | | | | the same physical register. Simplifies the fix from the previous checkin r122211. llvm-svn: 122370
* whitespaceAndrew Trick2010-12-211-42/+42
| | | | llvm-svn: 122368
* Reapply 122353-122355 with fixes. 122354 was wrong;Dale Johannesen2010-12-211-4/+31
| | | | | | | | the shift type was needed one place, the shift count type another. The transform in 123555 had the same problem. llvm-svn: 122366
* Revert 122353-122355 for the moment, they broke stuff.Dale Johannesen2010-12-211-29/+3
| | | | llvm-svn: 122360
* Add a new transform to DAGCombiner.Dale Johannesen2010-12-211-0/+26
| | | | llvm-svn: 122355
* Get the type of a shift from the shift, not from its shiftDale Johannesen2010-12-211-1/+1
| | | | | | | | count operand. These should be the same but apparently are not always, and this is cleaner anyway. This improves the code in an existing test. llvm-svn: 122354
* Shift by the word size is invalid IR; don't create it.Dale Johannesen2010-12-211-2/+2
| | | | llvm-svn: 122353
* fix some typosChris Lattner2010-12-211-2/+1
| | | | llvm-svn: 122349
* Fix indentation, add comment.Stuart Hastings2010-12-211-4/+6
| | | | llvm-svn: 122345
* Missing logic for nested CALLSEQ_START/END.Stuart Hastings2010-12-211-2/+5
| | | | llvm-svn: 122342
* Incremental progress towards a new implementation of StrongPHIElimination. MostCameron Zwarich2010-12-211-3/+186
| | | | | | | | | | | | of the problems with my last attempt were in the updating of LiveIntervals rather than the coalescing itself. Therefore, I decided to get that right first by essentially reimplementing the existing PHIElimination using LiveIntervals. It works correctly, with only a few tests failing (which may not be legitimate failures) and no new verifier failures (at least as far as I can tell, I didn't count the number per file). llvm-svn: 122321
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-2112-60/+60
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* improve "cannot yet select" errors a trivial amount: nowChris Lattner2010-12-211-1/+1
| | | | | | they are just as useless, but at least a bit more gramatical llvm-svn: 122305
* Add EdgeBundles to SplitKit.Jakob Stoklund Olesen2010-12-212-1/+85
| | | | | | | | | Edge bundles is an annotation on the CFG that turns it into a bipartite directed graph where each basic block is connected to an outgoing and an ingoing bundle. These bundles are useful for identifying regions of the CFG for live range splitting. llvm-svn: 122301
* Use IntEqClasses to compute connected components of live intervals.Jakob Stoklund Olesen2010-12-211-49/+9
| | | | llvm-svn: 122296
* Cosmetic changes.Dale Johannesen2010-12-201-2/+2
| | | | llvm-svn: 122259
* MachineVerifier should count landing pad successors as basic blocks rather thanCameron Zwarich2010-12-201-7/+9
| | | | | | out-edges. Fixes PR8824. llvm-svn: 122228
* Teach MachineVerifier that early clobber defs begin at USE slots and other defsCameron Zwarich2010-12-201-5/+26
| | | | | | begin at DEF slots. Fixes the second half of PR8813. llvm-svn: 122225
* Add a missing check from r122218.Cameron Zwarich2010-12-201-1/+1
| | | | llvm-svn: 122224
* implement type legalization promotion support for SMULO and UMULO, giving Chris Lattner2010-12-201-5/+48
| | | | | | | | ARM (and other 32-bit-only) targets support for i8 and i16 overflow multiplies. The generated code isn't great, but this at least fixes CodeGen/Generic/overflow.ll when running on ARM hosts. llvm-svn: 122221
* Don't assume that an instruction ending a register's live range always readsCameron Zwarich2010-12-201-4/+18
| | | | | | the register; it may be a dead def instead. Fixes PR8820. llvm-svn: 122218
* Fix a bug in the scheduler's handling of "unspillable" vregs.Chris Lattner2010-12-201-1/+14
| | | | | | | | | | | | | | | | | | Imagine we see: EFLAGS = inst1 EFLAGS = inst2 FLAGS gpr = inst3 EFLAGS Previously, we would refuse to schedule inst2 because it clobbers the EFLAGS of the predecessor. However, it also uses the EFLAGS of the predecessor, so it is safe to emit. SDep edges ensure that the right order happens already anyway. This fixes 2 testsuite crashes with the X86 patch I'm going to commit next. llvm-svn: 122211
* the result of CheckForLiveRegDef is dead, remove it.Chris Lattner2010-12-201-12/+8
| | | | llvm-svn: 122209
* reduce indentation, no functionality change.Chris Lattner2010-12-202-25/+26
| | | | llvm-svn: 122208
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