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* Remove more guts of TargetMachine::getNameWithPrefix and migrate one check ↵Eric Christopher2016-09-201-0/+7
| | | | | | | | to the TLOF mach-o version. NFC intended. llvm-svn: 281983
* Remove extra argument used once on TargetMachine::getNameWithPrefix and ↵Eric Christopher2016-09-201-1/+1
| | | | | | inline the result into the singular caller. llvm-svn: 281981
* Improve the -debug output for Debug Range Extension (NFC)Keith Walker2016-09-201-1/+2
| | | | | | Include header messages and remove unnecessary blank lines. llvm-svn: 281980
* GlobalISel: split aggregates for PCS loweringTim Northover2016-09-204-6/+7
| | | | | | | | | | | This should match the existing behaviour for passing complicated struct and array types, in particular HFAs come through like that from Clang. For C & C++ we still need to somehow support all the weird ABI flags, or at least those that are present in the IR (signext, byval, ...), and stack-based parameter passing. llvm-svn: 281977
* BranchFolder: Fix invalid undef flags after merge.Matthias Braun2016-09-201-5/+14
| | | | | | | | | | It is legal to merge instructions with different undef flags; However we must drop the undef flag from the merged instruction if it isn't present everywhere. This fixes http://llvm.org/PR30199 llvm-svn: 281957
* [RegisterBankInfo] Adapt call to std::fill due to use of SmallVector.Quentin Colombet2016-09-191-1/+1
| | | | | | This was meant to be commited with my previous commit. llvm-svn: 281948
* [RegisterBankInfo] Avoid heap allocation in most cases.Quentin Colombet2016-09-191-1/+1
| | | | | | | | | | | The OperandsMapper class is used heavy in RegBankSelect and each instantiation triggered a heap allocation for the array of operands. Instead, use a SmallVector with a big enough size such that most of the cases do not have to use dynamically allocated memory. This improves the compile time of the RegBankSelect pass. llvm-svn: 281916
* LiveRangeCalc: Fix reporting of invalid vreg usage in liveness calculationMatthias Braun2016-09-191-3/+3
| | | | | | | | | | | | | Machine programs need a definition of each vreg before reaching a use (the definition may come from an IMPLICIT_DEF instruction). This class of errors is not detected by the MachineVerifier because of efficiency concerns. LiveRangeCalc used to report these problems, make it do that again (followup to r279625). Also use report_fatal_error() instead of llvm_unreachable() as the error reporting is only present in asserts build anyway. llvm-svn: 281914
* [XRay] ARM 32-bit no-Thumb support in LLVMDean Michael Berris2016-09-192-29/+96
| | | | | | | | | | | | This is a port of XRay to ARM 32-bit, without Thumb support yet. The XRay instrumentation support is moving up to AsmPrinter. This is one of 3 commits to different repositories of XRay ARM port. The other 2 are: https://reviews.llvm.org/D23932 (Clang test) https://reviews.llvm.org/D23933 (compiler-rt) Differential Revision: https://reviews.llvm.org/D23931 llvm-svn: 281878
* [AVX-512] Don't lower CVTPD2PS intrinsics to ISD::FP_ROUND with an X86 ↵Craig Topper2016-09-181-1/+2
| | | | | | | | rounding mode encoding in the second operand. This immediate should only be 0 or 1 and indicates if the truncation loses precision. Also enhance an assert in SelectionDAG::getNode to flag this sort of problem in the future. llvm-svn: 281868
* [X86][SSE] Improve recognition of uitofp conversions that can be performed ↵Simon Pilgrim2016-09-181-4/+0
| | | | | | | | | | | | | | as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
* Change the order of the splitted store from high - low to low - high.Wei Mi2016-09-181-2/+2
| | | | | | | It is a trivial change which could make the testcase easier to be reused for the store splitting in CodeGenPrepare. llvm-svn: 281846
* Don't create a SymbolTable in Function when the LLVMContext discards value ↵Mehdi Amini2016-09-172-4/+4
| | | | | | | | | | | | | | names (NFC) The ValueSymbolTable is used to detect name conflict and rename instructions automatically. This is not needed when the value names are automatically discarded by the LLVMContext. No functional change intended, just saving a little bit of memory. This is a recommit of r281806 after fixing the accessor to return a pointer instead of a reference and updating all the call-sites. llvm-svn: 281813
* [MIR Parser] Fix Build!Mehdi Amini2016-09-171-1/+1
| | | | | | Last-second refactoring before push was bad idea... llvm-svn: 281812
* MIR Parser: issue an error when the Context discard value names.Mehdi Amini2016-09-171-0/+8
| | | | | | This is in line with the LLParser behavior llvm-svn: 281811
* [safestack] Fix assertion failure in stack coloring.Evgeniy Stepanov2016-09-161-4/+6
| | | | | | | | | | This is a fix for PR30318. Clang may generate IR where an alloca is already live when entering a BB with lifetime.start. In this case, conservatively extend the alloca lifetime all the way back to the block entry. llvm-svn: 281784
* [RegAllocGreedy] Fix the list of NewVRegs for last chance recoloring.Quentin Colombet2016-09-161-2/+22
| | | | | | | | | | | | | | | | | When trying to recolor a register we may split live-ranges in the process. When we create new live-ranges we will have to process them, but when we move a register from Assign to Split, the allocation is not changed until the whole recoloring session is successful. Therefore, only push the live-ranges that changed from Assign to Split when the recoloring is successful. Same as the previous commit, I was not able to produce a test case that reproduce the problem with in-tree targets. Note: The bug has been here since the recoloring scheme has been added back in r200883 (Feb 2014). llvm-svn: 281783
* [RegAllocGreedy] Fix an assertion and condition when last chance recoloring ↵Quentin Colombet2016-09-161-2/+3
| | | | | | | | | | | | | | | | is used. When last chance recoloring is used, the list of NewVRegs may not be empty when calling selectOrSplitImpl. Indeed, another coloring may have taken place with splitting/spilling in the same recoloring session. Relax an assertion to take this into account and adapt a condition to act as if the NewVRegs were local to this selectOrSplitImpl instance. Unfortunately I am unable to produce a test case for this, I was only able to reproduce the conditions on an out-of-tree target. llvm-svn: 281782
* [AArch64][GlobalISel] Test default regbank mapping for G_ICMP.Ahmed Bougacha2016-09-161-1/+1
| | | | | | | Also relax a RegisterBankInfo verifier check that's incompatible with 1-bit mappings. llvm-svn: 281735
* Place the lowered phi instruction(s) before the DEBUG_VALUE entryKeith Walker2016-09-165-5/+19
| | | | | | | | | | | | | | | | When a phi node is finally lowered to a machine instruction it is important that the lowered "load" instruction is placed before the associated DEBUG_VALUE entry describing the value loaded. Renamed the existing SkipPHIsAndLabels to SkipPHIsLabelsAndDebug to more fully describe that it also skips debug entries. Then used the "new" function SkipPHIsAndLabels when the debug information should not be skipped when placing the lowered "load" instructions so that it is placed before the debug entries. Differential Revision: https://reviews.llvm.org/D23760 llvm-svn: 281727
* Move the Mangler from the AsmPrinter down to TLOF and clean up theEric Christopher2016-09-165-81/+62
| | | | | | TLOF API accordingly. llvm-svn: 281708
* GlobalISel: legalize GEP instructions with small offsets.Tim Northover2016-09-151-0/+7
| | | | llvm-svn: 281602
* GlobalISel: relax type constraints on G_ICMP to allow pointers.Tim Northover2016-09-151-3/+1
| | | | llvm-svn: 281600
* GlobalISel: remove "unsized" LLTTim Northover2016-09-155-13/+8
| | | | | | | | It was only really there as a sentinel when instructions had to have precisely one type. Now that registers are typed, each register really has to have a type that is sized. llvm-svn: 281599
* GlobalISel: cache pointer sizes in LLTTim Northover2016-09-153-20/+21
| | | | | | | Otherwise everything that needs to work out what size they are has to keep a DataLayout handy, which is a bit silly and very annoying. llvm-svn: 281597
* Fix indentation in codeview codeReid Kleckner2016-09-141-7/+7
| | | | llvm-svn: 281542
* Finish renaming remaining analyzeBranch functionsMatt Arsenault2016-09-148-56/+56
| | | | llvm-svn: 281535
* [Stackmap] Added callsite counts to emitted function information.Sanjoy Das2016-09-141-13/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: It was previously not possible for tools to use solely the stackmap information emitted to reconstruct the return addresses of callsites in the map, which is necessary to use the information to walk a stack. This patch adds per-function callsite counts when emitting the stackmap section in order to resolve the problem. Note that this slightly alters the stackmap format, so external tools parsing these maps will need to be updated. **Problem Details:** Records only store their offset from the beginning of the function they belong to. While these records and the functions are output in program order, it is not possible to determine where the end of one function's records are without the callsite count when processing the records to compute return addresses. Patch by Kavon Farvardin! Reviewers: atrick, ributzka, sanjoy Subscribers: nemanjai Differential Revision: https://reviews.llvm.org/D23487 llvm-svn: 281532
* Make analyzeBranch family of instruction names consistentMatt Arsenault2016-09-1410-37/+37
| | | | | | | analyzeBranch was renamed to use lowercase first, rename the related set to match. llvm-svn: 281506
* getValueType().getScalarSizeInBits() -> getScalarValueSizeInBits(), round 2 ↵Sanjay Patel2016-09-142-5/+4
| | | | | | ; NFCI llvm-svn: 281498
* getVectorElementType().getSizeInBits() -> getScalarSizeInBits() ; NFCISanjay Patel2016-09-147-17/+15
| | | | llvm-svn: 281495
* getValueType().getSizeInBits() -> getValueSizeInBits() ; NFCISanjay Patel2016-09-1412-62/+54
| | | | llvm-svn: 281493
* getValueType().getScalarSizeInBits() -> getScalarValueSizeInBits() ; NFCISanjay Patel2016-09-143-46/+33
| | | | llvm-svn: 281490
* getScalarType().getSizeInBits() -> getScalarSizeInBits() ; NFCISanjay Patel2016-09-146-70/+70
| | | | llvm-svn: 281489
* [StackProtector] Use INITIALIZE_TM_PASS instead of INITIALIZE_PASSSilviu Baranga2016-09-141-1/+1
| | | | | | | | | | in order to make sure that its TargetMachine constructor is registered. This allows us to run the PEI machine pass with MIR input (see PR30324). llvm-svn: 281474
* [CodeGen] Fix invalid shift in mul expansionPawel Bylica2016-09-131-6/+11
| | | | | | | | | | | | Summary: When expanding mul in type legalization make sure the type for shift amount can actually fit the value. This fixes PR30354 https://llvm.org/bugs/show_bug.cgi?id=30354. Reviewers: hfinkel, majnemer, RKSimon Subscribers: RKSimon, llvm-commits Differential Revision: https://reviews.llvm.org/D24478 llvm-svn: 281403
* [DAG] Allow build-to-shuffle combine to combine builds from two wide vectors.Michael Kuperstein2016-09-131-27/+53
| | | | | | | | | | | This allows us to, in some cases, create a vector_shuffle out of a build_vector, when the inputs to the build are extract_elements from two different vectors, at least one of which is wider than the output. (E.g. a <8 x i16> being constructed out of elements from a <16 x i16> and a <8 x i16>). Differential Revision: https://reviews.llvm.org/D24491 llvm-svn: 281402
* AMDGPU: Support commuting a FrameIndex operandMatt Arsenault2016-09-131-0/+10
| | | | llvm-svn: 281369
* [DAGCombiner] Use APInt directly in (shl (zext (srl x, C)), C) combine range ↵Simon Pilgrim2016-09-131-2/+2
| | | | | | | | | | test To avoid assertion, we must ensure that the inner shift constant is within range before calling ConstantSDNode::getZExtValue(). We already know that the outer shift constant is in range. Followup to D23007 llvm-svn: 281362
* [DAGCombiner] Use APInt directly in (shl (ext (shl x, c1)), c2) combineSimon Pilgrim2016-09-131-11/+15
| | | | | | | | Fix failure to detect out of range shift constants leading to assert in ConstantSDNode::getZExtValue() Followup to D23007 llvm-svn: 281354
* Remove MVT:i1 xor instruction before SELECT. (Performance improvement).Ayman Musa2016-09-131-0/+16
| | | | | | Differential Revision: https://reviews.llvm.org/D23764 llvm-svn: 281308
* DebugInfo: New metadata representation for global variables.Peter Collingbourne2016-09-137-64/+63
| | | | | | | | | | | | | This patch reverses the edge from DIGlobalVariable to GlobalVariable. This will allow us to more easily preserve debug info metadata when manipulating global variables. Fixes PR30362. A program for upgrading test cases is attached to that bug. Differential Revision: http://reviews.llvm.org/D20147 llvm-svn: 281284
* [DAG] Refactor BUILD_VECTOR combine to make it easier to extend. NFCI.Michael Kuperstein2016-09-131-123/+156
| | | | | | | This should make it easier to add cases that we currently don't cover, like supporting more kinds of type mismatches and more than 2 input vectors. llvm-svn: 281283
* Fix the bug introduced in r281252.Dehao Chen2016-09-121-1/+1
| | | | llvm-svn: 281253
* Lower consecutive select instructions correctly.Dehao Chen2016-09-121-23/+75
| | | | | | | | | | | | Summary: If consecutive select instructions are lowered separately in CGP, it will introduce redundant condition check and branches that cannot be removed by later optimization phases. This patch lowers all consecutive select instructions at the same to to avoid inefficent code as demonstrated in https://llvm.org/bugs/show_bug.cgi?id=29095 Reviewers: davidxl Subscribers: vsk, llvm-commits Differential Revision: https://reviews.llvm.org/D24147 llvm-svn: 281252
* [GlobalISel] Fix mismatched "<..)" in intrinsic MO printing. NFC.Ahmed Bougacha2016-09-121-2/+2
| | | | llvm-svn: 281229
* [BranchFolding] Unique added live-ins after hoisting code.Ahmed Bougacha2016-09-121-0/+7
| | | | | | We're not supposed to have duplicate live-ins. llvm-svn: 281224
* GlobalISel: support translation of global addresses.Tim Northover2016-09-122-0/+14
| | | | llvm-svn: 281207
* GlobalISel: translate GEP instructions.Tim Northover2016-09-122-0/+95
| | | | | | | | Unlike SDag, we use a separate G_GEP instruction (much simplified, only taking a single byte offset) to preserve the pointer type information through selection. llvm-svn: 281205
* GlobalISel: disambiguate types when printing MIRTim Northover2016-09-124-19/+56
| | | | | | | | | | | | | | | | | Some generic instructions have multiple types. While in theory these always be discovered by inspecting the single definition of each generic vreg, in practice those definitions won't always be local and traipsing through a big function to find them will not be fun. So this changes MIRPrinter to print out the type of uses as well as defs, if they're known to be different or not known to be the same. On the parsing side, we're a little more flexible: provided each register is given a type in at least one place it's mentioned (and all types are consistent) we accept the MIR. This doesn't introduce ambiguity but makes writing tests manually a bit less painful. llvm-svn: 281204
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