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* LiveIntervalAnalysis: Support moving of subregister defs in handleMoveMatthias Braun2016-02-151-34/+153
| | | | | | | | | | | | | | | | | | | This is an updated version which fixes a bug that happened with uses tied to an earlyclobber operand which end at an unusual slotindex. If two definitions write to independent subregisters then they can be put in any order. LiveIntervalAnalysis::handleMove() did not support this previously because it looks like moving a definition of a vreg past another one. This is a modified version of a patch proposed (two years ago) by Vincent Lejeune! This version does not touch the read-undef flags and is extended for the case of moving a subregister def behind all uses - this can happen for subregister defs that are completely unused. Differential Revision: http://reviews.llvm.org/D9067 llvm-svn: 260906
* MachineVerifier: Add parameter to choose if MachineFunction::verify() abortsMatthias Braun2016-02-151-10/+13
| | | | | | | The abort on error behaviour is unpractical for debugger and unittest usage. llvm-svn: 260904
* [CodeGen] Document and use getConstant's splat-building feature. NFC.Ahmed Bougacha2016-02-152-10/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D17229 llvm-svn: 260901
* [ScheduleDAGInstrs] isUnsafeMemoryObject() removedJonas Paulsson2016-02-151-36/+5
| | | | | | | | | | | This function was basically useless, since volatile memacesses or MIs with unmodelled sideffects become global memory objects, and the other little checks are also done elsewhere. Reviewed by Andy Trick http://reviews.llvm.org/D16881 llvm-svn: 260899
* [AggressiveAntiDepBreaker] Skip some unnecessary BitVector copies.Benjamin Kramer2016-02-131-9/+11
| | | | llvm-svn: 260825
* LiveIntervalAnalysis: Remove LiveVariables requirementMatthias Braun2016-02-133-7/+3
| | | | | | | | | This requirement was a huge hack to keep LiveVariables alive because it was optionally used by TwoAddressInstructionPass and PHIElimination. However we have AnalysisUsage::addUsedIfAvailable() which we can use in those passes. llvm-svn: 260806
* Don't combine fp_round (fp_round x) if f80 to f16 is generatedPirama Arumuga Nainar2016-02-131-0/+11
| | | | | | | | | | | | | | | | | | | | Summary: This patch skips DAG combine of fp_round (fp_round x) if it results in an fp_round from f80 to f16. fp_round from f80 to f16 always generates an expensive (and as yet, unimplemented) libcall to __truncxfhf2. This prevents selection of native f16 conversion instructions from f32 or f64. Moreover, the first (value-preserving) fp_round from f80 to either f32 or f64 may become a NOP in platforms like x86. Reviewers: ab Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D17221 llvm-svn: 260769
* [codeview] Describe local variables in registersReid Kleckner2016-02-122-51/+225
| | | | llvm-svn: 260746
* [WinEH] Prevent EH state numbering from skipping nested cleanup pads that ↵Andrew Kaylor2016-02-121-6/+14
| | | | | | | | never return Differential Revision: http://reviews.llvm.org/D17208 llvm-svn: 260733
* Get rid of some GLOBAL_ISEL ifdefs that should be harmless for code size.Quentin Colombet2016-02-121-8/+3
| | | | | | More to come, but those were easy. llvm-svn: 260723
* GlobalISel is always built since r260566, reflect it in LLVMBuild.txtMehdi Amini2016-02-121-1/+1
| | | | | | | Other component could not depends on an optional library in llvm-config From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 260701
* [IRTranslator] Use a single virtual register to represent any Value.Quentin Colombet2016-02-111-13/+11
| | | | | | PR26161. llvm-svn: 260602
* [Target] Add a helper function to check if an opcode is invalid after isel.Quentin Colombet2016-02-111-1/+13
| | | | llvm-svn: 260590
* Revert "LiveIntervalAnalysis: Support moving of subregister defs in handleMove"Matthias Braun2016-02-111-152/+34
| | | | | | | | | | | | This is broke a bot: http://lab.llvm.org:8011/builders/clang-cmake-aarch64-quick/builds/4703/steps/test-suite/logs/test.log Reverting while I investigate. This reverts commit r260565. llvm-svn: 260586
* [SelectionDAG] change getConstant() to use the input SDLoc when building ↵Sanjay Patel2016-02-111-5/+4
| | | | | | | | | | | | | | | | | | | | | | splat vectors The code change is simple enough: instead of attaching an anonymous SDLoc to splatted vector constants, use the scalar constant's existing SDLoc since that is what is passed into getConstant() as a param. But this changes instruction scheduling, so I'll explain why that happens. The motivation for this patch starts near: http://reviews.llvm.org/rL258833 ...x86's getZeroVector() could be similarly cleaned up and I thought it would be 'NFC'. But when I made that change locally, several x86 codegen tests wiggled. It turns out that the lack of SDLoc consistency in getConstant() changes the way ScheduleDAGRRList behaves. This is because the SDLoc contains 'IROrder' and some DAG scheduler algorithms use IROrder for tie-breaking. Differential Revision: http://reviews.llvm.org/D16972 llvm-svn: 260582
* [GlobalISel] Add the necessary plumbing to lower formal arguments.Quentin Colombet2016-02-111-0/+14
| | | | llvm-svn: 260579
* DwarfDebug: emit type units immediately.Peter Collingbourne2016-02-1110-85/+88
| | | | | | | | | | | | | | | | | | | Rather than storing type units in a vector and emitting them at the end of code generation, emit them immediately and destroy them, reclaiming the memory we were using for their DIEs. In one benchmark carried out against Chromium's 50 largest (by bitcode file size) translation units, total peak memory consumption with type units decreased by median 17%, or by 7% when compared against disabling type units. Tested using check-{llvm,clang}, the GDB 7.5 test suite (with '-fdebug-types-section') and by eyeballing llvm-dwarfdump output on those Chromium translation units with split DWARF both disabled and enabled, and verifying that the only changes were to addresses and abbreviation ordering. Differential Revision: http://reviews.llvm.org/D17118 llvm-svn: 260578
* [codeview] Fix bug around multi-level wrapper inliningReid Kleckner2016-02-111-13/+20
| | | | | | | If there were wrapper functions with no instructions of their own in the inlining tree, we would fail to emit InlineSite records for them. llvm-svn: 260571
* Play nice with Visual Studio and attributesQuentin Colombet2016-02-111-1/+3
| | | | llvm-svn: 260568
* [CMake] Produce an empty library for GlobalISel when not building it.Quentin Colombet2016-02-113-5/+40
| | | | | | | | | | | | | | | | The rational for this change is that LLVMBuild cannot express conditional dependencies. Therefore, when we start optionally using GlobalISel library for say AArch64, without that change, all the tools that use the AArch64 library would need to explicitly link with GlobalISel when we ask for it. This does not scale. Instead, we will set the dependencies between the target and GlobalISel and if we did not ask to build GlobalISel, the library will just be empty. Thanks to Chris Bieneman and Mehdi Animi for the idea. llvm-svn: 260566
* LiveIntervalAnalysis: Support moving of subregister defs in handleMoveMatthias Braun2016-02-111-34/+152
| | | | | | | | | | | | | | | | If two definitions write to independent subregisters then they can be put in any order. LiveIntervalAnalysis::handleMove() did not support this previously because it looks like moving a definition of a vreg past another one. This is a modified version of a patch proposed (two years ago) by Vincent Lejeune! This version does not touch the read-undef flags and is extended for the case of moving a subregister def behind all uses - this can happen for subregister defs that are completely unused. Differential Revision: http://reviews.llvm.org/D9067 llvm-svn: 260565
* [GlobalISel] Teach the IRTranslator how to lower returns.Quentin Colombet2016-02-112-6/+42
| | | | llvm-svn: 260562
* [GlobalISel] Add a type to MachineInstr.Quentin Colombet2016-02-111-5/+20
| | | | | | | | | | | | | | | | | | | | | | | | We actually need that information only for generic instructions, therefore it would be nice not to have to pay the extra memory consumption for all instructions. Especially because a typed non-generic instruction does not make sense. The question is then, is it possible to have that information in a union or something? My initial thought was that we could have a derived class GenericMachineInstr with additional information, but in practice it makes little to no sense since generic MachineInstrs are likely turned into non-generic ones by just switching the opcode. In other words, we don't want to go through the process of creating a new, non-generic MachineInstr, object each time we do this switch. The memory benefit probably is not worth the extra compile time. Another option would be to keep the type of the MachineInstr in a side table. This would induce an extra indirection though. Anyway, I will file a PR to discuss about it and remember we need to come back to it at some point. llvm-svn: 260558
* [GlobalISel] Add a hook in TargetConfigPass to run GlobalISel.Quentin Colombet2016-02-111-2/+14
| | | | llvm-svn: 260553
* [GlobalISel][IRTranslator] Change the ownership of the MIRBuilder field.Quentin Colombet2016-02-111-10/+8
| | | | llvm-svn: 260551
* [GlobalISel][IRTranslator] Fix a typo in assert.Quentin Colombet2016-02-111-1/+1
| | | | llvm-svn: 260550
* [GlobalISel][IRTranslator] Teach the pass how to translate Add instructions.Quentin Colombet2016-02-111-1/+44
| | | | llvm-svn: 260549
* [GlobalISel] Add a MachineIRBuilder class.Quentin Colombet2016-02-112-0/+62
| | | | | | | Helper class to build machine instrs. This is a higher abstraction than MachineInstrBuilder. llvm-svn: 260547
* Drop the hidden visibility from DebugHandlerBase for now.Benjamin Kramer2016-02-111-1/+1
| | | | | | | | | | | | If a class has hidden visibility all derived classes and all classes that have it as a member must have hidden visibility too. That may be fixable here but requires changes to quite a lot of debug info classes. This is also one of the things that GCC enforces aggressively while clang ignores it, making testing more annoying than necessary. llvm-svn: 260529
* [GlobalISel][MachineRegisterInfo] Add a method to create generic vregs.Quentin Colombet2016-02-112-0/+21
| | | | | | | | | | | | | | | | For now, generic virtual registers will not have a register class. We may want to change that. For instance, if we want to use all the methods from TargetRegisterInfo with generic virtual registers, we need to either have some sort of generic register classes that do what we want, or teach those methods how to deal with nullptr register class. Although the latter seems easy enough to do, we may still want to differenciate generic register classes from nullptr to catch cases where nullptr gets introduced by a bug of some sort. Anyway, I will file a PR to keep track of that. llvm-svn: 260474
* [GlobalISel] Remember the size of generic virtual registersQuentin Colombet2016-02-102-1/+17
| | | | llvm-svn: 260468
* [GlobalISel] More detailed skeleton for the IRTranslator.Quentin Colombet2016-02-101-2/+31
| | | | llvm-svn: 260456
* [codeview] Describe int local variables using .cv_def_rangeReid Kleckner2016-02-107-288/+498
| | | | | | | | | | | | | | | | Summary: Refactor common value, scope, and label tracking logic out of DwarfDebug into a common base class called DebugHandlerBase. Update an old LLVM IR test case to avoid an assertion in LexicalScopes. Reviewers: dblaikie, majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D16931 llvm-svn: 260432
* [CodeGen] Prefer "if (SDValue R = ...)" to "if (R.getNode())". NFCI.Ahmed Bougacha2016-02-094-50/+34
| | | | llvm-svn: 260316
* [SelectionDAG] make getMemBasePlusOffset() accessible; NFCISanjay Patel2016-02-091-12/+9
| | | | | | | | | I reinvented this functionality in http://reviews.llvm.org/D16828 because it was hidden away as a static function. The changes in x86 are not based on a complete audit. I suspect there are other possible uses there, and there are almost certainly more potential users in other targets. llvm-svn: 260295
* [regalloc][WinEH] Do not mark intervals as not spillable if they contain a ↵Andrew Kaylor2016-02-082-2/+39
| | | | | | | | regmask Differential Revision: http://reviews.llvm.org/D16831 llvm-svn: 260164
* [X86] Don't zero/sign-extend i1, i8, or i16 return values to 32 bits (PR22532)Hans Wennborg2016-02-081-1/+1
| | | | | | | | | | | | | | | | | | | | This matches GCC and MSVC's behaviour, and saves on code size. We were already not extending i1 return values on x86_64 after r127766. This takes that patch further by applying it to x86 target as well, and also for i8 and i16. The ABI docs have been unclear about the required behaviour here. The new i386 psABI [1] clearly states (Table 2.4, page 14) that i1, i8, and i16 return vales do not need to be extended beyond 8 bits. The x86_64 ABI doc is being updated to say the same [2]. Differential Revision: http://reviews.llvm.org/D16907 [1]. https://01.org/sites/default/files/file_attach/intel386-psabi-1.0.pdf [2]. https://groups.google.com/d/msg/x86-64-abi/E8O33onbnGQ/_RFWw_ixDQAJ llvm-svn: 260133
* SelectionDAG: Lower some range metadata to AssertZextMatt Arsenault2016-02-082-3/+45
| | | | | | | | | | If a range has a lower bound of 0, add an AssertZext from the nearest floor power of two. This allows operations with some workitem intrinsics with known maximum ranges to use fast 24-bit multiplies. llvm-svn: 260109
* [StatepointLower] Use None instead of Optional<int>()Sanjoy Das2016-02-051-5/+5
| | | | llvm-svn: 259956
* Some stackslots are allocated to vregs which have no real reference.Wei Mi2016-02-051-7/+9
| | | | | | | | | | | | | | LiveRangeEdit::eliminateDeadDef is used to remove dead define instructions after rematerialization. To remove a VNI for a vreg from its LiveInterval, LiveIntervals::removeVRegDefAt is used. However, after non-PHI VNIs are all removed, PHI VNI are still left in the LiveInterval. Such unused vregs will be kept in RegsToSpill[] at the end of InlineSpiller::reMaterializeAll and spiller will allocate stackslot for them. The fix is to get rid of unused reg by checking whether it has non-dbg reference instead of whether it has non-empty interval. llvm-svn: 259895
* Fix printing of f16 machine operandsMatt Arsenault2016-02-051-2/+8
| | | | | | | | | | | | | Only single and double FP immediates are correctly printed by MachineInstr::print() during debug output. Half float type goes to APFloat::convertToDouble() and hits assertion it is not a double semantics. This diff prints half machine operands correctly. This cannot currently be hit by any in-tree target. Patch by Stanislav Mekhanoshin llvm-svn: 259857
* Enable the %s modifier in inline asm template stringNemanja Ivanovic2016-02-041-0/+5
| | | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D16847 There are some files in glibc that use the output operand modifier even though it was deprecated in GCC. This patch just adds support for it to prevent issues with such files. llvm-svn: 259798
* [Power PC] softening long double typePetar Jovanovic2016-02-042-26/+71
| | | | | | | | | | | This patch implements softening of long double type (ppcf128) on ppc32 architecture and enables operations for this type for soft float. Patch by Strahinja Petrovic. Differential Revision: http://reviews.llvm.org/D15811 llvm-svn: 259791
* [ScheduleDagInstrs] Improved commentsJonas Paulsson2016-02-041-9/+9
| | | | llvm-svn: 259783
* rangify; NFCISanjay Patel2016-02-031-159/+129
| | | | llvm-svn: 259722
* [codeview] Remove EmitLabelDiff in favor emitAbsoluteSymbolDiffReid Kleckner2016-02-031-18/+4
| | | | llvm-svn: 259700
* [codeview] Use the MCStreamer interface directly instead of AsmPrinterReid Kleckner2016-02-032-101/+100
| | | | | | | | | This is mostly about having shorter lines and standardizing on one interface, but it also avoids some needless indirection. No functional change. llvm-svn: 259697
* [DWARFDebug] Fix another case of overlapping rangesKeno Fischer2016-02-031-13/+42
| | | | | | | | | | | | | | | Summary: In r257979, I added code to ensure that we wouldn't merge DebugLocEntries if the pieces they describe overlap. Unfortunately, I failed to cover the case, where there may have multiple active Expressions in the entry, in which case we need to make sure that no two values overlap before we can perform the merge. This fixed PR26148. Reviewers: aprantl Differential Revision: http://reviews.llvm.org/D16742 llvm-svn: 259696
* [SelectionDAG] Fix CombineToPreIndexedLoadStore O(n^2) behaviorTim Shen2016-02-032-6/+9
| | | | | | | | | | | | | | | | | | | | This patch consists of two parts: a performance fix in DAGCombiner.cpp and a correctness fix in SelectionDAG.cpp. The test case tests the bug that's uncovered by the performance fix, and fixed by the correctness fix. The performance fix keeps the containers required by the hasPredecessorHelper (which is a lazy DFS) and reuse them. Since hasPredecessorHelper is called in a loop, the overall efficiency reduced from O(n^2) to O(n), where n is the number of SDNodes. The correctness fix keeps iterating the neighbor list even if it's time to early return. It will return after finishing adding all neighbors to Worklist, so that no neighbors are discarded due to the original early return. llvm-svn: 259691
* [ScheduleDAGInstrs::buildSchedGraph()] Handling of memory dependecies rewritten.Jonas Paulsson2016-02-031-347/+362
| | | | | | | | | | | | | | | | | | | Recommited, after some fixing with test cases. Updated test cases: test/CodeGen/AArch64/arm64-misched-memdep-bug.ll test/CodeGen/AArch64/tailcall_misched_graph.ll Temporarily disabled test cases: test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll test/CodeGen/PowerPC/ppc64-fastcc.ll (partially updated) test/CodeGen/PowerPC/vsx-fma-m.ll test/CodeGen/PowerPC/vsx-fma-sp.ll http://reviews.llvm.org/D8705 Reviewers: Hal Finkel, Andy Trick. llvm-svn: 259673
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