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* Formatting fixes.Akira Hatanaka2012-05-081-4/+4
| | | | | | Patch by Jack Carter. llvm-svn: 156409
* Handle OpDeref in case it comes in as a register operand.Eric Christopher2012-05-082-4/+7
| | | | | | Part of rdar://11352000 llvm-svn: 156405
* Extract methods for joining physregs.Jakob Stoklund Olesen2012-05-081-77/+103
| | | | | | No functional change. llvm-svn: 156345
* Naming convention and whitespace. No functional change.Jakob Stoklund Olesen2012-05-071-68/+67
| | | | llvm-svn: 156342
* Coalesce subreg-subreg copies.Jakob Stoklund Olesen2012-05-071-14/+25
| | | | | | | | | | | | | | | | | At least some of them: %vreg1:sub_16bit = COPY %vreg2:sub_16bit; GR64:%vreg1, GR32: %vreg2 Previously, we couldn't figure out that the above copy could be eliminated by coalescing %vreg2 with %vreg1:sub_32bit. The new getCommonSuperRegClass() hook makes it possible. This is not very useful yet since the unmodified part of the destination register usually interferes with the source register. The coalescer needs to understand sub-register interference checking first. llvm-svn: 156334
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-0710-22/+29
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* Teach DAG combine to fold x-x to 0.0 when unsafe FP math is enabled.Owen Anderson2012-05-071-0/+4
| | | | llvm-svn: 156324
* Add a new target hook "predictableSelectIsExpensive".Benjamin Kramer2012-05-051-0/+1
| | | | | | | | | | | This will be used to determine whether it's profitable to turn a select into a branch when the branch is likely to be predicted. Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM. I'm not entirely happy with the name of this flag, suggestions welcome ;) llvm-svn: 156233
* Make sure findRepresentativeClass picks the widest super-register.Jakob Stoklund Olesen2012-05-041-6/+10
| | | | | | | | We want the representative register class to contain the largest super-registers available. This makes the function less sensitive to the register class numbering. llvm-svn: 156220
* Remove extra comma in debug output.Jakob Stoklund Olesen2012-05-041-1/+1
| | | | llvm-svn: 156219
* Use SuperRegClassIterator for findRepresentativeClass().Jakob Stoklund Olesen2012-05-041-26/+15
| | | | | | | | The masks returned by SuperRegClassIterator are computed automatically by TableGen. This is better than depending on the manually specified SuperRegClasses. llvm-svn: 156147
* Fix two-address pass's aggressive instruction commuting heuristics. It's meantEvan Cheng2012-05-031-15/+16
| | | | | | | | | | | | | | | | | | | | | | to catch cases like: %reg1024<def> = MOV r1 %reg1025<def> = MOV r0 %reg1026<def> = ADD %reg1024, %reg1025 r0 = MOV %reg1026 By commuting ADD, it let coalescer eliminate all of the copies. However, there was a bug in the heuristics where it ended up commuting the ADD in: %reg1024<def> = MOV r0 %reg1025<def> = MOV 0 %reg1026<def> = ADD %reg1024, %reg1025 r0 = MOV %reg1026 That did no benefit but rather ensure the last MOV would not be coalesced. rdar://11355268 llvm-svn: 156048
* Added TargetRegisterInfo::getAllocatableClass.Andrew Trick2012-05-032-7/+12
| | | | | | | | | | The ensures that virtual registers always belong to an allocatable class. If your target attempts to create a vreg for an operand that has no allocatable register subclass, you will crash quickly. This ensures that targets define register classes as intended. llvm-svn: 156046
* Teach DAGCombine the same multiply-by-1.0 folding trick when doing FMAs, ↵Owen Anderson2012-05-021-0/+18
| | | | | | just like it now knows for FMULs. llvm-svn: 156029
* Teach DAG combine that multiplication by 1.0 can always be constant folded.Owen Anderson2012-05-021-0/+3
| | | | llvm-svn: 156023
* Tidy up. Naming conventions.Jim Grosbach2012-05-011-16/+16
| | | | llvm-svn: 155960
* Use dyn_cast instead of checking opcode and cast.Jakub Staszak2012-05-011-2/+1
| | | | llvm-svn: 155957
* Strip the pointer casts off of allocas so that the selection DAG can find them.Bill Wendling2012-05-011-1/+1
| | | | | | PR10799 llvm-svn: 155954
* Target independent Hexagon Packetizer fix.Sirish Pande2012-05-011-55/+36
| | | | llvm-svn: 155947
* Change the PassManager from a reference to a pointer.Bill Wendling2012-05-011-21/+21
| | | | | | | | | The TargetPassManager's default constructor wants to initialize the PassManager to 'null'. But it's illegal to bind a null reference to a null l-value. Make the ivar a pointer instead. PR12468 llvm-svn: 155902
* Add some constantness. No functionality change.Jakub Staszak2012-04-301-9/+9
| | | | llvm-svn: 155859
* RegisterPressure: ArrayRefize some functions for better readability. No ↵Benjamin Kramer2012-04-292-38/+40
| | | | | | functionality change. llvm-svn: 155795
* Don't update spill weights when joining intervals.Jakob Stoklund Olesen2012-04-281-25/+0
| | | | | | We don't compute spill weights until after coalescing anyway. llvm-svn: 155766
* Spring cleaning - Delete dead code.Jakob Stoklund Olesen2012-04-281-12/+0
| | | | llvm-svn: 155765
* Reapply 155668: Fix the SD scheduler to avoid gluing the same node twice.Andrew Trick2012-04-281-26/+58
| | | | | | | | | | This time, also fix the caller of AddGlue to properly handle incomplete chains. AddGlue had failure modes, but shamefully hid them from its caller. It's luck ran out. Fixes rdar://11314175: BuildSchedUnits assert. llvm-svn: 155749
* Temporarily revert r155668: Fix the SD scheduler to avoid gluing.Andrew Trick2012-04-271-4/+2
| | | | | | This definitely caused regression with ARM -mno-thumb. llvm-svn: 155743
* Fix the SD scheduler to avoid gluing the same node twice.Andrew Trick2012-04-261-3/+5
| | | | | | | | | | | DAGCombine strangeness may result in multiple loads from the same offset. They both may try to glue themselves to another load. We could insist that the redundant loads glue themselves to each other, but the beter fix is to bail out from bad gluing at the time we detect it. Fixes rdar://11314175: BuildSchedUnits assert. llvm-svn: 155668
* Remove more dead code.Jakob Stoklund Olesen2012-04-251-3/+0
| | | | llvm-svn: 155566
* Remove the -disable-cross-class-join option.Jakob Stoklund Olesen2012-04-251-13/+4
| | | | | | | | Cross-class joins have been normal and fully supported for a while now. With TableGen generating the getMatchingSuperRegClass() hook, they are unlikely to cause problems again. llvm-svn: 155552
* Cross-class joining is winning.Jakob Stoklund Olesen2012-04-251-66/+0
| | | | | | | | | | | | Remove the heuristic for disabling cross-class joins. The greedy register allocator can handle the narrow register classes, and when it splits a live range, it can pick a larger register class. Benchmarks were unaffected by this change. <rdar://problem/11302212> llvm-svn: 155551
* Fix a naughty header include that breaks "installed" builds.Andrew Trick2012-04-241-2/+12
| | | | llvm-svn: 155486
* MachineBasicBlock::SplitCriticalEdge() should follow LLVM IR variant and ↵Evan Cheng2012-04-241-0/+5
| | | | | | refuse to break edge to EH landing pad. rdar://11300144 llvm-svn: 155470
* cmake: new fileAndrew Trick2012-04-241-0/+1
| | | | llvm-svn: 155460
* misched: DAG builder must special case earlyclobberAndrew Trick2012-04-241-0/+9
| | | | llvm-svn: 155459
* misched: try (not too hard) to place debug values where they belongAndrew Trick2012-04-241-0/+25
| | | | llvm-svn: 155458
* misched: ignore debug values during schedulingAndrew Trick2012-04-241-6/+31
| | | | llvm-svn: 155457
* misched: DAG builder support for tracking register pressure within the ↵Andrew Trick2012-04-242-5/+58
| | | | | | | | | current scheduling region. The DAG builder is a convenient place to do it. Hopefully this is more efficient than a separate traversal over the same region. llvm-svn: 155456
* RegisterPressure: A utility for computing register pressure within aAndrew Trick2012-04-242-0/+718
| | | | | | | | | | | | | | | | | | MachineInstr sequence. This uses the new target interface for tracking register pressure using pressure sets to model overlapping register classes and subregisters. RegisterPressure results can be tracked incrementally or stored at region boundaries. Global register pressure can be deduced from local RegisterPressure results if desired. This is an early, somewhat untested implementation. I'm working on testing it within the context of a register pressure reducing MachineScheduler. llvm-svn: 155454
* Look for the 'Is Simulated' module flag. This indicates that the program is ↵Bill Wendling2012-04-241-4/+5
| | | | | | compiled to run on a simulator. llvm-svn: 155435
* This patch fixes a problem which arose when using the Post-RA schedulerPreston Gurd2012-04-232-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on X86 Atom. Some of our tests failed because the tail merging part of the BranchFolding pass was creating new basic blocks which did not contain live-in information. When the anti-dependency code in the Post-RA scheduler ran, it would sometimes rename the register containing the function return value because the fact that the return value was live-in to the subsequent block had been lost. To fix this, it is necessary to run the RegisterScavenging code in the BranchFolding pass. This patch makes sure that the register scavenging code is invoked in the X86 subtarget only when post-RA scheduling is being done. Post RA scheduling in the X86 subtarget is only done for Atom. This patch adds a new function to the TargetRegisterClass to control whether or not live-ins should be preserved during branch folding. This is necessary in order for the anti-dependency optimizations done during the PostRASchedulerList pass to work properly when doing Post-RA scheduling for the X86 in general and for the Intel Atom in particular. The patch adds and invokes the new function trackLivenessAfterRegAlloc() instead of using the existing requiresRegisterScavenging(). It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of requiresRegisterScavenging(). It changes the all the targets that implemented requiresRegisterScavenging() to also implement trackLivenessAfterRegAlloc(). It adds an assertion in the Post RA scheduler to make sure that post RA liveness information is available when it is needed. It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order to avoid running into the added assertion. Finally, this patch restores the use of anti-dependency checking (which was turned off temporarily for the 3.1 release) for Intel Atom in the Post RA scheduler. Patch by Andy Zhang! Thanks to Jakob and Anton for their reviews. llvm-svn: 155395
* Temporarily revert r155364 until the upstream review can complete, perChandler Carruth2012-04-231-36/+55
| | | | | | the stated developer policy. llvm-svn: 155373
* Hexagon Packetizer's target independent fix.Sirish Pande2012-04-231-55/+36
| | | | llvm-svn: 155364
* ZERO_EXTEND/SIGN_EXTEND/TRUNCATE optimization for AVX2Elena Demikhovsky2012-04-221-0/+2
| | | | llvm-svn: 155309
* Teach getVectorTypeBreakdown about promotion of vectors in addition to ↵Nadav Rotem2012-04-211-3/+6
| | | | | | widening of vectors. llvm-svn: 155296
* Fix PR12599.Jakob Stoklund Olesen2012-04-201-1/+6
| | | | | | | | The X86 target is editing the selection DAG while isel is selecting nodes following a topological ordering. When the DAG hacking triggers CSE, nodes can be deleted and bad things happen. llvm-svn: 155257
* Make ISelPosition a local variable.Jakob Stoklund Olesen2012-04-201-8/+25
| | | | | | | | | Now that multiple DAGUpdateListeners can be active at the same time, ISelPosition can become a local variable in DoInstructionSelection. We simply register an ISelUpdater with CurDAG while ISelPosition exists. llvm-svn: 155249
* Register DAGUpdateListeners with SelectionDAG.Jakob Stoklund Olesen2012-04-206-119/+87
| | | | | | | | | | | | | | | Instead of passing listener pointers to RAUW, let SelectionDAG itself keep a linked list of interested listeners. This makes it possible to have multiple listeners active at once, like RAUWUpdateListener was already doing. It also makes it possible to register listeners up the call stack without controlling all RAUW calls below. DAGUpdateListener uses an RAII pattern to add itself to the SelectionDAG list of active listeners. llvm-svn: 155248
* Print <def,read-undef> to avoid confusion.Jakob Stoklund Olesen2012-04-201-1/+5
| | | | | | | | The <undef> flag on a def operand only applies to partial register redefinitions. Only print the flag when relevant, and print it as <def,read-undef> to make it clearer what it means. llvm-svn: 155239
* New and improved comment.Andrew Trick2012-04-201-1/+1
| | | | llvm-svn: 155229
* SparseSet: Add support for key-derived indexes and arbitrary key types.Andrew Trick2012-04-202-3/+3
| | | | | | | | | | | | | | | | | | | This nicely handles the most common case of virtual register sets, but also handles anticipated cases where we will map pointers to IDs. The goal is not to develop a completely generic SparseSet template. Instead we want to handle the expected uses within llvm without any template antics in the client code. I'm adding a bit of template nastiness here, and some assumption about expected usage in order to make the client code very clean. The expected common uses cases I'm designing for: - integer keys that need to be reindexed, and may map to additional data - densely numbered objects where we want pointer keys because no number->object map exists. llvm-svn: 155227
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