summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
* Reapply "[CGP] Check for existing inttotpr before creating new one"Roman Tereshin2019-01-191-4/+18
| | | | | | Original commit: r351582 llvm-svn: 351626
* Revert "Reapply "[CGP] Check for existing inttotpr before creating new one""Roman Tereshin2019-01-191-17/+4
| | | | | | | | | | This reverts commit r351618. Compiler RT + ASAN tests are failing for PowerPC. Not sure how would I reproduce these on macOS, so reverting (again) until I do. llvm-svn: 351619
* Reapply "[CGP] Check for existing inttotpr before creating new one"Roman Tereshin2019-01-191-4/+17
| | | | | | Original commit: r351582 llvm-svn: 351618
* Revert r351584: "GlobalISel: Verify g_zextload and g_sextload"Amara Emerson2019-01-191-14/+1
| | | | | | This new assertion triggered on the AArch64 GlobalISel bots. Reverting while it's being investigated. llvm-svn: 351617
* Revert "[CGP] Check for existing inttotpr before creating new one"Roman Tereshin2019-01-181-13/+4
| | | | | | | | This reverts commit r351582. Bots are failing. Reverting this to fix and re-commit later. llvm-svn: 351598
* GlobalISel: Verify G_BITCASTMatt Arsenault2019-01-181-0/+13
| | | | llvm-svn: 351594
* GlobalISel: Verify G_ICMP/G_FCMP vector typesMatt Arsenault2019-01-181-0/+11
| | | | llvm-svn: 351591
* GlobalISel: Verify g_zextload and g_sextloadMatt Arsenault2019-01-181-1/+14
| | | | llvm-svn: 351584
* [CGP] Check for existing inttotpr before creating new oneRoman Tereshin2019-01-181-4/+13
| | | | | | | | | | | | | | | | Make sure CodeGenPrepare doesn't emit multiple inttoptr instructions of the same integer value while sinking address computations, but rather CSEs them on the fly: excessive inttoptr's confuse SCEV into thinking that related pointers have nothing to do with each other. This problem blocks LoadStoreVectorizer from vectorizing some of the loads / stores in a downstream target. Reviewed By: hfinkel Differential Revision: https://reviews.llvm.org/D56838 llvm-svn: 351582
* [SelectionDAG] Updates for -dag-dump-verboseBjorn Pettersson2019-01-182-35/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch makes some changes related to -dag-dump-verbose. Main use case has been when debugging how SelectionDAG is dealing with debug info (SDDbgValue nodes). 1) We now print the number of DbgValues that are mapped to each SDNode. 2) Removed duplicated printing of DebugLoc (nowadays DebugLoc is printed also when not using -dag-dump-verbose). 3) Renamed SDDbgValue::dump to SDDbgValue::print, and added a new SDDbgValue::dump that will start a new line after calling print. 4) SDDbgValue::print now prints "Order", and it also prints some additional information when kind is CONST/FRAMEIX/VREG. 5) SelectionDAG::dump() now dumps all SDDbgValue nodes after the list of SDNodes (both "regular" and "ByVal" SDDbgValue:s). Invalidated nodes are not printed. 6) Prohibit inline printing of SDNode operands that has SDDbgValue nodes associated to them. Reviewers: jmorse, aprantl Reviewed By: aprantl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D56793 llvm-svn: 351581
* [GlobalISel] Change to range-based invocation of llvm::sortMandeep Singh Grang2019-01-181-6/+3
| | | | llvm-svn: 351574
* [SelectionDAG] Split very large token factors for chained stores to 64k chunks.Florian Hahn2019-01-181-1/+1
| | | | | | | | | | | | | | Similar to D55073. Without this change, the DAG combiner crashes on code with more than 64k of stores in a single basic block that form parallelizable chains. No test case, as it would be very IR file. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D56740 llvm-svn: 351571
* [SelectionDAGBuilder] Cleanup InlineAsm Output generation. NFCI.Nirav Dave2019-01-181-115/+104
| | | | | | | | Defer inline asm's output fixup work until after we've generated the inline asm node itself. Remove StoresToEmit, IndirectStoresToEmit, and RetValRegs in favor of using ConstraintOperands. llvm-svn: 351558
* [SelectionDAG] Add getTokenFactor, which splits nodes with > 64k operands.Florian Hahn2019-01-182-13/+14
| | | | | | | | | This functionality is required at multiple places which potentially create large operand lists, like SelectionDAGBuilder or DAGCombiner. Differential Revision: https://reviews.llvm.org/D56739 llvm-svn: 351552
* [SelectionDAG] Add static getMaxNumOperands function to SDNode.Florian Hahn2019-01-182-3/+2
| | | | | | | | | | | | | | | | | | | Summary: Use this helper to make sure we use the same value at various places. This will likely be needed at more places were we currently crash because we use more operands than possible. Also makes it easier to change in the future. Reviewers: RKSimon, craig.topper, efriedma, aemerson Reviewed By: RKSimon Subscribers: hiraditya, arsenm, llvm-commits Differential Revision: https://reviews.llvm.org/D56859 llvm-svn: 351537
* [ScheduleDAGRRList] Do not preschedule the node has ADJCALLSTACKDOWN parentShiva Chen2019-01-181-0/+23
| | | | | | | | | | | | We should not pre-scheduled the node has ADJCALLSTACKDOWN parent, or else, when bottom-up scheduling, ADJCALLSTACKDOWN and ADJCALLSTACKUP may hold CallResource too long and make other calls can't be scheduled. If there's no other available node to schedule, the scheduler will try to rename the register by creating copy to avoid the conflict which will fail because CallResource is not a real physical register. llvm-svn: 351527
* [CodeGen] Fix bugs in LiveDebugVariables when debug labels are generated.Hsiangkai Wang2019-01-181-13/+125
| | | | | | | | | | | | Remove DBG_LABELs in LiveDebugVariables and generate them in VirtRegRewriter. This bug is reported in https://bugs.chromium.org/p/chromium/issues/detail?id=898152. Differential Revision: https://reviews.llvm.org/D54465 llvm-svn: 351525
* [mips] Emit .reloc R_{MICRO}MIPS_JALR along with j(al)r(c) $25Vladimir Stefanovic2019-01-171-2/+3
| | | | | | | | | | | | The callee address is added as an optional operand (MCSymbol) in AdjustInstrPostInstrSelection() and then used by asm printer to insert: '.reloc tmplabel, R_MIPS_JALR, symbol tmplabel:'. Controlled with '-mips-jalr-reloc', default is true. Differential revision: https://reviews.llvm.org/D56694 llvm-svn: 351485
* Allow FP types for atomicrmw xchgMatt Arsenault2019-01-175-1/+70
| | | | llvm-svn: 351427
* [AsmPrinter] Collapse .loc 0 0 directivesJonas Devlieghere2019-01-161-1/+1
| | | | | | | | | | | | | | | | Currently we do not always collapse subsequent .loc 0 0 directives. The reason is that we were checking for a PrevInstLoc which is not set when we emit a line-0 record. We should only check the LastAsmLine, which seems to be created exactly for this purpose. // When we emit a line-0 record, we don't update PrevInstLoc; so look at // the last line number actually emitted, to see if it was line 0. unsigned LastAsmLine = Asm->OutStreamer->getContext().getCurrentDwarfLoc().getLine(); Differential revision: https://reviews.llvm.org/D56767 llvm-svn: 351395
* [COFF, ARM64] Implement support for SEH extensions __try/__except/__finallyMandeep Singh Grang2019-01-162-9/+16
| | | | | | | | | | | | | | | | | Summary: This patch supports MS SEH extensions __try/__except/__finally. The intrinsics localescape and localrecover are responsible for communicating escaped static allocas from the try block to the handler. We need to preserve frame pointers for SEH. So we create a new function/property HasLocalEscape. Reviewers: rnk, compnerd, mstorsjo, TomTan, efriedma, ssijaric Reviewed By: rnk, efriedma Subscribers: smeenai, jrmuizel, alex, majnemer, ssijaric, ehsan, dmajor, kristina, javed.absar, kristof.beyls, chrib, llvm-commits Differential Revision: https://reviews.llvm.org/D53540 llvm-svn: 351370
* [DebugInfo] Allow creation of DBG_VALUEs in blocks where the operand is not usedJeremy Morse2019-01-161-5/+6
| | | | | | | | | | | | | dbg.value intrinsics can appear in blocks where their operand is not used, meaning the operand never receives an SDNode, and thus no DBG_VALUE will be created. Get around this by looking to see whether the operand has already been allocated a virtual register. This allows dbg.values of Phi node and Values that are used across basic blocks to successfully be translated into DBG_VALUEs. Differential Revision: https://reviews.llvm.org/D56678 llvm-svn: 351358
* [SelectionDAG] Update check in createOperands to reflect max() is a valid value.Florian Hahn2019-01-161-1/+1
| | | | | | | | | | | | | | | The value returned by max() is the last valid value, adjust the comparison accordingly. The code added in D55073 creates TokenFactors with max() operands. Reviewers: aemerson, efriedma, RKSimon, craig.topper Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D56738 llvm-svn: 351318
* [DAGCombine] Fix ReduceLoadWidth for shifted offsetsSam Parker2019-01-161-12/+8
| | | | | | | | | | | | ReduceLoadWidth can trigger using a shifted mask is used and this requires that the function return a shl node to correct for the offset. However, the way that this was implemented meant that the returned result could be an existing node, which would be incorrect. This fixes the method of inserting the new node and replacing uses. Differential Revision: https://reviews.llvm.org/D50432 llvm-svn: 351310
* [GISel]: Add support for CSEing continuously during GISel passes.Aditya Nandakumar2019-01-1611-74/+814
| | | | | | | | | | https://reviews.llvm.org/D52803 This patch adds support to continuously CSE instructions during each of the GISel passes. It consists of a GISelCSEInfo analysis pass that can be used by the CSEMIRBuilder. llvm-svn: 351283
* [EH] Rename llvm.x86.seh.recoverfp intrinsic to llvm.eh.recoverfpMandeep Singh Grang2019-01-162-2/+2
| | | | | | | | | | | | | | | | Summary: Make recoverfp intrinsic target-independent so that it can be implemented for AArch64, etc. Refer D53541 for the context. Clang counterpart D56748. Reviewers: rnk, efriedma Reviewed By: rnk, efriedma Subscribers: javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D56747 llvm-svn: 351281
* Reapply "[CodeGen][X86] Expand USUBSAT to UMAX+SUB, also for vectors"Nikita Popov2019-01-152-4/+28
| | | | | | | | | | | | | Related to https://bugs.llvm.org/show_bug.cgi?id=40123. Rather than scalarizing, expand a vector USUBSAT into UMAX+SUB, which produces much better code for X86. Reapplying with updated SLPVectorizer tests. Differential Revision: https://reviews.llvm.org/D56636 llvm-svn: 351219
* [SelectionDAG] Check membership of register in class for singleNirav Dave2019-01-151-6/+1
| | | | | | | | | register constraints. NFCI. Now that X86's ST(7) constraints are fixed this check can be reinstated. llvm-svn: 351207
* [DAGCombiner] reduce buildvec of zexted extracted element to shuffleSanjay Patel2019-01-151-0/+75
| | | | | | | | | | | | | | | The motivating case for this is shown in the first regression test. We are transferring to scalar and back rather than just zero-extending with 'vpmovzxdq'. That's a special-case for a more general pattern as shown here. In all tests, we're avoiding the vector-scalar-vector moves in favor of vector ops. We aren't producing optimal shuffle code in some cases though, so the patch is limited to reduce regressions. Differential Revision: https://reviews.llvm.org/D56281 llvm-svn: 351198
* [EarlyIfConversion] Don't if-convert unconditional branches.Eli Friedman2019-01-151-0/+7
| | | | | | | | | | | | | A block ending in an unconditional branch can have two successors if one is a landing pad. In practice, I think this only has an effect on Windows because landing pads are never empty for Itanium unwinding. (Alternatively, I could add a check to AArch64InstrInfo::canInsertSelect, but this seems more obvious.) Differential Revision: https://reviews.llvm.org/D56468 llvm-svn: 351142
* Revert "[CodeGen][X86] Expand USUBSAT to UMAX+SUB, also for vectors"Nikita Popov2019-01-142-28/+4
| | | | | | | | | This reverts commit r351125. I missed test changes in an SLPVectorizer test, due to the cost model changes. Reverting for now. llvm-svn: 351129
* [CodeGen][X86] Expand USUBSAT to UMAX+SUB, also for vectorsNikita Popov2019-01-142-4/+28
| | | | | | | | | | | Related to https://bugs.llvm.org/show_bug.cgi?id=40123. Rather than scalarizing, expand a vector USUBSAT into UMAX+SUB, which produces much better code for X86. Differential Revision: https://reviews.llvm.org/D56636 llvm-svn: 351125
* Reapply r345008 "Split MachinePipeliner code into header and cpp files"Adrian Prantl2019-01-141-595/+18
| | | | | | | | | | | | | | Split MachinePipeliner code into header and cpp files to allow inheritance from SwingSchedulerDAG. This reapplies https://reviews.llvm.org/D56084 after moving the implementation of the dump functions into the .cpp files. This fixes a linker error when building with Clang modules enables and local submodule visibility disabled. Original patch by Lama Saba <lama.saba@intel.com>! llvm-svn: 351077
* Reland "Refactor GetRegistersForValue. NFCI."Nirav Dave2019-01-141-55/+44
| | | | | | Remove over-strictification class membership check. llvm-svn: 351074
* [DAGCombiner] Add (sub_sat x, x) -> 0 combineSimon Pilgrim2019-01-141-0/+4
| | | | llvm-svn: 351073
* [DAGCombiner] Enable sub saturation constant foldingSimon Pilgrim2019-01-142-1/+8
| | | | llvm-svn: 351072
* [DAGCombiner] Add add/sub saturation undef handlingSimon Pilgrim2019-01-142-0/+14
| | | | | | | | Match ConstantFolding.cpp: (add_sat x, undef) -> -1 (sub_sat x, undef) -> 0 llvm-svn: 351070
* [DAGCombiner] Enable add saturation constant foldingSimon Pilgrim2019-01-142-2/+5
| | | | llvm-svn: 351060
* [DAGCombiner] Add add saturation constant folding tests.Simon Pilgrim2019-01-141-2/+3
| | | | | | Exposes an issue with sadd_sat for computeOverflowKind, so I've disabled it for now. llvm-svn: 351057
* [SelectionDAG] Add type sanity assertions for add/sub saturation node creation.Simon Pilgrim2019-01-141-0/+4
| | | | llvm-svn: 351055
* Replace "no-frame-pointer-*" function attributes with "frame-pointer"Francis Visoiu Mistrih2019-01-142-12/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Part of the effort to refactoring frame pointer code generation. We used to use two function attributes "no-frame-pointer-elim" and "no-frame-pointer-elim-non-leaf" to represent three kinds of frame pointer usage: (all) frames use frame pointer, (non-leaf) frames use frame pointer, (none) frame use frame pointer. This CL makes the idea explicit by using only one enum function attribute "frame-pointer" Option "-frame-pointer=" replaces "-disable-fp-elim" for tools such as llc. "no-frame-pointer-elim" and "no-frame-pointer-elim-non-leaf" are still supported for easy migration to "frame-pointer". tests are mostly updated with // replace command line args ‘-disable-fp-elim=false’ with ‘-frame-pointer=none’ grep -iIrnl '\-disable-fp-elim=false' * | xargs sed -i '' -e "s/-disable-fp-elim=false/-frame-pointer=none/g" // replace command line args ‘-disable-fp-elim’ with ‘-frame-pointer=all’ grep -iIrnl '\-disable-fp-elim' * | xargs sed -i '' -e "s/-disable-fp-elim/-frame-pointer=all/g" Patch by Yuanfang Chen (tabloid.adroit)! Differential Revision: https://reviews.llvm.org/D56351 llvm-svn: 351049
* [DAGCombiner] If add_sat(x,y) can't overflow -> add(x,y)Simon Pilgrim2019-01-131-0/+4
| | | | | NOTE: We need more powerful signed overflow detection in computeOverflowKind llvm-svn: 351026
* Fix unused variable warning. NFCI.Simon Pilgrim2019-01-131-1/+0
| | | | llvm-svn: 351025
* [DAGCombiner] Some very basic add/sub saturation combines.Simon Pilgrim2019-01-131-0/+64
| | | | | | Handle combines with zero and constant canonicalization for adds. llvm-svn: 351024
* [LegalizeDAG] Remove 'NeedInvert' code from expansion of BR_CC. Replace with ↵Craig Topper2019-01-131-4/+1
| | | | | | | | | | | | an assert. I accidentally triggered this code while doing some experiments and it doesn't look lke it could possibly work. It calls 'getNOT' on a node that should be a CondCode. I think to do this right we would need to swap the branch target and the fallthrough target. But that's not easy to do. Or we could create an explicit SetCC and feed that into a new BR_CC? llvm-svn: 351022
* [X86] Rename overly verbose method; NFCNikita Popov2019-01-133-8/+5
| | | | | | As suggested on D56636. llvm-svn: 351021
* Give helper classes/functions local linkage. NFC.Benjamin Kramer2019-01-123-2/+6
| | | | llvm-svn: 351016
* [DAGCombiner] fold insert_subvector of insert_subvectorSanjay Patel2019-01-121-0/+8
| | | | | | | | | | | | | | | | | | | This pattern: t33: v8i32 = insert_subvector undef:v8i32, t35, Constant:i64<0> t21: v16i32 = insert_subvector undef:v16i32, t33, Constant:i64<0> ...shows up in PR33758: https://bugs.llvm.org/show_bug.cgi?id=33758 ...although this patch doesn't make any difference to the final result on that yet. In the affected tests here, it looks like it just makes RA wiggle. But we might as well squash this to prevent it interfering with other pattern-matching. Differential Revision: https://reviews.llvm.org/D56604 llvm-svn: 351008
* Use getShiftAmountTy for shift amounts.Simon Pilgrim2019-01-121-1/+2
| | | | llvm-svn: 351005
* [X86][AARCH64] Improve ISD::ABS supportSimon Pilgrim2019-01-123-0/+43
| | | | | | | | This patch takes some of the code from D49837 to allow us to enable ISD::ABS support for all SSE vector types. Differential Revision: https://reviews.llvm.org/D56544 llvm-svn: 350998
OpenPOWER on IntegriCloud