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* When fast iseling a GEP, accumulate the offset rather than emitting a series ofChad Rosier2011-11-171-11/+35
| | | | | | | | | | | | | ADDs. MaxOffs is used as a threshold to limit the size of the offset. Tradeoffs being: (1) If we can't materialize the large constant then we'll cause fast-isel to bail. (2) Too large of an offset can't be directly encoded in the ADD resulting in a MOV+ADD. Generally not a bad thing because otherwise we would have had ADD+ADD, but on Thumb this turns into a MOVS+MOVT+ADD. Working on a fix for that. (3) Conversely, too low of a threshold we'll miss opportunities to coalesce ADDs. rdar://10412592 llvm-svn: 144886
* Make sure to replace the chain properly when DAGCombining a ↵Eli Friedman2011-11-161-4/+17
| | | | | | LOAD+EXTRACT_VECTOR_ELT into a single LOAD. Fixes PR10747/PR11393. llvm-svn: 144863
* Add fast-isel stats to determine who's doing all the work, the Chad Rosier2011-11-161-0/+7
| | | | | | target-independent selector or the target-specific selector. llvm-svn: 144833
* Fix the stats collection for fast-isel. The failed count was only accountingChad Rosier2011-11-161-5/+18
| | | | | | | | | for a single miss and not all predecessor instructions that get selected by the selection DAG instruction selector. This is still not exact (e.g., over states misses when folded/dead instructions are present), but it is a step in the right direction. llvm-svn: 144832
* Disable expensive two-address optimizations at -O0. rdar://10453055Evan Cheng2011-11-161-0/+8
| | | | llvm-svn: 144806
* Disable the assertion again. Looks like fastisel is still generating bad ↵Evan Cheng2011-11-161-1/+2
| | | | | | kill markers. llvm-svn: 144804
* Sink codegen optimization level into MCCodeGenInfo along side relocation modelEvan Cheng2011-11-162-33/+30
| | | | | | | and code model. This eliminates the need to pass OptLevel flag all over the place and makes it possible for any codegen pass to use this information. llvm-svn: 144788
* Record landing pads with a SmallSetVector to avoid multiple entries.Bob Wilson2011-11-161-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There may be many invokes that share one landing pad, and the previous code would record the landing pad once for each invoke. Besides the wasted effort, a pair of volatile loads gets inserted every time the landing pad is processed. The rest of the code can get optimized away when a landing pad is processed repeatedly, but the volatile loads remain, resulting in code like: LBB35_18: Ltmp483: ldr r2, [r7, #-72] ldr r2, [r7, #-68] ldr r2, [r7, #-72] ldr r2, [r7, #-68] ldr r2, [r7, #-72] ldr r2, [r7, #-68] ldr r2, [r7, #-72] ldr r2, [r7, #-68] ldr r2, [r7, #-72] ldr r2, [r7, #-68] ldr r2, [r7, #-72] ldr r2, [r7, #-68] ldr r2, [r7, #-72] ldr r2, [r7, #-68] ldr r2, [r7, #-72] ldr r2, [r7, #-68] ldr r4, [r7, #-72] ldr r2, [r7, #-68] llvm-svn: 144787
* Update the SP in the SjLj jmpbuf whenever it changes. <rdar://problem/10444602>Bob Wilson2011-11-161-3/+21
| | | | | | | This same basic code was in the older version of the SjLj exception handling, but it was removed in the recent revisions to that code. It needs to be there. llvm-svn: 144782
* Revert r144568 now that r144730 has fixed the fast-isel kill marker bug.Evan Cheng2011-11-161-2/+1
| | | | llvm-svn: 144776
* If the 2addr instruction has other kills, don't move it below any other uses ↵Evan Cheng2011-11-161-2/+7
| | | | | | since we don't want to extend other live ranges. llvm-svn: 144772
* RescheduleKillAboveMI() must backtrack to before the rescheduled DBG_VALUE ↵Evan Cheng2011-11-161-1/+1
| | | | | | instructions. rdar://10451185 llvm-svn: 144771
* Process all uses first before defs to accurately capture register liveness. ↵Evan Cheng2011-11-161-7/+13
| | | | | | rdar://10449480 llvm-svn: 144770
* CONCAT_VECTORS can have more than two operands. PR11389.Eli Friedman2011-11-161-22/+12
| | | | llvm-svn: 144768
* Add a couple asserts so it will be easier to debug if we accidentally pass ↵Eli Friedman2011-11-161-0/+4
| | | | | | indexed loads/stores to the legalizer. llvm-svn: 144767
* Rename MVT::untyped to MVT::Untyped to match similar nomenclature.Owen Anderson2011-11-162-3/+3
| | | | llvm-svn: 144747
* Stabilize the output of the dwarf accelerator tables. Fixes a comparisonEric Christopher2011-11-151-2/+11
| | | | | | failure during bootstrap with it turned on. llvm-svn: 144731
* GEPs with all zero indices are trivially coalesced by fast-isel. For example,Chad Rosier2011-11-151-0/+5
| | | | | | | | | | | | | %arrayidx135 = getelementptr inbounds [4 x [4 x [4 x [4 x i32]]]]* %M0, i32 0, i64 0 %arrayidx136 = getelementptr inbounds [4 x [4 x [4 x i32]]]* %arrayidx135, i32 0, i64 %idxprom134 Prior to this commit, the GEP instruction that defines %arrayidx136 thought that %arrayidx135 was a trivial kill. The GEP that defines %arrayidx135 doesn't generate any code and thus %M0 gets folded into the second GEP. Thus, we need to look through GEPs with all zero indices. rdar://10443319 llvm-svn: 144730
* Added custom lowering for load->dec->store sequence in x86 when the EFLAGS ↵Pete Cooper2011-11-151-0/+5
| | | | | | | | | | | | registers is used by later instructions. Only done for DEC64m right now. Fixes <rdar://problem/6172640> llvm-svn: 144705
* Insert modified DBG_VALUE into LiveDbgValueMap. Devang Patel2011-11-151-1/+1
| | | | llvm-svn: 144696
* We currently use a callback to handle an IL pass deleting a BB that stillRafael Espindola2011-11-151-0/+12
| | | | | | | | | | | has a reference to it. Unfortunately, that doesn't work for codegen passes since we don't get notified of MBB's being deleted (the original BB stays). Use that fact to our advantage and after printing a function, check if any of the IL BBs corresponds to a symbol that was not printed. This fixes pr11202. llvm-svn: 144674
* Remove all remaining uses of Value::getNameStr().Benjamin Kramer2011-11-157-16/+16
| | | | llvm-svn: 144648
* Twinify GraphWriter a little bit.Benjamin Kramer2011-11-154-9/+9
| | | | llvm-svn: 144647
* Check all overlaps when looking for used registers.Jakob Stoklund Olesen2011-11-151-4/+5
| | | | | | A function using any RC alias is enough to enable the ExeDepsFix pass. llvm-svn: 144636
* Make use of MachinePointerInfo::getFixedStack.Jay Foad2011-11-151-2/+1
| | | | llvm-svn: 144635
* Remove some unnecessary includes of PseudoSourceValue.h.Jay Foad2011-11-157-7/+0
| | | | llvm-svn: 144634
* Set SeenStore to true to prevent loads from being moved; also eliminates a ↵Evan Cheng2011-11-151-2/+2
| | | | | | non-deterministic behavior. llvm-svn: 144628
* Rather than trying to use the loop block sequence *or* the functionChandler Carruth2011-11-151-27/+24
| | | | | | | | | | | | | | | | | | | | | | | block sequence when recovering from unanalyzable control flow constructs, *always* use the function sequence. I'm not sure why I ever went down the path of trying to use the loop sequence, it is fundamentally not the correct sequence to use. We're trying to preserve the incoming layout in the cases of unreasonable control flow, and that is only encoded at the function level. We already have a filter to select *exactly* the sub-set of blocks within the function that we're trying to form into a chain. The resulting code layout is also significantly better because of this. In several places we were ending up with completely unreasonable control flow constructs due to the ordering chosen by the loop structure for its internal storage. This change removes a completely wasteful vector of basic blocks, saving memory allocation in the common case even though it costs us CPU in the fairly rare case of unnatural loops. Finally, it fixes the latest crasher reduced out of GCC's single source. Thanks again to Benjamin Kramer for the reduction, my bugpoint skills failed at it. llvm-svn: 144627
* Break false dependencies before partial register updates.Jakob Stoklund Olesen2011-11-151-0/+27
| | | | | | | | | | | | | | Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix about instructions with partial register updates causing false unwanted dependencies. The ExecutionDepsFix pass will break the false dependencies if the updated register was written in the previoius N instructions. The small loop added to sse-domains.ll runs twice as fast with dependency-breaking instructions inserted. llvm-svn: 144602
* Track register ages more accurately.Jakob Stoklund Olesen2011-11-151-101/+184
| | | | | | | | | | | | | | | Keep track of the last instruction to define each register individually instead of per DomainValue. This lets us track more accurately when a register was last written. Also track register ages across basic blocks. When entering a new basic block, use the least stale predecessor def as a worst case estimate for register age. The register age is used to arbitrate between conflicting domains. The most recently defined register wins. llvm-svn: 144601
* Avoid dereferencing off the beginning of lists.Evan Cheng2011-11-141-7/+4
| | | | llvm-svn: 144569
* At -O0, multiple uses of a virtual registers in the same BB are being markedEvan Cheng2011-11-141-1/+2
| | | | | | | | "kill". This looks like a bug upstream. Since that's going to take some time to understand, loosen the assertion and disable the optimization when multiple kills are seen. llvm-svn: 144568
* Teach two-address pass to re-schedule two-address instructions (or the killEvan Cheng2011-11-141-19/+356
| | | | | | | | | instructions of the two-address operands) in order to avoid inserting copies. This fixes the few regressions introduced when the two-address hack was disabled (without regressing the improvements). rdar://10422688 llvm-svn: 144559
* Fix early-clobber handling in shrinkToUses.Jakob Stoklund Olesen2011-11-141-12/+8
| | | | | | | | I broke this in r144515, it affected most ARM testers. <rdar://problem/10441389> llvm-svn: 144547
* It helps to deallocate memory as well as allocate it. =] This actuallyChandler Carruth2011-11-141-0/+1
| | | | | | | | cleans up all the chains allocated during the processing of each function so that for very large inputs we don't just grow memory usage without bound. llvm-svn: 144533
* Remove an over-eager assert that was firing on one of the ARM regressionChandler Carruth2011-11-141-3/+6
| | | | | | | | | | | | | | tests when I forcibly enabled block placement. It is apparantly possible for an unanalyzable block to fallthrough to a non-loop block. I don't actually beleive this is correct, I believe that 'canFallThrough' is returning true needlessly for the code construct, and I've left a bit of a FIXME on the verification code to try to track down why this is coming up. Anyways, removing the assert doesn't degrade the correctness of the algorithm. llvm-svn: 144532
* Begin chipping away at one of the biggest quadratic-ish behaviors inChandler Carruth2011-11-141-2/+26
| | | | | | | | | | | | | | this pass. We're leaving already merged blocks on the worklist, and scanning them again and again only to determine each time through that indeed they aren't viable. We can instead remove them once we're going to have to scan the worklist. This is the easy way to implement removing them. If this remains on the profile (as I somewhat suspect it will), we can get a lot more clever here, as the worklist's order is essentially irrelevant. We can use swapping and fold the two loops to reduce overhead even when there are many blocks on the worklist but only a few of them are removed. llvm-svn: 144531
* Under the hood, MBPI is doing a linear scan of every successor everyChandler Carruth2011-11-141-4/+13
| | | | | | | | | | | | | | | | | | time it is queried to compute the probability of a single successor. This makes computing the probability of every successor of a block in sequence... really really slow. ;] This switches to a linear walk of the successors rather than a quadratic one. One of several quadratic behaviors slowing this pass down. I'm not really thrilled with moving the sum code into the public interface of MBPI, but I don't (at the moment) have ideas for a better interface. My direction I'm thinking in for a better interface is to have MBPI actually retain much more state and make *all* of these queries cheap. That's a lot of work, and would require invasive changes. Until then, this seems like the least bad (ie, least quadratic) solution. Suggestions welcome. llvm-svn: 144530
* Reuse the logic in getEdgeProbability within getHotSucc in order toChandler Carruth2011-11-141-11/+3
| | | | | | | | | | correctly handle blocks whose successor weights sum to more than UINT32_MAX. This is slightly less efficient, but the entire thing is already linear on the number of successors. Calling it within any hot routine is a mistake, and indeed no one is calling it. It also simplifies the code. llvm-svn: 144527
* Fix an overflow bug in MachineBranchProbabilityInfo. This pass relied onChandler Carruth2011-11-141-10/+26
| | | | | | | | | | | | | | | | | | | | | | | | | the sum of the edge weights not overflowing uint32, and crashed when they did. This is generally safe as BranchProbabilityInfo tries to provide this guarantee. However, the CFG can get modified during codegen in a way that grows the *sum* of the edge weights. This doesn't seem unreasonable (imagine just adding more blocks all with the default weight of 16), but it is hard to come up with a case that actually triggers 32-bit overflow. Fortuately, the single-source GCC build is good at this. The solution isn't very pretty, but its no worse than the previous code. We're already summing all of the edge weights on each query, we can sum them, check for an overflow, compute a scale, and sum them again. I've included a *greatly* reduced test case out of the GCC source that triggers it. It's a pretty lame test, as it clearly is just barely triggering the overflow. I'd like to have something that is much more definitive, but I don't understand the fundamental pattern that triggers an explosion in the edge weight sums. The buggy code is duplicated within this file. I'll colapse them into a single implementation in a subsequent commit. llvm-svn: 144526
* Use getVNInfoBefore() when it makes sense.Jakob Stoklund Olesen2011-11-144-8/+7
| | | | llvm-svn: 144517
* Teach machine block placement to cope with unnatural loops. These don'tChandler Carruth2011-11-141-21/+60
| | | | | | | | | | | | | | | | | | get loop info structures associated with them, and so we need some way to make forward progress selecting and placing basic blocks. The technique used here is pretty brutal -- it just scans the list of blocks looking for the first unplaced candidate. It keeps placing blocks like this until the CFG becomes tractable. The cost is somewhat unfortunate, it requires allocating a vector of all basic block pointers eagerly. I have some ideas about how to simplify and optimize this, but I'm trying to get the logic correct first. Thanks to Benjamin Kramer for the reduced test case out of GCC. Sadly there are other bugs that GCC is tickling that I'm reducing and working on now. llvm-svn: 144516
* Use kill slots instead of the previous slot in shrinkToUses.Jakob Stoklund Olesen2011-11-131-13/+14
| | | | | | It's more natural to use the actual end points. llvm-svn: 144515
* Cleanup some 80-columns violations and poor formatting. These snuck byChandler Carruth2011-11-131-5/+9
| | | | | | when I was reading through the code for style. llvm-svn: 144513
* Terminate all dead defs at the dead slot instead of the 'next' slot.Jakob Stoklund Olesen2011-11-133-8/+8
| | | | | | | | | | | | | | | | | | | This makes no difference for normal defs, but early clobber dead defs now look like: [Slot_EarlyClobber; Slot_Dead) instead of: [Slot_EarlyClobber; Slot_Register). Live ranges for normal dead defs look like: [Slot_Register; Slot_Dead) as before. llvm-svn: 144512
* Simplify early clobber slots a bit.Jakob Stoklund Olesen2011-11-131-12/+3
| | | | llvm-svn: 144507
* Enhance the assertion mechanisms in place to make it easier to catchChandler Carruth2011-11-131-5/+28
| | | | | | | | when we fail to place all the blocks of a loop. Currently this is happening for unnatural loops, and this logic helps more immediately point to the problem. llvm-svn: 144504
* Rename SlotIndexes to match how they are used.Jakob Stoklund Olesen2011-11-1313-103/+107
| | | | | | | | | | | | | | | | | | | | The old naming scheme (load/use/def/store) can be traced back to an old linear scan article, but the names don't match how slots are actually used. The load and store slots are not needed after the deferred spill code insertion framework was deleted. The use and def slots don't make any sense because we are using half-open intervals as is customary in C code, but the names suggest closed intervals. In reality, these slots were used to distinguish early-clobber defs from normal defs. The new naming scheme also has 4 slots, but the names match how the slots are really used. This is a purely mechanical renaming, but some of the code makes a lot more sense now. llvm-svn: 144503
* Teach MBP to force-merge layout successors for blocks with unanalyzableChandler Carruth2011-11-131-3/+20
| | | | | | | | | | | | | | | | | branches that also may involve fallthrough. In the case of blocks with no fallthrough, we can still re-order the blocks profitably. For example instruction decoding will in some cases continue past an indirect jump, making laying out its most likely successor there profitable. Note, no test case. I don't know how to write a test case that exercises this logic, but it matches the described desired semantics in discussions with Jakob and others. If anyone has a nice example of IR that will trigger this, that would be lovely. Also note, there are still assertion failures in real world code with this. I'm digging into those next, now that I know this isn't the cause. llvm-svn: 144499
* Hoist another gross nested loop into a helper method.Chandler Carruth2011-11-131-23/+44
| | | | llvm-svn: 144498
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