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* Make SplitAnalysis::UseSlots private.Jakob Stoklund Olesen2012-01-122-6/+10
| | | | llvm-svn: 148031
* Make data structures private.Jakob Stoklund Olesen2012-01-113-11/+17
| | | | llvm-svn: 147979
* Sink spillInterferences into RABasic.Jakob Stoklund Olesen2012-01-113-63/+62
| | | | | | This helper method is too simplistic for RAGreedy. llvm-svn: 147976
* Cleanup.Jakob Stoklund Olesen2012-01-111-9/+0
| | | | llvm-svn: 147975
* Move RegAllocBase into its own cpp file separate from RABasic.Jakob Stoklund Olesen2012-01-113-312/+336
| | | | | | No functional change. llvm-svn: 147972
* On AVX, we can load v8i32 at a time. The bug happens when two uneven loads ↵Nadav Rotem2012-01-111-5/+23
| | | | | | | | | | are used. When we load the v12i32 type, the GenWidenVectorLoads method generates two loads: v8i32 and v4i32 and attempts to use CONCAT_VECTORS to join them. In this fix I concat undef values to widen the smaller value. The test "widen_load-2.ll" also exposes this bug on AVX. llvm-svn: 147964
* Teach the X86 instruction selection to do some heroic transforms toChandler Carruth2012-01-111-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | detect a pattern which can be implemented with a small 'shl' embedded in the addressing mode scale. This happens in real code as follows: unsigned x = my_accelerator_table[input >> 11]; Here we have some lookup table that we look into using the high bits of 'input'. Each entity in the table is 4-bytes, which means this implicitly gets turned into (once lowered out of a GEP): *(unsigned*)((char*)my_accelerator_table + ((input >> 11) << 2)); The shift right followed by a shift left is canonicalized to a smaller shift right and masking off the low bits. That hides the shift right which x86 has an addressing mode designed to support. We now detect masks of this form, and produce the longer shift right followed by the proper addressing mode. In addition to saving a (rather large) instruction, this also reduces stalls in Intel chips on benchmarks I've measured. In order for all of this to work, one part of the DAG needs to be canonicalized *still further* than it currently is. This involves removing pointless 'trunc' nodes between a zextload and a zext. Without that, we end up generating spurious masks and hiding the pattern. llvm-svn: 147936
* Detect when a value is undefined on an edge to a landing pad.Jakob Stoklund Olesen2012-01-111-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consider this code: int h() { int x; try { x = f(); g(); } catch (...) { return x+1; } return x; } The variable x is undefined on the first edge to the landing pad, but it has the f() return value on the second edge to the landing pad. SplitAnalysis::getLastSplitPoint() would assume that the return value from f() was live into the landing pad when f() throws, which is of course impossible. Detect these cases, and treat them as if the landing pad wasn't there. This allows spill code to be inserted after the function call to f(). <rdar://problem/10664933> llvm-svn: 147912
* Exclusively use SplitAnalysis::getLastSplitPoint().Jakob Stoklund Olesen2012-01-113-25/+14
| | | | | | | | | Delete the alternative implementation in LiveIntervalAnalysis. These functions computed the same thing, but SplitAnalysis caches the result. llvm-svn: 147911
* Avoid CSE of instructions which define physical registers across MBBs unlessEvan Cheng2012-01-111-4/+12
| | | | | | the physical registers are not allocatable. llvm-svn: 147902
* 80 col violation.Evan Cheng2012-01-101-2/+2
| | | | llvm-svn: 147884
* Add 'llvm_unreachable' to passify GCC's understanding of the constraintsChandler Carruth2012-01-105-0/+5
| | | | | | | | of several newly un-defaulted switches. This also helps optimizers (including LLVM's) recognize that every case is covered, and we should assume as much. llvm-svn: 147861
* Remove unnecessary default cases in switches that cover all enum values.David Blaikie2012-01-1010-24/+0
| | | | llvm-svn: 147855
* Fix a bug in the legalization of shuffle vectors. When we emulate shuffles ↵Nadav Rotem2012-01-101-1/+3
| | | | | | using BUILD_VECTORS we may be using a BV of different type. Make sure to cast it back. llvm-svn: 147851
* Allow machine-cse to look across MBB boundary when cse'ing instructions thatEvan Cheng2012-01-101-15/+54
| | | | | | | | | | define physical registers. It's currently very restrictive, only catching cases where the CE is in an immediate (and only) predecessor. But it catches a surprising large number of cases. rdar://10660865 llvm-svn: 147827
* Remove the logging streamer.Rafael Espindola2012-01-101-5/+0
| | | | llvm-svn: 147820
* Avoid eraseing copies from a reserved register unless the definition can beEvan Cheng2012-01-081-0/+26
| | | | | | safely proven not to have been clobbered. No small test case possible. llvm-svn: 147751
* Replace some uses of hasNUsesOfValue(0, X) with !hasAnyUseOfValue(X)Craig Topper2012-01-071-4/+4
| | | | llvm-svn: 147733
* Add some DAG combines for SUBC/SUBE. If nothing uses the carry/borrow out of ↵Craig Topper2012-01-071-2/+51
| | | | | | subc, turn it into a sub. Turn (subc x, x) into 0 with no borrow. Turn (subc x, 0) into x with no borrow. Turn (subc -1, x) into (xor x, -1) with no borrow. Turn sube with no borrow in into subc. llvm-svn: 147728
* Optimize reserved register coalescing.Jakob Stoklund Olesen2012-01-071-0/+25
| | | | | | | | | | | | | | | | | Reserved registers don't have proper live ranges, their LiveInterval simply has a snippet of liveness for each def. Virtual registers with a single value that is a copy of a reserved register (typically %esp) can be coalesced with the reserved register if the live range doesn't overlap any reserved register defs. When coalescing with a reserved register, don't modify the reserved register live range. Just leave it as a bunch of dead defs. This eliminates quadratic coalescer behavior in i386 functions with many function calls. PR11699 llvm-svn: 147726
* Use the 'regalloc' debug tag for most register allocator tracing.Jakob Stoklund Olesen2012-01-073-3/+3
| | | | llvm-svn: 147725
* Revert part of r147716. Looks like x87 instructions kill markers are all messedEvan Cheng2012-01-071-9/+11
| | | | | | | | | | up so branch folding pass can't use the scavenger. :-( This doesn't breaks anything currently. It just means targets which do not carefully update kill markers cannot run post-ra scheduler (not new, it has always been the case). We should fix this at some point since it's really hacky. llvm-svn: 147719
* Added a late machine instruction copy propagation pass. This catchesEvan Cheng2012-01-079-38/+274
| | | | | | | | | | | | | | | | | | | | | | | | opportunities that only present themselves after late optimizations such as tail duplication .e.g. ## BB#1: movl %eax, %ecx movl %ecx, %eax ret The register allocator also leaves some of them around (due to false dep between copies from phi-elimination, etc.) This required some changes in codegen passes. Post-ra scheduler and the pseudo-instruction expansion passes have been moved after branch folding and tail merging. They were before branch folding before because it did not always update block livein's. That's fixed now. The pass change makes independently since we want to properly schedule instructions after branch folding / tail duplication. rdar://10428165 rdar://10640363 llvm-svn: 147716
* Missing raw_ostream.h breaks MSVC build.Andrew Trick2012-01-071-0/+1
| | | | llvm-svn: 147703
* Add comment.Chad Rosier2012-01-061-0/+4
| | | | llvm-svn: 147696
* Add a comment and ensure that anyone else looking at this code doesn't startEric Christopher2012-01-061-6/+5
| | | | | | to bleed from the eyes. llvm-svn: 147695
* Use const vector references instead of a vector copy. Spotted by Devang.Eric Christopher2012-01-061-4/+4
| | | | llvm-svn: 147694
* Use -> instead of (*iter).Eric Christopher2012-01-061-10/+10
| | | | llvm-svn: 147693
* Tracing to help investigate issues with SjLj spill code.Andrew Trick2012-01-061-0/+2
| | | | llvm-svn: 147682
* Fix a leak I noticed while reviewing the accelerator table changes. PassesEric Christopher2012-01-061-0/+5
| | | | | | | | lldb testsuite. rdar://10652330 llvm-svn: 147673
* As part of the ongoing work in finalizing the accelerator tables, extendEric Christopher2012-01-065-38/+110
| | | | | | | | | the debug type accelerator tables to contain the tag and a flag stating whether or not a compound type is a complete type. rdar://10652330 llvm-svn: 147651
* Kill ObjectCodeEmitter and BinaryObject, they were unused and superseded by MC.Benjamin Kramer2012-01-052-142/+0
| | | | llvm-svn: 147618
* Remove the old ELF writer.Rafael Espindola2012-01-056-1868/+0
| | | | llvm-svn: 147615
* Remove an unused variable.Chandler Carruth2012-01-051-1/+0
| | | | llvm-svn: 147605
* Prevent a DAGCombine from firing where there are two uses ofChandler Carruth2012-01-051-1/+3
| | | | | | | | | a combined-away node and the result of the combine isn't substantially smaller than the input, it's just canonicalized. This is the first part of a significant (7%) performance gain for Snappy's hot decompression loop. llvm-svn: 147604
* Minor postra scheduler cleanup. It could result in more precise ↵Andrew Trick2012-01-051-25/+19
| | | | | | antidependence latency on ARM in exceedingly rare cases. llvm-svn: 147594
* Freeze reserved registers before starting register allocation.Jakob Stoklund Olesen2012-01-054-0/+7
| | | | | | | | | | | The register allocators don't currently support adding reserved registers while they are running. Extend the MRI API to keep track of the set of reserved registers when register allocation started. Target hooks like hasFP() and needsStackRealignment() can look at this set to avoid reserving more registers during register allocation. llvm-svn: 147577
* Allow vector shuffle normalizing to use concat vector even if the sources ↵Craig Topper2012-01-041-11/+24
| | | | | | are commuted in the shuffle mask. llvm-svn: 147527
* Implement VECTOR_SHUFFLE canonicalizations during DAG combine.Craig Topper2012-01-041-2/+50
| | | | llvm-svn: 147525
* Turn a few more inline asm errors into "emitErrors" instead of fatal errors.Chris Lattner2012-01-031-9/+21
| | | | | | | | | | | | | | | | | | Before we'd get: $ clang t.c fatal error: error in backend: Invalid operand for inline asm constraint 'i'! Now we get: $ clang t.c t.c:16:5: error: invalid operand for inline asm constraint 'i'! "movq (%4), %%mm0\n" ^ Which at least gets us the inline asm that is the problem. llvm-svn: 147502
* Assert when reserved registers have been assigned.Jakob Stoklund Olesen2012-01-031-0/+4
| | | | | | | | | This can only happen if the set of reserved registers changes during register allocation. <rdar://problem/10625436> llvm-svn: 147486
* Fix incorrect widening of the bitcast sdnode in case the incoming operand is ↵Nadav Rotem2012-01-031-0/+6
| | | | | | integer-promoted. llvm-svn: 147484
* Remove the restriction that target intrinsics can only involve legal types. ↵Owen Anderson2012-01-031-8/+0
| | | | | | Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization. For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's. ARM already does some expansions like this for non-intrinsic operations. llvm-svn: 147472
* Clarified assert text.Lang Hames2012-01-031-1/+1
| | | | llvm-svn: 147471
* Fix typo in ruler. No functionality change.Nick Lewycky2012-01-031-1/+1
| | | | llvm-svn: 147454
* Fixed a bug in SelectionDAG.cpp.Elena Demikhovsky2012-01-031-6/+50
| | | | | | | | | | | | The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. llvm-svn: 147445
* Revert 147399. It broke CodeGen/ARM/vext.ll.Rafael Espindola2012-01-011-39/+5
| | | | llvm-svn: 147400
* Fixed a bug in SelectionDAG.cpp.Elena Demikhovsky2012-01-011-5/+39
| | | | | | | | | | | | The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. llvm-svn: 147399
* PR11662.Nadav Rotem2011-12-281-1/+5
| | | | | | Promotion of the mask operand needs to be done using PromoteTargetBoolean, and not padded with garbage. llvm-svn: 147309
* Make sure DAGCombiner doesn't introduce multiple loads from the same memory ↵Eli Friedman2011-12-261-1/+23
| | | | | | location. PR10747, part 2. llvm-svn: 147283
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