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* [ms-inline asm] We only need one bit to represent the AsmDialect in theChad Rosier2012-09-052-11/+5
| | | | | | MachineInstr. llvm-svn: 163257
* Constify this properly. Found by gcc48 -Wcast-qual.Roman Divacky2012-09-051-4/+4
| | | | llvm-svn: 163256
* Constify SDNodeIterator an stop its only non-const user being cast strippedRoman Divacky2012-09-051-1/+1
| | | | | | of its constness. Found by gcc48 -Wcast-qual. llvm-svn: 163254
* [ms-inline asm] Propagate the asm dialect into the MachineInstr representation.Chad Rosier2012-09-052-1/+19
| | | | llvm-svn: 163243
* Remove unused typedefs gcc4.8 warns about.Roman Divacky2012-09-051-1/+0
| | | | llvm-svn: 163225
* Fixed the DAG combiner to better handle the folding of AND nodes for vector ↵Silviu Baranga2012-09-051-1/+11
| | | | | | types. The previous code was making the assumption that the length of the bitmask returned by isConstantSplat was equal to the size of the vector type. Now we first make sure that the splat value has at least the length of the vector lane type, then we only use as many fields as we have available in the splat value. llvm-svn: 163203
* Reorder the comments of EmitExceptionTable.Logan Chien2012-09-051-20/+20
| | | | llvm-svn: 163194
* Convert vextracti128/vextractf128 intrinsics to extract_subvector at DAG ↵Craig Topper2012-09-051-1/+15
| | | | | | build time. Similar was previously done for vinserti128/vinsertf128. Add patterns for folding these extract_subvectors with stores. llvm-svn: 163192
* Search the whole instruction for tied operands.Jakob Stoklund Olesen2012-09-041-2/+1
| | | | | | | Implicit uses can be dynamically tied to defs. This will soon be used for predicated instructions on ARM. llvm-svn: 163177
* Typo.Jakob Stoklund Olesen2012-09-041-1/+1
| | | | llvm-svn: 163154
* Actually use the MachineOperand field for isRegTiedToDefOperand().Jakob Stoklund Olesen2012-09-041-103/+0
| | | | | | | | | | The MachineOperand::TiedTo field was maintained, but not used. This patch enables it in isRegTiedToDefOperand() and isRegTiedToUseOperand() which are the actual functions use by the register allocator. llvm-svn: 163153
* Move tie checks into MachineVerifier::visitMachineOperand.Jakob Stoklund Olesen2012-09-041-36/+26
| | | | llvm-svn: 163152
* Allow tied uses and defs in different orders.Jakob Stoklund Olesen2012-09-041-30/+91
| | | | | | | | | | | | | | | | After much agonizing, use a full 4 bits of precious MachineOperand space to encode this. This uses existing padding, and doesn't grow MachineOperand beyond its current 32 bytes. This allows tied defs among the first 15 operands on a normal instruction, just like the current MCInstrDesc constraint encoding. Inline assembly needs to be able to tie more than the first 15 operands, and gets special treatment. Tied uses can appear beyond 15 operands, as long as they are tied to a def that's in range. llvm-svn: 163151
* Generic Bypass Slow DivPreston Gurd2012-09-041-1/+0
| | | | | | | | | | | | | | | | | | | | | | | - CodeGenPrepare pass for identifying div/rem ops - Backend specifies the type mapping using addBypassSlowDivType - Enabled only for Intel Atom with O2 32-bit -> 8-bit - Replace IDIV with instructions which test its value and use DIVB if the value is positive and less than 256. - In the case when the quotient and remainder of a divide are used a DIV and a REM instruction will be present in the IR. In the non-Atom case they are both lowered to IDIVs and CSE removes the redundant IDIV instruction, using the quotient and remainder from the first IDIV. However, due to this optimization CSE is not able to eliminate redundant IDIV instructions because they are located in different basic blocks. This is overcome by calculating both the quotient (DIV) and remainder (REM) in each basic block that is inserted by the optimization and reusing the result values when a subsequent DIV or REM instruction uses the same operands. - Test cases check for the presents of the optimization when calculating either the quotient, remainder, or both. Patch by Tyler Nowicki! llvm-svn: 163150
* IRBuilderify the SjlLjEHPrepare pass.Benjamin Kramer2012-09-031-57/+25
| | | | | | No functionality change. llvm-svn: 163115
* When updating live range endpoints, make sure to preserve the early clobber bit.Lang Hames2012-09-031-2/+2
| | | | | | Fixs PR13719. llvm-svn: 163107
* Fix a typo.Nadav Rotem2012-09-021-1/+1
| | | | llvm-svn: 163094
* Generate better select code by allowing the target to use scalar select, and ↵Nadav Rotem2012-09-021-4/+3
| | | | | | not sign-extend. llvm-svn: 163086
* Only legalise a VSELECT in to bitwise operations if the vector mask bool is ↵Pete Cooper2012-09-011-1/+6
| | | | | | | | | zeros or all ones. A vector bool with just ones isn't suitable for masking with. No test case unfortunately as i couldn't find a target which fit all the conditions needed to hit this code. llvm-svn: 163075
* Revert "Take account of boolean vector contents when promoting a build ↵Pete Cooper2012-09-011-17/+1
| | | | | | | | | | | | | | vector from i1 to some other type. rdar://problem/12210060" This reverts commit 5dd9e214fb92847e947f9edab170f9b4e52b908f. Thanks to Duncan for explaining how this should have been done. Conflicts: test/CodeGen/X86/vec_select.ll llvm-svn: 163064
* Fix typo.Logan Chien2012-09-011-1/+1
| | | | llvm-svn: 163059
* Teach DAG combine a number of tricks to simplify FMA expressions in ↵Owen Anderson2012-09-011-0/+64
| | | | | | fast-math mode. llvm-svn: 163051
* Fix typoMichael Liao2012-09-011-1/+1
| | | | llvm-svn: 163049
* Add MachineInstr::tieOperands, remove setIsTied().Jakob Stoklund Olesen2012-08-312-12/+18
| | | | | | | | | | | Manage tied operands entirely internally to MachineInstr. This makes it possible to change the representation of tied operands, as I will do shortly. The constraint that tied uses and defs must be in the same order was too restrictive. llvm-svn: 163021
* Use CloneMachineInstr to make a new MI in commuteInstruction to make the ↵Craig Topper2012-08-311-10/+1
| | | | | | code tolerant of instructions with more than two input operands. llvm-svn: 163000
* Don't enforce ordered inline asm operands.Jakob Stoklund Olesen2012-08-311-10/+0
| | | | | | | | | I was too optimistic, inline asm can have tied operands that don't follow the def order. Fixes PR13742. llvm-svn: 162998
* Take account of boolean vector contents when promoting a build vector from ↵Pete Cooper2012-08-301-1/+17
| | | | | | i1 to some other type. rdar://problem/12210060 llvm-svn: 162960
* Teach the DAG combiner to turn chains of FADDs (x+x+x+x+...) into FMULs by ↵Owen Anderson2012-08-301-1/+122
| | | | | | constants. This is only enabled in unsafe FP math mode, since it does not preserve rounding effects for all such constants. llvm-svn: 162956
* Currently targets that do not support selects with scalar conditions and ↵Nadav Rotem2012-08-301-1/+65
| | | | | | | | | | | vector operands - scalarize the code. ARM is such a target because it does not support CMOV of vectors. To implement this efficientlyi, we broadcast the condition bit and use a sequence of NAND-OR to select between the two operands. This is the same sequence we use for targets that don't have vector BLENDs (like SSE2). rdar://12201387 llvm-svn: 162926
* Don't use MCInstrDesc flags for implicit operands.Jakob Stoklund Olesen2012-08-301-11/+16
| | | | | | | | | | | | | When a MachineInstr is constructed, its implicit operands are added first, then the explicit operands are inserted before the implicits. MCInstrDesc has oprand flags like early clobber and operand ties that apply to the explicit operands. Don't look at those flags when the implicit operands are first added in the explicit operands's positions. llvm-svn: 162910
* Add FMA to switch statement in VectorLegalizer::LegalizeOp so that it can be ↵Craig Topper2012-08-301-0/+1
| | | | | | expanded when it isn't legal. llvm-svn: 162894
* Add support for FMA to WidenVectorResult.Craig Topper2012-08-302-0/+14
| | | | llvm-svn: 162893
* Verify the order of tied operands in inline asm.Jakob Stoklund Olesen2012-08-291-0/+12
| | | | | | | | | | | | | | When there are multiple tied use-def pairs on an inline asm instruction, the tied uses must appear in the same order as the defs. It is possible to write an LLVM IR inline asm instruction that breaks this constraint, but there is no reason for a front end to emit the operands out of order. The gnu inline asm syntax specifies tied operands as a single read/write constraint "+r", so ouf of order operands are not possible. llvm-svn: 162878
* Set the isTied flags when building INLINEASM MachineInstrs.Jakob Stoklund Olesen2012-08-291-4/+21
| | | | | | | | For normal instructions, isTied() is set automatically by addOperand(), based on MCInstrDesc, but inline asm has tied operands outside the descriptor. llvm-svn: 162869
* Rename hasVolatileMemoryRef() to hasOrderedMemoryRef().Jakob Stoklund Olesen2012-08-292-9/+9
| | | | | | | | Ordered memory operations are more constrained than volatile loads and stores because they must be ordered with respect to all other memory operations. llvm-svn: 162861
* Don't move normal loads across volatile/atomic loads.Jakob Stoklund Olesen2012-08-291-3/+8
| | | | | | | | | | | | | It is technically allowed to move a normal load across a volatile load, but probably not a good idea. It is not allowed to move a load across an atomic load with Ordering > Monotonic, and we model those with MOVolatile as well. I recently removed the mayStore flag from atomic load instructions, so they don't need a pseudo-opcode. This patch makes up for the difference. llvm-svn: 162857
* Verify the consistency of inline asm operands.Jakob Stoklund Olesen2012-08-291-16/+72
| | | | | | | | | | The operands on an INLINEASM machine instruction are divided into groups headed by immediate flag operands. Verify this structure. Extract verifyTiedOperands(), and only call it for non-inlineasm instructions. llvm-svn: 162849
* Clean this up slightly, doesn't really fall through.Eric Christopher2012-08-291-2/+1
| | | | llvm-svn: 162848
* Verify the tied operand flags.Jakob Stoklund Olesen2012-08-291-0/+37
| | | | | | | | WHen running with -verify-machineinstrs, check that tied operands come in matching use/def pairs, and that they are consistent with MCInstrDesc when it applies. llvm-svn: 162816
* Maintain a vaild isTied bit as operands are added and removed.Jakob Stoklund Olesen2012-08-291-1/+39
| | | | | | | | The isTied bit is set automatically when a tied use is added and MCInstrDesc indicates a tied operand. The tie is broken when one of the tied operands is removed. llvm-svn: 162814
* Add a MachineOperand::isTied() flag.Jakob Stoklund Olesen2012-08-281-21/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While in SSA form, a MachineInstr can have pairs of tied defs and uses. The tied operands are used to represent read-modify-write operands that must be assigned the same physical register. Previously, tied operand pairs were computed from fixed MCInstrDesc fields, or by using black magic on inline assembly instructions. The isTied flag makes it possible to add tied operands to any instruction while getting rid of (some of) the inlineasm magic. Tied operands on normal instructions are needed to represent predicated individual instructions in SSA form. An extra <tied,imp-use> operand is required to represent the output value when the instruction predicate is false. Adding a predicate to: %vreg0<def> = ADD %vreg1, %vreg2 Will look like: %vreg0<tied,def> = ADD %vreg1, %vreg2, pred:3, %vreg7<tied,imp-use> The virtual register %vreg7 is the value given to %vreg0 when the predicate is false. It will be assigned the same physreg as %vreg0. This commit adds the isTied flag and sets it based on MCInstrDesc when building an instruction. The flag is not used for anything yet. llvm-svn: 162774
* Don't allow TargetFlags on MO_Register MachineOperands.Jakob Stoklund Olesen2012-08-281-2/+2
| | | | | | | | | | | | Register operands are manipulated by a lot of target-independent code, and it is not always possible to preserve target flags. That means it is not safe to use target flags on register operands. None of the targets in the tree are using register operand target flags. External targets should be using immediate operands to annotate instructions with operand modifiers. llvm-svn: 162770
* Remove extra MayLoad/MayStore flags from atomic_load/store.Jakob Stoklund Olesen2012-08-281-18/+23
| | | | | | | | | | | | | | | These extra flags are not required to properly order the atomic load/store instructions. SelectionDAGBuilder chains atomics as if they were volatile, and SelectionDAG::getAtomic() sets the isVolatile bit on the memory operands of all atomic operations. The volatile bit is enough to order atomic loads and stores during and after SelectionDAG. This means we set mayLoad on atomic_load, mayStore on atomic_store, and mayLoad+mayStore on the remaining atomic read-modify-write operations. llvm-svn: 162733
* Fix bug 13532.Akira Hatanaka2012-08-281-1/+1
| | | | | | | | | In SelectionDAGLegalize::ExpandLegalINT_TO_FP, expand INT_TO_FP nodes without using any f64 operations if f64 is not a legal type. Patch by Stefan Kristiansson. llvm-svn: 162728
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-242-7/+5
| | | | | | Reviewed offline by chandlerc. llvm-svn: 162623
* Avoid including explicit uses when counting SDNode imp-uses.Jakob Stoklund Olesen2012-08-241-3/+6
| | | | | | | It is legal to have a register node as an explicit operand, it shouldn't be counted as an implicit use. llvm-svn: 162591
* BranchProb: modify the definition of an edge in BranchProbabilityInfo to handleManman Ren2012-08-243-28/+60
| | | | | | | | | | | | | | the case of multiple edges from one block to another. A simple example is a switch statement with multiple values to the same destination. The definition of an edge is modified from a pair of blocks to a pair of PredBlock and an index into the successors. Also set the weight correctly when building SelectionDAG from LLVM IR, especially when converting a Switch. IntegersSubsetMapping is updated to calculate the weight for each cluster. llvm-svn: 162572
* Use DW_FORM_flag_present to save space in debug information if we'reEric Christopher2012-08-244-25/+41
| | | | | | | | not in darwin gdb compat mode. Fixes rdar://10975088 llvm-svn: 162526
* Remove the DW_AT_MIPS_linkage name attribute when we don't need itEric Christopher2012-08-231-1/+8
| | | | | | | | | | | output (we're emitting a specification already and the information isn't changing) and we're not in old gdb compat mode. Saves 1% on the debug information for a build of llvm. Fixes rdar://11043421 llvm-svn: 162493
* Turn these two options in to trinary state so that they can beEric Christopher2012-08-232-15/+42
| | | | | | turned on and off separate from the platform if you're on darwin. llvm-svn: 162487
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