summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
...
* Use the new getRegAllocationHints() hook from AllocationOrder.Jakob Stoklund Olesen2012-12-032-79/+49
| | | | | | | This simplifies the hinting code quite a bit while making the targets easier to write at the same time. llvm-svn: 169173
* moves doInitialization and doFinalization to the Pass class and removes some ↵Pedro Artigas2012-12-031-15/+0
| | | | | | | | unreachable code in MachineModuleInfo reviewed by Evan Cheng <evan.cheng@apple.com> llvm-svn: 169164
* Add a new hook for providing register allocator hints more flexibly.Jakob Stoklund Olesen2012-12-031-0/+38
| | | | | | | | | | | | | | | | | | The TargetRegisterInfo::getRegAllocationHints() function is going to replace the existing mechanisms for providing target-dependent hints to the register allocator: ResolveRegAllocHint() and getRawAllocationOrder(). The new hook is more flexible because it allows the target to provide multiple preferred candidate registers for each virtual register, and it is easier to use because targets are not required to return a reference to a constant array like getRawAllocationOrder(). An optional VirtRegMap argument can be used to provide target-dependent hints that depend on the provisional assignments of other virtual registers. llvm-svn: 169154
* Fix PR12942: Allow two CUs to be generated from the same source file.Eli Bendersky2012-12-034-24/+33
| | | | | | Thanks Eric for the review. llvm-svn: 169142
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-03113-689/+682
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Allow merging multiple store sequences on the same chain.Nadav Rotem2012-12-021-2/+15
| | | | llvm-svn: 169111
* misched: Fix RegisterPressureTracker handling of DebugVals.Andrew Trick2012-12-013-19/+25
| | | | | | | Assertion failed: (TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker"). rdar://12790302. llvm-svn: 169072
* misched: Fix the DAG builder to handle an undef operand at ExitSU.Andrew Trick2012-12-011-1/+2
| | | | | | | Assertion failed: (VNI && "No value to read by operand") rdar://12790267. llvm-svn: 169071
* misched: Fix LiveInterval update to better handle DebugVal.Andrew Trick2012-12-011-1/+5
| | | | | | | Assertion failed: (itr != mi2iMap.end() && "Instruction not found in maps.") rdar://12777252. llvm-svn: 169070
* misched: fix RegionBegin when DebugValues get shuffled to the top.Andrew Trick2012-12-011-0/+2
| | | | | | | | assert (RemainingInstrs == 0 && "Instruction count mismatch!") rdar://12776937. llvm-svn: 169069
* Simplify REG_SEQUENCE lowering.Jakob Stoklund Olesen2012-12-011-187/+69
| | | | | | | | | | | The TwoAddressInstructionPass takes the machine code out of SSA form by expanding REG_SEQUENCE instructions into copies. It is no longer necessary to rewrite the registers used by a REG_SEQUENCE instruction because the new coalescer algorithm can do it now. REG_SEQUENCE is just converted to a sequence of sub-register copies now. llvm-svn: 169067
* Add some first skeleton work for the DWARF5 Fission proposal. EmitEric Christopher2012-11-302-8/+119
| | | | | | | | | part of the compile unit CU and start separating out information into the various sections that will be pulled out later. WIP. llvm-svn: 169061
* Convert COPY instructions into KILLs if they have implicit defs.Jakob Stoklund Olesen2012-11-301-3/+17
| | | | | | | | | | | MachineCopyPropagation doesn't understand super-register liveness well enough to be able to remove implicit defs of super-registers. This fixes a problem in ARM/2012-01-26-CopyPropKills.ll that is exposed by an future TwoAddressInstructionPass change. The KILL instructions are removed before the machine code is emitted. llvm-svn: 169060
* Replace r168930 with a more reasonable patch.Bill Wendling2012-11-302-3/+9
| | | | | | | | | | | The original patch removed a bunch of code that the SjLjEHPrepare pass placed into the entry block if all of the landing pads were removed during the CodeGenPrepare class. The more natural way of doing things is to run the CGP *before* we run the SjLjEHPrepare pass. Make it so! llvm-svn: 169044
* More comment.Eric Christopher2012-11-291-0/+2
| | | | llvm-svn: 168952
* Cleanup recent addition of DAGTypeLegalizer::SplitVecOp_VSELECTJustin Holewinski2012-11-291-35/+31
| | | | llvm-svn: 168932
* misched: Recompute priority queue when DFSResults are updated.Benjamin Kramer2012-11-291-0/+2
| | | | | | | | This was found by MSVC10's STL debug mode on a test from the test suite. Sadly std::is_heap isn't standard so there is no way to assert this without writing our own heap verify, which looks like overkill to me. llvm-svn: 168885
* Teach the legalizer how to handle operands for VSELECT nodesJustin Holewinski2012-11-292-1/+60
| | | | | | | If we need to split the operand of a VSELECT, it must be the mask operand. We split the entire VSELECT operand with EXTRACT_SUBVECTOR. llvm-svn: 168883
* Allow targets to prefer TypeSplitVector over TypePromoteInteger when ↵Justin Holewinski2012-11-291-1/+1
| | | | | | | | computing the legalization method for vectors For some targets, it is desirable to prefer scalarizing <N x i1> instead of promoting to a larger legal type, such as <N x i32>. llvm-svn: 168882
* Use MCPhysReg for RegisterClassInfo allocation orders.Jakob Stoklund Olesen2012-11-296-15/+17
| | | | | | This saves a bit of memory. llvm-svn: 168852
* Avoid rewriting instructions twice.Jakob Stoklund Olesen2012-11-291-0/+9
| | | | | | | | | This could cause miscompilations in targets where sub-register composition is not always idempotent (ARM). <rdar://problem/12758887> llvm-svn: 168837
* When combining consecutive stores allow loads in between the stores, if the ↵Nadav Rotem2012-11-291-3/+61
| | | | | | loads do not alias. llvm-svn: 168832
* Make the LiveRegMatrix analysis available to targets.Jakob Stoklund Olesen2012-11-2820-564/+21
| | | | | | | | | | | No functional change, just moved header files. Targets can inject custom passes between register allocation and rewriting. This makes it possible to tweak the register allocation before rewriting, using the full global interference checking available from LiveRegMatrix. llvm-svn: 168806
* misched: Analysis that partitions the DAG into subtrees.Andrew Trick2012-11-282-56/+222
| | | | | | | | | | | This is a simple, cheap infrastructure for analyzing the shape of a DAG. It recognizes uniform DAGs that take the shape of bottom-up subtrees, such as the included matrix multiplication example. This is useful for heuristics that balance register pressure with ILP. Two canonical expressions of the heuristic are implemented in scheduling modes: -misched-ilpmin and -misched-ilpmax. llvm-svn: 168773
* misched: rename ScheduleDAGILP to ScheduleDFS to prepare for other heuristics.Andrew Trick2012-11-282-2/+2
| | | | llvm-svn: 168772
* misched: better alias analysis.Andrew Trick2012-11-281-2/+3
| | | | | | | | | | | | | This fixes a hole in the "cheap" alias analysis logic implemented within the DAG builder itself, regardless of whether proper alias analysis is enabled. It now handles this pattern produced by LSR+CodeGenPrepare. %sunkaddr1 = ptrtoint * %obj to i64 %sunkaddr2 = add i64 %sunkaddr1, %lsr.iv %sunkaddr3 = inttoptr i64 %sunkaddr2 to i32* store i32 %v, i32* %sunkaddr3 llvm-svn: 168768
* misched: Debug output fix. Use an always valid iterator.Andrew Trick2012-11-281-1/+1
| | | | llvm-svn: 168767
* Move the guts of TargetInstrInfoImpl into the TargetInstrInfo class.Jakob Stoklund Olesen2012-11-283-691/+659
| | | | | | | The *Impl class no longer serves a purpose now that the super-class implementation is in CodeGen. llvm-svn: 168759
* Move Target{Instr,Register}Info.cpp into lib/CodeGen.Jakob Stoklund Olesen2012-11-283-0/+338
| | | | | | | | | | | | | | | | The Target library is not allowed to depend on the large CodeGen library, but the TRI and TII classes provide abstract interfaces that require both caller and callee to link to CodeGen. The implementation files for these classes provide default implementations of some of the hooks. These methods may need to reference CodeGen, so they belong in that library. We already have a number of methods implemented in the TargetInstrInfoImpl sub-class because of that. I will merge that class into the parent next. llvm-svn: 168758
* Revert r168630, r168631, and r168633 as these are causing nightly test failures.Chad Rosier2012-11-284-2/+4
| | | | llvm-svn: 168751
* Attempt to make the comments for dwarf debug look more likeEric Christopher2012-11-272-274/+200
| | | | | | the coding standard would like. llvm-svn: 168737
* Reapply section moving, make sure string section is output last.Eric Christopher2012-11-271-24/+54
| | | | llvm-svn: 168736
* CSE: allow PerformTrivialCoalescing to check copies across basic blockManman Ren2012-11-271-2/+0
| | | | | | | | | | | | | | | | boundaries. Given the following case: BB0 %vreg1<def> = SUBrr %vreg0, %vreg7 %vreg2<def> = COPY %vreg7 BB1 %vreg10<def> = SUBrr %vreg0, %vreg2 We should be able to CSE between SUBrr in BB0 and SUBrr in BB1. rdar://12462006 llvm-svn: 168717
* Remove duplicated #includes.Jakub Staszak2012-11-271-4/+0
| | | | llvm-svn: 168712
* Never use .lcomm on platforms where it does not accept an alignmentUlrich Weigand2012-11-271-2/+7
| | | | | | | | | | | argument. Instead, use a pair of .local and .comm directives. This avoids spurious differences between binaries built by the integrated assembler vs. those built by the external assembler, since the external assembler may impose alignment requirements on .lcomm symbols where the integrated assembler does not. llvm-svn: 168704
* Revert rearrangement of debug info sections to unblock the botsEric Christopher2012-11-271-59/+26
| | | | | | and O0 + debug codegen. llvm-svn: 168680
* Remove unneeded #include.Jakub Staszak2012-11-271-1/+0
| | | | llvm-svn: 168670
* Remove unneeded #include.Jakub Staszak2012-11-271-1/+0
| | | | llvm-svn: 168664
* llvm/CodeGen: Remove empty files in r168659.NAKAMURA Takumi2012-11-271-0/+0
| | | | llvm-svn: 168663
* Remove unused forward declaration.Jakub Staszak2012-11-271-1/+0
| | | | llvm-svn: 168660
* Remove unused MachineLoopRanges analysis.Jakub Staszak2012-11-274-149/+0
| | | | llvm-svn: 168659
* Make comment names match function names.Eric Christopher2012-11-271-3/+3
| | | | llvm-svn: 168644
* Add in sections for the fission case (no change so incorrect) andEric Christopher2012-11-271-1/+32
| | | | | | add a TODO for starting. llvm-svn: 168643
* Reorder section output ordering.Eric Christopher2012-11-271-25/+27
| | | | llvm-svn: 168638
* Whitespace cleanup.Eric Christopher2012-11-271-27/+27
| | | | llvm-svn: 168637
* Add an assertion to ensure freezeReservedRegs() is only ever called once.Chad Rosier2012-11-261-0/+2
| | | | llvm-svn: 168633
* Now that the X86 Maximal Stack Alignment Check pass has been removed (i.e.,Chad Rosier2012-11-262-3/+0
| | | | | | | | | r168627), we no longer need to call the freezeReservedRegs() function a second time. Previously, this pass was conservatively adding the FP to the set of reserved registers, requiring the second update to the reserved registers. rdar://12719844 llvm-svn: 168631
* Now that the X86 Maximal Stack Alignment Check pass has been removed (i.e.,Chad Rosier2012-11-261-1/+0
| | | | | | | | | r168627), we no longer need to call the freezeReservedRegs() function a second time. Previously, this pass was conservatively adding the FP to the set of reserved registers, requiring the second update to the reserved registers. rdar://12719844 llvm-svn: 168630
* Don't use iterator after being erased.Jakub Staszak2012-11-261-1/+1
| | | | llvm-svn: 168622
* Remove unneeded #includes.Jakub Staszak2012-11-261-4/+0
| | | | llvm-svn: 168608
OpenPOWER on IntegriCloud