summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
* DebugInfo: Do not use DW_FORM_GNU_addr_index in skeleton CUs, GDB 7.8 errors ↵David Blaikie2014-09-071-1/+1
| | | | | | | | | | on this. It's probably not a huge deal to not do this - if we could, maybe the address could be reused by a subprogram low_pc and avoid an extra relocation, but it's just one per CU at best. llvm-svn: 217338
* Allow vector fsub ops with constants to get the same optimizations as scalars.Sanjay Patel2014-09-051-2/+2
| | | | | | | | This problem is bigger than just fsub, but this is the minimum fix to solve fneg for PR20556 ( http://llvm.org/bugs/show_bug.cgi?id=20556 ), and we solve zero subtraction with the same change. llvm-svn: 217286
* clean up; NFCSanjay Patel2014-09-051-2/+2
| | | | llvm-svn: 217278
* Revert "Disable the fix for pr20793 because of a gnu ld bug."Rafael Espindola2014-09-051-11/+0
| | | | | | | | | | This reverts commit r217211. Both the bfd ld and gold outputs were valid. They were using a Rela relocation, so the value present in the relocated location was not used, which caused me to misread the output. llvm-svn: 217264
* Set the parent pointer of cloned DBG_VALUE instructions correctly.Adrian Prantl2014-09-051-1/+1
| | | | | | | | | | | | | | | | | | Fixes PR20523. When spilling variables onto the stack, spillVirtReg() is setting the parent pointer of the cloned DBG_VALUE intrinsic for the stack location to the parent pointer of the original intrinsic. MachineInstr parent pointers should however always point to the parent basic block. MBB is shadowing the MBB member variable. The instruction still ends up being inserted into the right basic block, because it's inserted after MI which serves as the iterator. I failed at constructing a reliable testcase for this, see http://llvm.org/bugs/show_bug.cgi?id=20523 for a large testcases. llvm-svn: 217260
* Disable the fix for pr20793 because of a gnu ld bug.Rafael Espindola2014-09-051-0/+11
| | | | llvm-svn: 217211
* Refactor to avoid code duplication. NFC.Rafael Espindola2014-09-051-34/+25
| | | | llvm-svn: 217207
* Fix pr20793.Rafael Espindola2014-09-041-24/+48
| | | | | | With this patch the third field of llvm.global_ctors is also used on ELF. llvm-svn: 217202
* MC Win64: Put unwind info for COMDAT code into the same COMDAT groupReid Kleckner2014-09-041-19/+4
| | | | | | | | | | | | | | | | | Summary: This fixes a long standing issue where we would emit many little .text sections and only one .pdata and .xdata section. Now we generate one .pdata / .xdata pair per .text section and associate them correctly. Fixes PR19667. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5181 llvm-svn: 217176
* Revert r216803 "[MachineSinking] Clear kill flag of all operands at all ↵Juergen Ributzka2014-09-041-13/+3
| | | | | | | | | their uses." This reverts commit r216803, because it might have broken the buildbot. The issue is tracked in PR20842. llvm-svn: 217120
* Refactor AtomicExpandPass and add a generic isAtomic() method to InstructionRobin Morisset2014-09-031-30/+31
| | | | | | | | | | | | | | | | | | | | | Summary: Split shouldExpandAtomicInIR() into different versions for Stores/Loads/RMWs/CmpXchgs. Makes runOnFunction cleaner (no more redundant checking/casting), and will help moving the X86 backend to this pass. This requires a way of easily detecting which instructions are atomic. I followed the pattern of mayReadFromMemory, mayWriteOrReadMemory, etc.. in making isAtomic() a method of Instruction implemented by a switch on the opcodes. Test Plan: make check Reviewers: jfb Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D5035 llvm-svn: 217080
* Use target-dependent emitLeading/TrailingFence instead of the ↵Robin Morisset2014-09-031-51/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | target-independent insertLeading/TrailingFence (in AtomicExpandPass) Fixes two latent bugs: - There was no fence inserted before expanded seq_cst load (unsound on Power) - There was only a fence release before seq_cst stores (again unsound, in particular on Power) It is not even clear if this is correct on ARM swift processors (where release fences are DMB ishst instead of DMB ish). This behaviour is currently preserved on ARM Swift as it is not clear whether it is incorrect. I would love to get documentation stating whether it is correct or not. These two bugs were not triggered because Power is not (yet) using this pass, and these behaviours happen to be (mostly?) working on ARM (although they completely butchered the semantics of the llvm IR). See: http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-August/075821.html for an example of the problems that can be caused by the second of these bugs. I couldn't see a way of fixing these in a completely target-independent way without adding lots of unnecessary fences on ARM, hence the target-dependent parts of this patch. This patch implements the new target-dependent parts only for ARM (the default of not doing anything is enough for AArch64), other architectures will use this infrastructure in later patches. llvm-svn: 217076
* [FastISel][tblgen] Rename tblgen generated FastISel functions. NFC.Juergen Ributzka2014-09-031-50/+50
| | | | | | | | | | This is the final round of renaming. This changes tblgen to emit lower-case function names for FastEmitInst_* and FastEmit_*, and updates all its uses in the source code. Reviewed by Eric llvm-svn: 217075
* [FastISel] Rename public visible FastISel functions. NFC.Juergen Ributzka2014-09-032-46/+44
| | | | | | | | | | | | | | | | | | | | | This commit renames the following public FastISel functions: LowerArguments -> lowerArguments SelectInstruction -> selectInstruction TargetSelectInstruction -> fastSelectInstruction FastLowerArguments -> fastLowerArguments FastLowerCall -> fastLowerCall FastLowerIntrinsicCall -> fastLowerIntrinsicCall FastEmitZExtFromI1 -> fastEmitZExtFromI1 FastEmitBranch -> fastEmitBranch UpdateValueMap -> updateValueMap TargetMaterializeConstant -> fastMaterializeConstant TargetMaterializeAlloca -> fastMaterializeAlloca TargetMaterializeFloatZero -> fastMaterializeFloatZero LowerCallTo -> lowerCallTo Reviewed by Eric llvm-svn: 217074
* Remove resetSubtargetFeatures as it is unused.Eric Christopher2014-09-031-3/+0
| | | | llvm-svn: 217071
* [FastISel] Some long overdue spring cleaning of FastISel.Juergen Ributzka2014-09-031-378/+333
| | | | | | | | | | | | | Things got a little bit messy over the years and it is time for a little bit spring cleaning. This first commit is focused on the FastISel base class itself. It doxyfies all comments, C++11fies the code where it makes sense, renames internal methods to adhere to the coding standard, and clang-formats the files. Reviewed by Eric llvm-svn: 217060
* Reinstate "Nuke the old JIT."Eric Christopher2014-09-026-42/+4
| | | | | | | | Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reinstates commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 216982
* Add pass-manager flags to use CFL AAHal Finkel2014-09-021-0/+6
| | | | | | | Add -use-cfl-aa (and -use-cfl-aa-in-codegen) to add CFL AA in the default pass managers (for easy testing). llvm-svn: 216978
* [FastISel] Provide the option to skip target-independent instruction ↵Juergen Ributzka2014-09-021-18/+24
| | | | | | | | | | | | | selection. NFC. This allows the target to disable target-independent instruction selection and jump directly into the target-dependent instruction selection code. This can be beneficial for targets, such as AArch64, which could emit much better code, but never got a chance to do so, because the target-independent instruction selector was able to find an instruction sequence. llvm-svn: 216947
* Fix interference caused by fmul 2, x -> fadd x, xMatt Arsenault2014-09-021-8/+21
| | | | | | | | If an fmul was introduced by lowering, it wouldn't be folded into a multiply by a constant since the earlier combine would have replaced the fmul with the fadd. llvm-svn: 216932
* CodeGen: Handle va_start in the entry blockReid Kleckner2014-09-021-24/+16
| | | | | | | | | Also fix a small copy-paste bug in X86ISelLowering where Chain should have been used in place of DAG.getEntryToken(). Fixes PR20828. llvm-svn: 216929
* Fix comment and unnecessary check for FP build_vectors.Matt Arsenault2014-09-021-5/+1
| | | | | | | This was copy-paste from the integer version, but FP build_vectors don't truncate. llvm-svn: 216928
* Change MCSchedModel to be a struct of statically initialized data.Pete Cooper2014-09-0210-19/+19
| | | | | | | | This removes static initializers from the backends which generate this data, and also makes this struct match the other Tablegen generated structs in behaviour Reviewed by Andy Trick and Chandler C llvm-svn: 216919
* unique_ptrify PBQPBuilder::buildDavid Blaikie2014-09-021-13/+13
| | | | llvm-svn: 216918
* Enable splitting indexing from loads with TargetConstantsHal Finkel2014-09-021-8/+21
| | | | | | | | | | | | When I recommitted r208640 (in r216898) I added an exclusion for TargetConstant offsets, as there is no guarantee that a backend can handle them on generic ADDs (even if it generates them during address-mode matching) -- and, specifically, applying this transformation directly with TargetConstants caused a self-hosting failure on PPC64. Ignoring all TargetConstants, however, is less than ideal. Instead, for non-opaque constants, we can convert them into regular constants for use with the generated ADD (or SUB). llvm-svn: 216908
* Revert "Revert '[DAGCombiner] Split up an indexed load if only the base ↵Hal Finkel2014-09-021-4/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pointer value is live'" I reverted r208640 in r209747 because r208640 broke self-hosting on PPC64. The underlying cause of the failure is that pre-inc loads with increments represented by ISD::TargetConstants were being transformed into ISD:::ADDs with ISD::TargetConstant operands. PPC doesn't have a pattern for those, and so they were selected as invalid r+r adds. This recommits r208640, rebased and with an exclusion for ISD::TargetConstant increments. This behavior seems correct, although in the future we might want to ask the target to split out the indexing that uses ISD::TargetConstants. Unfortunately, I don't yet have small test case where the relevant invalid 'add' instruction is not itself dead (and thus eliminated by DeadMachineInstructionElim -- sometimes bugpoint is too good at removing things) Original commit message (by Adam Nemet): Right now the load may not get DCE'd because of the side-effect of updating the base pointer. This can happen if we lower a read-modify-write of an illegal larger type (e.g. i48) such that the modification only affects one of the subparts (the lower i32 part but not the higher i16 part). See the testcase. In order to spot the dead load we need to revisit it when SimplifyDemandedBits decided that the value of the load is masked off. This is the CommitTargetLoweringOpt piece. I checked compile time with ARM64 by sending SPEC bitcode files through llc. No measurable change. Fixes <rdar://problem/16031651> llvm-svn: 216898
* CodeGen: indicate Windows unwind data formatSaleem Abdulrasool2014-09-011-1/+6
| | | | | | | | The structures for Windows unwinding are shared across multiple platforms. Indicate the encoding to be used for the particular target. Use this to switch the unwind emitter instantiated by the AsmPrinter. llvm-svn: 216895
* CodeGen: split out the Win64Exception emitterSaleem Abdulrasool2014-09-014-34/+54
| | | | | | | Move the Windows unwind information emitter into a separate header. This is not related to DWARF based emission. NFC. llvm-svn: 216894
* Fix in InlineSpiller to make the rematerilization loop also considerPatrik Hagglund2014-09-011-7/+18
| | | | | | | | | | | | | | | | | | | implicit uses of the whole register when a sub register is defined. Now the same iterator is used in the rematerilization loop as in the spill loop later. Patch provided by Mikael Holmen. This fix was proposed and reviewed by Quentin Colombet, http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-August/076135.html. Unfortunately, this error in the rematerilization code has only been seen in a large test case for an out-of-tree target, and is probably hard to reproduce on an in-tree target. Therefore, no testcase is provided. llvm-svn: 216873
* [MachineSink] Use the real post dominator treeJingyue Wu2014-09-011-21/+9
| | | | | | | | | | | | | | | | | | | | | | | Summary: Fixes a FIXME in MachineSinking. Instead of using the simple heuristics in isPostDominatedBy, use the real MachinePostDominatorTree. The old heuristics caused instructions to sink unnecessarily, and might create register pressure. Test Plan: Added a NVPTX codegen test to verify that our change is in effect. It also shows the unnecessary register pressure caused by over-sinking. Updated affected tests in AArch64 and X86. Reviewers: eliben, meheff, Jiangning Reviewed By: Jiangning Subscribers: jholewinski, aemerson, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D4814 llvm-svn: 216862
* DebugInfo: Elide lexical scopes which only contain other (inline or lexical) ↵David Blaikie2014-08-312-15/+31
| | | | | | | | | | | | | | | | | | | | | scopes. DW_TAG_lexical_scopes inform debuggers about the instruction range for which a given variable (or imported declaration/module/etc) is valid. If the scope doesn't itself contain any such entities, it's a waste of space and should be omitted. We were correctly doing this for entirely empty leaves, but not for intermediate nodes. Reduces total (not just debug sections) .o file size for a bootstrap -gmlt LLVM by 22% and bootstrap -gmlt clang executable by 13%. The wins for a full -g build will be less as a % (and in absolute terms), but should still be substantial - with some of that win being fewer relocations, thus more substantiall reducing link times than fewer bytes alone would have. llvm-svn: 216861
* DebugInfo: Move argument creation up into the caller that's unambiguously ↵David Blaikie2014-08-312-26/+34
| | | | | | handling the subprogram scope (replacing a conditional with an assertion in the process) llvm-svn: 216845
* Delay adding imported entity DIEs to the lexical scope, streamlining the ↵David Blaikie2014-08-311-5/+5
| | | | | | | | | | check for "this scope has nothing in it" This makes the emptiness of the scope with regards to variables and nested scopes is the same as with regards to imported entities. Just check if we had nothing at all before we build the node. llvm-svn: 216840
* Modify DwarfDebug::constructImportedEntityDIE to return rather than insert ↵David Blaikie2014-08-312-16/+7
| | | | | | | | into the scope Another step towards improving lexical_scope handling llvm-svn: 216839
* Refactor constructImportedEntityDIE(DwarfUnit, DIImportedEntity) to return a ↵David Blaikie2014-08-312-11/+16
| | | | | | | | | | | DIE rather than inserting it into a specified context. First of many steps to improve lexical scope construction (to omit trivial lexical scopes - those without any direct variables). To that end it's easier not to create imported entities directly into the lexical scope node, but to build them, then add them if necessary. llvm-svn: 216838
* Simplify expression using container's front() rather than begin()->David Blaikie2014-08-311-3/+1
| | | | llvm-svn: 216833
* [PATCH][Interpreter] Add missing FP intrinsic lowering.Josh Klontz2014-08-301-0/+16
| | | | | | | | | | | | | | | | | Summary: This extends the work done in [1], adding missing intrinsic lowering for floor, trunc, round and copysign. [1] http://comments.gmane.org/gmane.comp.compilers.llvm.cvs/199372 Test Plan: Extended `test/ExecutionEngine/Interpreter/intrinsics.ll` to test the additional missing intrinsics. All tests pass. Reviewers: dexonsmith Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5120 llvm-svn: 216827
* Fix some cases where StringRef was being passed by const reference. Remove ↵Craig Topper2014-08-302-4/+4
| | | | | | const from some other StringRefs since its implicitly const already. llvm-svn: 216820
* [MachineSinking] Clear kill flag of all operands at all their uses.Juergen Ributzka2014-08-291-3/+13
| | | | | | | | | | | | | | | | | | | | | | | When sinking an instruction it might be moved past the original last use of one of its operands. This last use has the kill flag set and the verifier will obviously complain about this. Before Machine Sinking (AArch64): %vreg3<def> = ASRVXr %vreg1, %vreg2<kill> %XZR<def> = SUBSXrs %vreg4, %vreg1<kill>, 160, %NZCV<imp-def> ... After Machine Sinking: %XZR<def> = SUBSXrs %vreg4, %vreg1<kill>, 160, %NZCV<imp-def> ... %vreg3<def> = ASRVXr %vreg1, %vreg2<kill> This fix clears all the kill flags in all instruction that use the same operands as the instruction that is being sunk. This fixes rdar://problem/18180996. llvm-svn: 216803
* Debug info: Add a new explicit DIDescriptor flag for the "public" accessAdrian Prantl2014-08-291-3/+3
| | | | | | | | | | specifier and change the default behavior to only emit the DW_AT_accessibility(public) attribute when the isPublic() is explicitly set. rdar://problem/18154959 llvm-svn: 216799
* Revert accidentally committed patches r216787-r216789David Blaikie2014-08-292-29/+9
| | | | | | | | | | Rushed when I realized I hadn't committed the FreeDeleter for a clang change I'd committed, and didn't check that I had things lying around in my client. Apologies for the noise. llvm-svn: 216792
* Omit DW_AT_artificial, DW_AT_external, and similar attributes under -gmltDavid Blaikie2014-08-291-0/+3
| | | | llvm-svn: 216789
* Omit dwarf::DW_AT_frame_base under -gmltDavid Blaikie2014-08-291-3/+6
| | | | llvm-svn: 216788
* StuffDavid Blaikie2014-08-291-6/+20
| | | | llvm-svn: 216787
* Fix typos in comments, NFCRobin Morisset2014-08-292-2/+2
| | | | | | | | | | | | | | Summary: Just fixing comments, no functional change. Test Plan: N/A Reviewers: jfb Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D5130 llvm-svn: 216784
* Add a const and munge some commentsReid Kleckner2014-08-291-1/+1
| | | | llvm-svn: 216781
* musttail: Forward regparms of variadic functions on x86_64Reid Kleckner2014-08-291-0/+7
| | | | | | | | | | | | | | | | | | | | | | Summary: If a variadic function body contains a musttail call, then we copy all of the remaining register parameters into virtual registers in the function prologue. We track the virtual registers through the function body, and add them as additional registers to pass to the call. Because this is all done in virtual registers, the register allocator usually gives us good code. If the function does a call, however, it will have to spill and reload all argument registers (ew). Forwarding regparms on x86_32 is not implemented because most compilers don't support varargs in 32-bit with regparms. Reviewers: majnemer Subscribers: aemerson, llvm-commits Differential Revision: http://reviews.llvm.org/D5060 llvm-svn: 216780
* Use DwarfDebug::attachLowHighPC for the compilation unit DIE.Frederic Riss2014-08-291-4/+1
| | | | llvm-svn: 216719
* Do not assume the value passed to memset is an i32.Job Noorman2014-08-291-8/+1
| | | | | | | | | | | | | The code in SelectionDAG::getMemset for some reason assumes the value passed to memset is an i32. This breaks the generated code for targets that only have registers smaller than 32 bits because the value might get split into multiple registers by the calling convention. See the test for the MSP430 target included in the patch for an example. This patch ensures that nothing is assumed about the type of the value. Instead, the type is taken from the selected overload of the llvm.memset intrinsic. llvm-svn: 216716
* Move FNEG next to FABS and make them more similar, so it's easier that they ↵Sanjay Patel2014-08-281-43/+46
| | | | | | can be refactored. NFC. llvm-svn: 216688
OpenPOWER on IntegriCloud