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* Check for extra kill flags on live-out virtual registers.Jakob Stoklund Olesen2012-06-291-0/+14
| | | | | | | This would previously get reported as the misleading "Virtual register def doesn't dominate all uses." llvm-svn: 159460
* Add getUniqueVRegDef to MachineRegisterInfo.Manman Ren2012-06-291-0/+11
| | | | | | This comes in handy during peephole optimization. llvm-svn: 159453
* Cleanup in DwarfDebug - fix a typo and remove two unused functionsAlexey Samsonov2012-06-291-7/+1
| | | | llvm-svn: 159433
* Move llvm/Support/IRBuilder.h -> llvm/IRBuilder.hChandler Carruth2012-06-293-17/+17
| | | | | | | | | | | | | | | | | This was always part of the VMCore library out of necessity -- it deals entirely in the IR. The .cpp file in fact was already part of the VMCore library. This is just a mechanical move. I've tried to go through and re-apply the coding standard's preferred header sort, but at 40-ish files, I may have gotten some wrong. Please let me know if so. I'll be committing the corresponding updates to Clang and Polly, and Duncan has DragonEgg. Thanks to Bill and Eric for giving the green light for this bit of cleanup. llvm-svn: 159421
* The DIBuilder class is just a wrapper around debug info creationBill Wendling2012-06-292-3/+3
| | | | | | | (a.k.a. MDNodes). The module doesn't belong in Analysis. Move it to the VMCore instead. llvm-svn: 159414
* Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick2012-06-291-2/+2
| | | | | | This reverts commit r159406. I noticed a performance regression so I'll back out for now. llvm-svn: 159411
* misched: avoid scheduling instructions that can't be dispatched.Andrew Trick2012-06-291-6/+29
| | | | llvm-svn: 159408
* misched: count micro-ops toward the issue limit.Andrew Trick2012-06-291-10/+19
| | | | llvm-svn: 159407
* Make NumMicroOps a variable in the subtarget's instruction itinerary.Andrew Trick2012-06-291-2/+2
| | | | | | | | | | | | | | The TargetInstrInfo::getNumMicroOps API does not change, but soon it will be used by MachineScheduler. Now each subtarget can specify the number of micro-ops per itinerary class. For ARM, this is currently always dynamic (-1), because it is used for load/store multiple which depends on the number of register operands. Zero is now a valid number of micro-ops. This can be used for nop pseudo-instructions or instructions that the hardware can squash during dispatch. llvm-svn: 159406
* add a new @llvm.donothing intrinsic that, well, does nothing, and teach ↵Nuno Lopes2012-06-281-1/+8
| | | | | | CodeGen to ignore calls to it llvm-svn: 159383
* 'Promote' vector [su]int_to_fp should widen elements.Jim Grosbach2012-06-281-3/+54
| | | | | | | | | | | Teach vector legalization how to honor Promote for int to float conversions. The code checking whether to promote the operation knew to look at the operand, but the actual promotion code didn't. This fixes that. The operand is promoted up via [zs]ext. rdar://11762659 llvm-svn: 159378
* Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp andBill Wendling2012-06-2816-28/+28
| | | | | | | | | include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h. The reasoning is because the DebugInfo module is simply an interface to the debug info MDNodes and has nothing to do with analysis. llvm-svn: 159312
* Allow targets to inject passes before the virtual register rewriter.Jakob Stoklund Olesen2012-06-261-1/+5
| | | | | | | | Such passes can be used to tweak the register assignments in a target-dependent way, for example to avoid write-after-write dependencies. llvm-svn: 159209
* Update a bunch of stale comments that dated from when this folled theChandler Carruth2012-06-261-14/+11
| | | | | | | very first (and worst) placement algorithm. These should now more accurately reflect the reality of the pass. llvm-svn: 159185
* Enable the new LoopInfo algorithm by default.Andrew Trick2012-06-261-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | The primary advantage is that loop optimizations will be applied in a stable order. This helps debugging and unit test creation. It is also a better overall implementation without pathologically bad performance on deep functions. On large functions (llvm-stress --size=200000 | opt -loops) Before: 0.1263s After: 0.0225s On deep functions (after tweaking llvm-stress, thanks Nadav): Before: 0.2281s After: 0.0227s See r158790 for more comments. The loop tree is now consistently generated in forward order, but loop passes are applied in reverse order over the program. If we have a loop optimization that prefers forward order, that can easily be achieved by adding a different type of LoopPassManager. llvm-svn: 159183
* Make sure type is not extended or untyped before create a constant of the ↵Evan Cheng2012-06-261-0/+4
| | | | | | type. No test case. Found by inspection. llvm-svn: 159179
* Enforce stricter liveness rules for PHIs.Jakob Stoklund Olesen2012-06-251-6/+11
| | | | | | | | | | | | | Verify that all paths from the entry block to a virtual register read pass through a def. Enable this check even when MRI->isSSA() is false. Verify that the live range of a virtual register is live out of all predecessor blocks, even for PHI-values. This requires that PHIElimination sometimes inserts IMPLICIT_DEF instruction in predecessor blocks. llvm-svn: 159150
* Run ProcessImplicitDefs on SSA form where it can be much simpler.Jakob Stoklund Olesen2012-06-252-262/+99
| | | | | | | | | | | Implicitly defined virtual registers can simply have the <undef> bit set on all uses, and copies can be turned into implicit defs recursively. Physical registers are a bit trickier. We handle the common case where a physreg def is used by a nearby instruction in the same basic block. For more complicated cases, just leave the IMPLICIT_DEF instruction in. llvm-svn: 159149
* Teach PHIElimination to handle <undef> operands.Jakob Stoklund Olesen2012-06-251-19/+34
| | | | | | | | | When a PHI use is <undef>, don't emit a copy in the predecessor block, but insert an IMPLICIT_DEF instruction instead. This ensures that virtual register uses are always jointly dominated by defs, even if some of them are IMPLICIT_DEF. llvm-svn: 159121
* Handle <undef> operands in TwoAddressInstructionPass.Jakob Stoklund Olesen2012-06-251-12/+31
| | | | | | | | | | | | | | | | | When the source register to a 2-addr instruction is undefined, there is no need to attempt any transformations - simply replace the source register with the destination register. This also comes up when lowering IMPLICIT_DEF instructions - make sure the <undef> flag is moved to the new partial register def operand: %vreg8<def> = INSERT_SUBREG %vreg9<undef>, %vreg0<kill>, sub_16bit rewrite undef: %vreg8<def> = INSERT_SUBREG %vreg8<undef>, %vreg0<kill>, sub_16bit convert to: %vreg8:sub_16bit<def,read-undef> = COPY %vreg0<kill> llvm-svn: 159120
* llvm/lib: [CMake] Add explicit dependency to intrinsics_gen.NAKAMURA Takumi2012-06-242-0/+4
| | | | llvm-svn: 159112
* DAG legalisation can now handle illegal fma vector types by scalarisationPete Cooper2012-06-242-0/+32
| | | | llvm-svn: 159092
* Teach LiveVariables to handle <undef> operands.Jakob Stoklund Olesen2012-06-231-3/+5
| | | | | | | | It's simple: Don't treat <undef> operands as uses, and don't assume a virtual register has a defining instruction unless a real use has been seen. llvm-svn: 159061
* Remove ProcessImplicitDefs.h which was unused.Jakob Stoklund Olesen2012-06-221-2/+27
| | | | | | The ProcessImplicitDefs class can be local to its implementation file. llvm-svn: 159041
* Also verify the def index for early clobbers.Jakob Stoklund Olesen2012-06-221-2/+3
| | | | llvm-svn: 159039
* Delete a boring statistic.Jakob Stoklund Olesen2012-06-221-6/+0
| | | | llvm-svn: 159030
* Store live intervals in an IndexedMap.Jakob Stoklund Olesen2012-06-221-14/+8
| | | | | | It is both smaller and faster than DenseMap. llvm-svn: 159029
* Revert r158679 - use case is unclear (and it increases the memory footprint).Hal Finkel2012-06-222-8/+8
| | | | | | | | | | Original commit message: Allow up to 64 functional units per processor itinerary. This patch changes the type used to hold the FU bitset from unsigned to uint64_t. This will be needed for some upcoming PowerPC itineraries. llvm-svn: 159027
* Fix a crash in --debug code.Jakob Stoklund Olesen2012-06-221-2/+6
| | | | | | Don't try to print out the live range of a physreg. llvm-svn: 159021
* Don't depend on live ranges being present.Jakob Stoklund Olesen2012-06-221-3/+8
| | | | | | | DBG_VALUE instructions could be referring to non-existing virtual registers. llvm-svn: 159020
* Simplify handleMove() a bit.Jakob Stoklund Olesen2012-06-221-4/+4
| | | | | | | There is no need to check for physreg live ranges. They don't exist any more. llvm-svn: 159019
* Stop computing physreg live ranges.Jakob Stoklund Olesen2012-06-221-189/+1
| | | | | | Everyone is using on-demand regunit ranges now. llvm-svn: 159018
* Remove some redundant LIS->hasInterval() checks.Jakob Stoklund Olesen2012-06-221-22/+0
| | | | | | | These functions only operate on virtual registers now, and they all have live ranges. llvm-svn: 159015
* Use MRI::isConstantPhysReg() to check remat feasibility.Jakob Stoklund Olesen2012-06-221-4/+8
| | | | | | | Don't depend on LiveIntervals::hasInterval() to determine if a physreg is reserved and constant. llvm-svn: 159013
* Use regunit liveness to guide LiveDebugVariables.Jakob Stoklund Olesen2012-06-221-5/+18
| | | | | | This should produce the same results as using physreg liveness directly. llvm-svn: 159009
* Remove LiveIntervals::trackingRegUnits().Jakob Stoklund Olesen2012-06-223-71/+13
| | | | | | | | | With regunit liveness permanently enabled, this function would always return true. Also remove now obsolete code for checking physreg interference. llvm-svn: 159006
* Remove another duplicated variable. We only need one to tell us if the linkerRafael Espindola2012-06-221-1/+1
| | | | | | knows dwarf or not. llvm-svn: 158993
* Fix a FIXME: DwarfRequiresRelocationForSectionOffset is the same asRafael Espindola2012-06-221-1/+1
| | | | | | DwarfUsesRelocationsAcrossSections. llvm-svn: 158992
* Emit relocations for DW_AT_location entries on systems which need it. This isNick Lewycky2012-06-222-11/+16
| | | | | | a recommit of r127757. Fixes PR9493. Patch by Paul Robinson! llvm-svn: 158957
* Rename -allow-excess-fp-precision flag to -fuse-fp-ops, and switch from aLang Hames2012-06-222-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | boolean flag to an enum: { Fast, Standard, Strict } (default = Standard). This option controls the creation by optimizations of fused FP ops that store intermediate results in higher precision than IEEE allows (E.g. FMAs). The behavior of this option is intended to match the behaviour specified by a soon-to-be-introduced frontend flag: '-ffuse-fp-ops'. Fast mode - allows formation of fused FP ops whenever they're profitable. Standard mode - allow fusion only for 'blessed' FP ops. At present the only blessed op is the fmuladd intrinsic. In the future more blessed ops may be added. Strict mode - allow fusion only if/when it can be proven that the excess precision won't effect the result. Note: This option only controls formation of fused ops by the optimizers. Fused operations that are explicitly requested (e.g. FMA via the llvm.fma.* intrinsic) will always be honored, regardless of the value of this option. Internally TargetOptions::AllowExcessFPPrecision has been replaced by TargetOptions::AllowFPOpFusion. llvm-svn: 158956
* The inline asm operand modifier 'n' is suppose Jack Carter2012-06-211-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | to be generic across architectures. It has the following description in the gnu sources: Negate the immediate constant Several Architectures such as x86 have local implementations of operand modifier 'n' which go beyond the above description slightly. This won't affect them. Affected files: lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Added 'n' to the switch cases. test/CodeGen/Generic/asm-large-immediate.ll Generic compiled test (x86 for me) test/CodeGen/Mips/asm-large-immediate.ll Mips compiled version of the generic one Contributer: Jack Carter llvm-svn: 158939
* Fix potential crash if DAGCombine on stores sees a half typePete Cooper2012-06-211-1/+2
| | | | llvm-svn: 158927
* The inline asm operand modifier 'c' is suppose Jack Carter2012-06-211-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to be generic across architectures. It has the following description in the gnu sources: Substitute immediate value without immediate syntax Several Architectures such as x86 have local implementations of operand modifier 'c' which go beyond the above description slightly. To make use of the generic modifiers without overriding local implementation one can make a call to the base class method for AsmPrinter::PrintAsmOperand() in the locally derived method's "default" case in the switch statement. That way if it is already defined locally the generic version will never get called. This change is needed when test/CodeGen/generic/asm-large-immediate.ll failed on a native Mips board. The test was assuming a generic implementation was in place. Affected files: lib/Target/Mips/MipsAsmPrinter.cpp: Changed the default case to call the base method. lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Added 'c' to the switch cases. test/CodeGen/Mips/asm-large-immediate.ll Mips compiled version of the generic one Contributer: Jack Carter llvm-svn: 158925
* Emit a single _udivmodsi4 libcall instead of two separate _udivsi3 andEvan Cheng2012-06-211-5/+7
| | | | | | | | _umodsi3 libcalls if they have the same arguments. This optimization was apparently broken if one of the node was replaced in place. rdar://11714607 llvm-svn: 158900
* Update regunits in RegisterCoalescer::reMaterializeTrivialDef.Jakob Stoklund Olesen2012-06-211-6/+4
| | | | | | Old code would only update physreg live intervals. llvm-svn: 158881
* Remove spurious typedefs.Jakob Stoklund Olesen2012-06-201-3/+0
| | | | llvm-svn: 158878
* Remove the RenderMachineFunction HTML output pass.Jakob Stoklund Olesen2012-06-206-1374/+0
| | | | | | | I don't think anyone has been using this functionality for a while, and it is getting in the way of refactoring now. llvm-svn: 158876
* Remove the -live-regunits command line option.Jakob Stoklund Olesen2012-06-201-12/+4
| | | | | | Register allocators depend on it being permanently enabled now. llvm-svn: 158873
* Fix some more LiveInterval enumerations.Jakob Stoklund Olesen2012-06-202-13/+12
| | | | | | Deterministically enumerate the virtual registers instead. llvm-svn: 158872
* Remove LiveIntervalUnions from RegAllocBase.Jakob Stoklund Olesen2012-06-204-167/+14
| | | | | | They are living in LiveRegMatrix now. llvm-svn: 158868
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