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* When lowering an inreg sext first shift left, then right arithmetically.Benjamin Kramer2013-01-121-3/+3
| | | | | | | Shifting right two times will only yield zero. Should fix SingleSource/UnitTests/SignlessTypes/factor. llvm-svn: 172322
* Limit the search space in RAGreedy::tryEvict().Jakob Stoklund Olesen2013-01-122-1/+33
| | | | | | | When tryEvict() is looking for a cheaper register in the allocation order, skip the tail of too expensive registers when possible. llvm-svn: 172281
* Precompute some information about register costs.Jakob Stoklund Olesen2013-01-121-2/+22
| | | | | | | | | | | Remember the minimum cost of the registers in an allocation order and the number of registers at the end of the allocation order that have the same cost per use. This information can be used to limit the search space for RAGreedy::tryEvict() when looking for a cheaper register. llvm-svn: 172280
* PPC: Implement efficient lowering of sign_extend_inreg.Nadav Rotem2013-01-111-1/+25
| | | | llvm-svn: 172269
* Remove some accidentaly duplicated code. This needs urgent cleanup :(Benjamin Kramer2013-01-111-270/+0
| | | | llvm-svn: 172248
* Split TargetLowering into a CodeGen and a SelectionDAG part.Benjamin Kramer2013-01-1110-992/+1301
| | | | | | | | | This fixes some of the cycles between libCodeGen and libSelectionDAG. It's still a complete mess but as long as the edges consist of virtual call it doesn't cause breakage. BasicTTI did static calls and thus broke some build configurations. llvm-svn: 172246
* ARM Cost Model: Modify the target independent cost model to askNadav Rotem2013-01-111-12/+21
| | | | | | | | the target if it supports the different CAST types. We didn't do this on X86 because of the different register sizes and types, but on ARM this makes sense. llvm-svn: 172245
* For inline asm:Eric Christopher2013-01-113-4/+18
| | | | | | | | | | | - recognize string "{memory}" in the MI generation - mark as mayload/maystore when there's a memory clobber constraint. PR14859. Patch by Krzysztof Parzyszek llvm-svn: 172228
* Follow-up typo correction from building the wrong branch.Andrew Trick2013-01-111-2/+2
| | | | llvm-svn: 172224
* Fix typo from r170452. Affects -enable-misched heuristics.Andrew Trick2013-01-111-2/+2
| | | | llvm-svn: 172223
* Simplify writing floating types to assembly.Tim Northover2013-01-111-74/+32
| | | | | | | This removes previous special cases for each floating-point type in favour of a shared codepath. llvm-svn: 172189
* PR14896: Handle memcpy from constant string where the memcpy size is larger ↵Evan Cheng2013-01-101-2/+3
| | | | | | than the string size. llvm-svn: 172124
* Remove unneeded includes from FunctionLoweringInfo.h.Jakub Staszak2013-01-101-1/+1
| | | | llvm-svn: 172123
* Allow hasProperty() to be called on bundle-internal instructions.Jakob Stoklund Olesen2013-01-101-0/+1
| | | | | | | | | | | | | When calling hasProperty() on an instruction inside a bundle, it should always behave as if IgnoreBundle was passed, and just return properties for the current instruction. Only attempt to aggregate bundle properties whan asked about the bundle header. The assertion fires on existing ARM test cases without this fix. llvm-svn: 172082
* Support headerless bundles in MachineInstr::hasProperty().Jakob Stoklund Olesen2013-01-101-7/+5
| | | | | | This function can still work without a BUNDLE header instruction. llvm-svn: 172029
* Stack Alignment: throw error if we can't satisfy the minimal alignmentManman Ren2013-01-103-20/+34
| | | | | | | | | | | | | | | | | | requirement when creating stack objects in MachineFrameInfo. Add CreateStackObjectWithMinAlign to throw error when the minimal alignment can't be achieved and to clamp the alignment when the preferred alignment can't be achieved. Same is true for CreateVariableSizedObject. Will not emit error in CreateSpillStackObject or CreateStackObject. As long as callers of CreateStackObject do not assume the object will be aligned at the requested alignment, we should not have miscompile since later optimizations which look at the object's alignment will have the correct information. rdar://12713765 llvm-svn: 172027
* ARM Cost model: Use the size of vector registers and widest vectorizable ↵Nadav Rotem2013-01-091-0/+5
| | | | | | instruction to determine the max vectorization factor. llvm-svn: 172010
* Fix a DAG combine bug visitBRCOND() is transforming br(xor(x, y)) to br(x != y).Evan Cheng2013-01-091-12/+18
| | | | | | | | | It cahced XOR's operands before calling visitXOR() but failed to update the operands when visitXOR changed the XOR node. rdar://12968664 llvm-svn: 171999
* Don't print bundle flags.Jakob Stoklund Olesen2013-01-091-1/+2
| | | | | | | The bundle flags are used by MachineBasicBlock::print(), they don't need to clutter up individual MachineInstrs. llvm-svn: 171986
* Don't require BUNDLE headers in MachineInstr::getBundleSize().Jakob Stoklund Olesen2013-01-091-10/+5
| | | | | | | | It is possible to build MI bundles that don't begin with a BUNDLE header. Add support for such bundles, counting all instructions inside the bundle. llvm-svn: 171985
* Fix a typo in MachineInstr::unbundleFromSucc() method.Sergei Larin2013-01-091-1/+1
| | | | llvm-svn: 171983
* Refactor to expose RTLIB calls to targets.Tim Northover2013-01-096-337/+367
| | | | | | | | | | fp128 is almost but not quite completely illegal as a type on AArch64. As a result it needs to have a register class (for argument passing mainly), but all operations need to be lowered to runtime calls. Currently there's no way for targets to do this (without duplicating code), as the relevant functions are hidden in SelectionDAG. This patch changes that. llvm-svn: 171971
* Last in the series of removing unnecessary '0' arguments forEric Christopher2013-01-094-8/+8
| | | | | | | address space. Reordered the EmitULEB128IntValue arguments to make this easier. llvm-svn: 171949
* MIsched: add an ILP window property to machine model.Andrew Trick2013-01-091-10/+2
| | | | | | | | | | This was an experimental option, but needs to be defined per-target. e.g. PPC A2 needs to aggressively hide latency. I converted some in-order scheduling tests to A2. Hal is working on more test cases. llvm-svn: 171946
* These functions have default arguments of 0 for the last arg. UseEric Christopher2013-01-093-5/+5
| | | | | | them. llvm-svn: 171933
* These functions have default arguments of 0 for the last arg. UseEric Christopher2013-01-095-25/+23
| | | | | | them and add one where it seemed obvious that we wanted one. llvm-svn: 171932
* Cost Model: Move the 'max unroll factor' variable to the TTI and add initial ↵Nadav Rotem2013-01-091-0/+5
| | | | | | Cost Model support on ARM. llvm-svn: 171928
* Move the string pools down into the units. No functional change.Eric Christopher2013-01-082-22/+14
| | | | llvm-svn: 171905
* Add fp128 rtlib function names to LLVMTim Northover2013-01-082-18/+138
| | | | llvm-svn: 171867
* Allow the asm printer to print fp128 values properly.Tim Northover2013-01-081-9/+12
| | | | llvm-svn: 171866
* Sink a function that refers to the SelectionDAG into that library in theChandler Carruth2013-01-082-21/+21
| | | | | | | | | | | | | | one file where it is called as a static function. Nuke the declaration and the definition in lib/CodeGen, along with the include of SelectionDAG.h from this file. There is no dependency edge from lib/CodeGen to lib/CodeGen/SelectionDAG, so it isn't valid for a routine in lib/CodeGen to reference the DAG. There is a dependency from lib/CodeGen/SelectionDAG on lib/CodeGen. This breaks one violation of this layering. llvm-svn: 171842
* Remove the llvm-local DW_TAG_vector_type tag and add a test toEric Christopher2013-01-081-2/+1
| | | | | | make sure that vector types do work. llvm-svn: 171833
* Pack MachineOperand bitfields better.Jakob Stoklund Olesen2013-01-071-1/+1
| | | | | | Previously, 4 bits were unused. llvm-svn: 171814
* Pack MachineInstr fields better.Jakob Stoklund Olesen2013-01-071-5/+3
| | | | | | This shrinks MachineInstr to 64 bytes (from 72). llvm-svn: 171813
* Whitespace and 80-col.Eric Christopher2013-01-073-5/+6
| | | | llvm-svn: 171803
* Add more comments to what's going on here.Eric Christopher2013-01-071-1/+3
| | | | llvm-svn: 171780
* Add support for separating strings for the split debug info DWARF5Eric Christopher2013-01-075-6/+63
| | | | | | | | | | | | | proposal. This leaves the strings in the skeleton die as strp, but in all dwo files they're accessed now via DW_FORM_GNU_str_index. Add support for dumping these sections and modify the fission-cu.ll testcase to have the correct strings and form. Fix a small bug in the fixed form sizes routine that involved out of array accesses for the table and add a FIXME in the extractFast routine to fix this up. llvm-svn: 171779
* Sink AddrMode back into TargetLowering, removing one of the mostChandler Carruth2013-01-072-2/+2
| | | | | | | | | peculiar headers under include/llvm. This struct still doesn't make a lot of sense, but it makes more sense down in TargetLowering than it did before. llvm-svn: 171739
* Switch the SCEV expander and LoopStrengthReduce to useChandler Carruth2013-01-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TargetTransformInfo rather than TargetLowering, removing one of the primary instances of the layering violation of Transforms depending directly on Target. This is a really big deal because LSR used to be a "special" pass that could only be tested fully using llc and by looking at the full output of it. It also couldn't run with any other loop passes because it had to be created by the backend. No longer is this true. LSR is now just a normal pass and we should probably lift the creation of LSR out of lib/CodeGen/Passes.cpp and into the PassManagerBuilder. =] I've not done this, or updated all of the tests to use opt and a triple, because I suspect someone more familiar with LSR would do a better job. This change should be essentially without functional impact for normal compilations, and only change behvaior of targetless compilations. The conversion required changing all of the LSR code to refer to the TTI interfaces, which fortunately are very similar to TargetLowering's interfaces. However, it also allowed us to *always* expect to have some implementation around. I've pushed that simplification through the pass, and leveraged it to simplify code somewhat. It required some test updates for one of two things: either we used to skip some checks altogether but now we get the default "no" answer for them, or we used to have no information about the target and now we do have some. I've also started the process of removing AddrMode, as the TTI interface doesn't use it any longer. In some cases this simplifies code, and in others it adds some complexity, but I think it's not a bad tradeoff even there. Subsequent patches will try to clean this up even further and use other (more appropriate) abstractions. Yet again, almost all of the formatting changes brought to you by clang-format. =] llvm-svn: 171735
* PR14759: Debug info support for C++ member pointers.David Blaikie2013-01-071-0/+3
| | | | | | | | This works fine with GDB for member variable pointers, but GDB's support for member function pointers seems to be quite unrelated to DW_TAG_ptr_to_member_type. (see GDB bug 14998 for details) llvm-svn: 171698
* Move TargetTransformInfo to live under the Analysis library. This noChandler Carruth2013-01-073-3/+3
| | | | | | | longer would violate any dependency layering and it is in fact an analysis. =] llvm-svn: 171686
* Switch TargetTransformInfo from an immutable analysis pass that requiresChandler Carruth2013-01-075-0/+486
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a TargetMachine to construct (and thus isn't always available), to an analysis group that supports layered implementations much like AliasAnalysis does. This is a pretty massive change, with a few parts that I was unable to easily separate (sorry), so I'll walk through it. The first step of this conversion was to make TargetTransformInfo an analysis group, and to sink the nonce implementations in ScalarTargetTransformInfo and VectorTargetTranformInfo into a NoTargetTransformInfo pass. This allows other passes to add a hard requirement on TTI, and assume they will always get at least on implementation. The TargetTransformInfo analysis group leverages the delegation chaining trick that AliasAnalysis uses, where the base class for the analysis group delegates to the previous analysis *pass*, allowing all but tho NoFoo analysis passes to only implement the parts of the interfaces they support. It also introduces a new trick where each pass in the group retains a pointer to the top-most pass that has been initialized. This allows passes to implement one API in terms of another API and benefit when some other pass above them in the stack has more precise results for the second API. The second step of this conversion is to create a pass that implements the TargetTransformInfo analysis using the target-independent abstractions in the code generator. This replaces the ScalarTargetTransformImpl and VectorTargetTransformImpl classes in lib/Target with a single pass in lib/CodeGen called BasicTargetTransformInfo. This class actually provides most of the TTI functionality, basing it upon the TargetLowering abstraction and other information in the target independent code generator. The third step of the conversion adds support to all TargetMachines to register custom analysis passes. This allows building those passes with access to TargetLowering or other target-specific classes, and it also allows each target to customize the set of analysis passes desired in the pass manager. The baseline LLVMTargetMachine implements this interface to add the BasicTTI pass to the pass manager, and all of the tools that want to support target-aware TTI passes call this routine on whatever target machine they end up with to add the appropriate passes. The fourth step of the conversion created target-specific TTI analysis passes for the X86 and ARM backends. These passes contain the custom logic that was previously in their extensions of the ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces. I separated them into their own file, as now all of the interface bits are private and they just expose a function to create the pass itself. Then I extended these target machines to set up a custom set of analysis passes, first adding BasicTTI as a fallback, and then adding their customized TTI implementations. The fourth step required logic that was shared between the target independent layer and the specific targets to move to a different interface, as they no longer derive from each other. As a consequence, a helper functions were added to TargetLowering representing the common logic needed both in the target implementation and the codegen implementation of the TTI pass. While technically this is the only change that could have been committed separately, it would have been a nightmare to extract. The final step of the conversion was just to delete all the old boilerplate. This got rid of the ScalarTargetTransformInfo and VectorTargetTransformInfo classes, all of the support in all of the targets for producing instances of them, and all of the support in the tools for manually constructing a pass based around them. Now that TTI is a relatively normal analysis group, two things become straightforward. First, we can sink it into lib/Analysis which is a more natural layer for it to live. Second, clients of this interface can depend on it *always* being available which will simplify their code and behavior. These (and other) simplifications will follow in subsequent commits, this one is clearly big enough. Finally, I'm very aware that much of the comments and documentation needs to be updated. As soon as I had this working, and plausibly well commented, I wanted to get it committed and in front of the build bots. I'll be doing a few passes over documentation later if it sticks. Commits to update DragonEgg and Clang will be made presently. llvm-svn: 171681
* Funnel the actual TargetTransformInfo pass from the SelectionDAGISelChandler Carruth2013-01-052-5/+9
| | | | | | | | | pass into the SelectionDAG itself rather than snooping on the implementation of that pass as exposed by the TargetMachine. This removes the last direct client of the ScalarTargetTransformInfo class outside of the TTI pass implementation. llvm-svn: 171625
* Emit DW_TAG_formal_parameter for unnamed parameters.David Blaikie2013-01-051-2/+0
| | | | | | | | | | This change essentially reverts r87069 which came without a test case. It causes no regressions in the GDB 7.5 test suite & fixes 25 xfails (commit to the test suite to follow). If anyone can present a test case that demonstrates why this check is necessary I'd be happy to account for it in one way or another. llvm-svn: 171609
* Don't call destructors on MachineInstr and MachineOperand.Jakob Stoklund Olesen2013-01-053-30/+13
| | | | | | | | | | | | | | | | | | | | The series of patches leading up to this one makes llc -O0 run 8% faster. When deallocating a MachineFunction, there is no need to visit all MachineInstr and MachineOperand objects to deallocate them. All their memory come from a BumpPtrAllocator that is about to be purged, and they have empty destructors anyway. This only applies when deallocating the MachineFunction. DeleteMachineInstr() should still be used to recycle MI memory during the codegen passes. Remove the LeakDetector support for MachineInstr. I've never seen it used before, and now it definitely doesn't work. With this patch, leaked MachineInstrs would be much less of a problem since all of their memory will be reclaimed by ~MachineFunction(). llvm-svn: 171599
* Use ArrayRecycler for MachineInstr operand lists.Jakob Stoklund Olesen2013-01-052-74/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of an std::vector<MachineOperand>, use MachineOperand arrays from an ArrayRecycler living in MachineFunction. This has several advantages: - MachineInstr now has a trivial destructor, making it possible to delete them in batches when destroying MachineFunction. This will be enabled in a later patch. - Bypassing malloc() and free() can be faster, depending on the system library. - MachineInstr objects and their operands are allocated from the same BumpPtrAllocator, so they will usually be next to each other in memory, providing better locality of reference. - Reduce MachineInstr footprint. A std::vector is 24 bytes, the new operand array representation only uses 8+4+1 bytes in MachineInstr. - Better control over operand array reallocations. In the old representation, the use-def chains would be reordered whenever a std::vector reached its capacity. The new implementation never changes the use-def chain order. Note that some decisions in the code generator depend on the use-def chain orders, so this patch may cause different assembly to be produced in a few cases. llvm-svn: 171598
* Add MachineRegisterInfo::moveOperands().Jakob Stoklund Olesen2013-01-051-0/+49
| | | | | | | | | | | | | This function works like memmove() for MachineOperands, except it also updates any use-def chains containing the moved operands. The use-def chains are updated without affecting the order of operands in the list. That isn't possible when using the removeRegOperandFromUseList() and addRegOperandToUseList() functions. Callers to follow soon. llvm-svn: 171597
* Move an assertion so it doesn't dereference end().Jakob Stoklund Olesen2013-01-041-4/+3
| | | | | | The R600 target has test cases that exercises this code. llvm-svn: 171538
* Add a name for the anonymous type we're creating for subrangeEric Christopher2013-01-041-0/+3
| | | | | | | | types and a FIXME for what we should be doing. Should solve the immediacy of PR12069 where our debug info is crashing another tool. llvm-svn: 171536
* small fixes to enable the reuse of the pass manager across multiple modulesPedro Artigas2013-01-041-1/+3
| | | | llvm-svn: 171475
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