summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
...
* [WinEH] Remove extraneous call to emitEHRegistrationOffsetLabelDavid Majnemer2015-10-211-1/+0
| | | | | | It's a relic from the earlier implementation, let's remove it. llvm-svn: 250964
* LegalizeDAG: Implement promote for build_vectorMatt Arsenault2015-10-211-0/+30
| | | | | | | | | | This will be used in future commits for AMDGPU to promote operations on i64 vectors into operations on 32-bit vector components. This will be used / tested in future AMDGPU commits. llvm-svn: 250945
* Masked Load/Store optimization for scalar codeElena Demikhovsky2015-10-211-12/+72
| | | | | | | | | When we have to convert the masked.load, masked.store to scalar code, we generate a chain of conditional basic blocks. I added optimization for constant mask vector. Differential Revision: http://reviews.llvm.org/D13855 llvm-svn: 250893
* Let MachineVerifier be aware of mem-to-mem instructions.Jonas Paulsson2015-10-211-2/+8
| | | | | | | | | | | | | | | A mem-to-mem instruction (that both loads and stores), which store to an FI, cannot pass the verifier since it thinks it is loading from the FI. For the mem-to-mem instruction, do a looser check in visitMachineOperand() and only check liveness at the reg-slot while analyzing a frame index operand. Needed to make CodeGen/SystemZ/xor-01.ll pass with -verify-machineinstrs, which now runs with this flag. Reviewed by Evan Cheng and Quentin Colombet. llvm-svn: 250885
* Tail duplication can mix incompatible registers in phi nodesKrzysztof Parzyszek2015-10-211-0/+21
| | | | | | | | | Do not tail duplicate blocks where the successor has a phi node, and the corresponding value in that phi node uses a subregister. http://reviews.llvm.org/D13922 llvm-svn: 250877
* Two switch blocks in VectorLegalizer::LegalizeOp already have aArtyom Skrobov2015-10-201-0/+1
| | | | | | | | | | default: llvm_unreachable("This action is not supported yet!"); -- so I'm adding one to the third switch block, too. This is a follow-up fix for http://reviews.llvm.org/D13862 llvm-svn: 250830
* Adding support for TargetLoweringBase::LibCallArtyom Skrobov2015-10-201-251/+275
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: TargetLoweringBase::Expand is defined as "Try to expand this to other ops, otherwise use a libcall." For ISD::UDIV and ISD::SDIV, the choice between the two possibilities was defined in a rather convoluted way: - if DIVREM is legal, expand to DIVREM - if DIVREM has a custom lowering, expand to DIVREM - if DIVREM libcall is defined and a remainder from the same division is computed elsewhere, expand to a DIVREM libcall - else, expand to a DIV libcall This had the undesirable effect that if both DIV and DIVREM are implemented as libcalls, then ISD::UDIV and ISD::SDIV are expanded to the heavier DIVREM libcall, even when the remainder isn't used. The new code adds a new LegalizeAction, TargetLoweringBase::LibCall, so that backends can directly control whether they prefer an expansion or a conversion to a libcall. This makes the generic lowering code even more generic, allowing its reuse in a wider range of target-specific configurations. The useful effect is that ARM backend will now generate a call to __aeabi_{i,u}div rather than __aeabi_{i,u}divmod in cases where it doesn't need the remainder. There's no functional change outside the ARM backend. Reviewers: t.p.northover, rengolin Subscribers: t.p.northover, llvm-commits, aemerson Differential Revision: http://reviews.llvm.org/D13862 llvm-svn: 250826
* Combining DIV+REM->DIVREM doesn't belong in LegalizeDAG; move it over into ↵Artyom Skrobov2015-10-203-67/+99
| | | | | | | | | | | | | | | | | | | | | | | | DAGCombiner. Summary: In addition to moving the code over, this patch amends the DIV,REM -> DIVREM combining to run on all affected nodes at once: if the nodes are converted to DIVREM one at a time, then the resulting DIVREM may get legalized by the backend into something target-specific that we won't be able to recognize and correlate with the remaining nodes. The motivation is to "prepare terrain" for D13862: when we set DIV and REM to be legalized to libcalls, instead of the DIVREM, we otherwise lose the ability to combine them together. To prevent this, we need to take the DIV,REM -> DIVREM combining out of the lowering stage. Reviewers: RKSimon, eli.friedman, rengolin Subscribers: john.brawn, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D13733 llvm-svn: 250825
* AsmPrinter: Remove implicit ilist iterator conversion, NFCDuncan P. N. Exon Smith2015-10-201-3/+3
| | | | llvm-svn: 250776
* Enhance loop rotation with existence of profile data in ↵Cong Hou2015-10-191-3/+184
| | | | | | | | | | | | | | | | MachineBlockPlacement pass. Currently, in MachineBlockPlacement pass the loop is rotated to let the best exit to be the last BB in the loop chain, to maximize the fall-through from the loop to outside. With profile data, we can determine the cost in terms of missed fall through opportunities when rotating a loop chain and select the best rotation. Basically, there are three kinds of cost to consider for each rotation: 1. The possibly missed fall through edge (if it exists) from BB out of the loop to the loop header. 2. The possibly missed fall through edges (if they exist) from the loop exits to BB out of the loop. 3. The missed fall through edge (if it exists) from the last BB to the first BB in the loop chain. Therefore, the cost for a given rotation is the sum of costs listed above. We select the best rotation with the smallest cost. This is only for PGO mode when we have more precise edge frequencies. Differential revision: http://reviews.llvm.org/D10717 llvm-svn: 250754
* [CGP] transform select instructions into branches and sink expensive operandsSanjay Patel2015-10-191-16/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | This was originally checked in at r250527, but reverted at r250570 because of PR25222. There were at least 2 problems: 1. The cost check was checking for an instruction with an exact cost of TCC_Expensive; that should have been >=. 2. The cause of the clang stage 1 failures was illegally sinking 'call' instructions; we can't sink instructions that may have side effects / are not safe to execute speculatively. Fixed those conditions in sinkSelectOperand() and added test cases. Original commit message: This is a follow-up to the discussion in D12882. Ideally, we would like SimplifyCFG to be able to form select instructions even when the operands are expensive (as defined by the TTI cost model) because that may expose further optimizations. However, we would then like a later pass like CodeGenPrepare to undo that transformation if the target would likely benefit from not speculatively executing an expensive op (this patch). Once we have this safety mechanism in place, we can adjust SimplifyCFG to restore its select-formation behavior that changed with r248439. Differential Revision: http://reviews.llvm.org/D13297 llvm-svn: 250743
* Restore the original behavior of SelectionDAG::getTargetIndex().Owen Anderson2015-10-191-1/+1
| | | | | | It looks like an extra negation snuck in as apart of restoring it. llvm-svn: 250726
* Put back SelectionDAG::getTargetIndex.Benjamin Kramer2015-10-191-0/+18
| | | | | | | While technically this is untested dead code, it has out-of-tree users. This reverts a part of r250434. llvm-svn: 250717
* Revert "RegisterPressure: allocatable physreg uses are always kills"Matthias Braun2015-10-191-27/+25
| | | | | | | | | This reverts commit r250596. Reverted for now as the commit triggers assert in the AMDGPU target pending investigation. llvm-svn: 250713
* Removed parameter "Consecutive" from isLegalMaskedLoad() / isLegalMaskedStore().Elena Demikhovsky2015-10-191-2/+2
| | | | | | | | | | Originally I planned to use the same interface for masked gather/scatter and set isConsecutive to "false" in this case. Now I'm implementing masked gather/scatter and see that the interface is inconvenient. I want to add interfaces isLegalMaskedGather() / isLegalMaskedScatter() instead of using the "Consecutive" parameter in the existing interfaces. Differential Revision: http://reviews.llvm.org/D13850 llvm-svn: 250686
* Use SDValue bool check. NFCI.Simon Pilgrim2015-10-181-2/+2
| | | | llvm-svn: 250653
* Move one-use variable inside test. NFC.Simon Pilgrim2015-10-181-2/+1
| | | | llvm-svn: 250651
* [DAG] Ensure vector constant folding uses correct scalar undef typesSimon Pilgrim2015-10-171-2/+2
| | | | | | Minor fix to D13665 found during post-commit review. llvm-svn: 250616
* RegisterPressure: Unify the sparse sets in LiveRegsSet; NFCMatthias Braun2015-10-171-12/+19
| | | | | | Also do some cleanups comment improvements. llvm-svn: 250598
* RegisterPressure: allocatable physreg uses are always killsMatthias Braun2015-10-171-25/+27
| | | | | | | | | | | | | | This property was already used in the code path when no liveness intervals are present. Unfortunately the code path that uses liveness intervals tried to query a cached live interval for an allocatable physreg, those are usually not computed so a conservative default was used. This doesn't affect any of the lit testcases. This is a foreclosure to upcoming changes which should be NFC but without this patch this tidbit wouldn't be NFC. llvm-svn: 250596
* RegisterPressure: Remove 0 entries from PressureChangeMatthias Braun2015-10-171-4/+14
| | | | | | | | | | | This should not change behaviour because as far as I can see all code reading the pressure changes has no effect if the PressureInc is 0. Removing these entries however does avoid unnecessary computation, and results in a more stable debug output. I want the stable debug output to check that some upcoming changes are indeed NFC and identical even at the debug output level. llvm-svn: 250595
* RegisterPressure: Hide non-const iterators of PressureDiffMatthias Braun2015-10-171-1/+1
| | | | | | | It is too easy to accidentally violate the ordering requirements when modifying the PressureDiff entries through iterators. llvm-svn: 250590
* [WinEH] Fix eh.exceptionpointer intrinsic loweringJoseph Tremoulet2015-10-171-1/+2
| | | | | | | | | | | | | | | Summary: Some shared code for handling eh.exceptionpointer and eh.exceptioncode needs to not share the part that truncates to 32 bits, which is intended just for exception codes. Reviewers: rnk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13747 llvm-svn: 250588
* [WinEH] Fix stack alignment in funclets and ParentFrameOffset calculationReid Kleckner2015-10-161-6/+8
| | | | | | | | | | | | Our previous value of "16 + 8 + MaxCallFrameSize" for ParentFrameOffset is incorrect when CSRs are involved. We were supposed to have a test case to catch this, but it wasn't very rigorous. The main effect here is that calling _CxxThrowException inside a catchpad doesn't immediately crash on MOVAPS when you have an odd number of CSRs. llvm-svn: 250583
* RegisterPressure: Use range based for, cleanupMatthias Braun2015-10-161-14/+7
| | | | llvm-svn: 250579
* Revert "This is a follow-up to the discussion in D12882."Benjamin Kramer2015-10-161-100/+16
| | | | | | Breaks clang selfhost, see PR25222. This reverts commits r250527 and r250528. llvm-svn: 250570
* [WinEH] Fix CatchRetSuccessorColorMap accountingJoseph Tremoulet2015-10-161-2/+0
| | | | | | | | | | | | | | | | Summary: We now use the block for the catchpad itself, rather than its normal successor, as the funclet entry. Putting the normal successor in the map leads downstream funclet membership computations to erroneous results. Reviewers: majnemer, rnk Subscribers: rnk, llvm-commits Differential Revision: http://reviews.llvm.org/D13798 llvm-svn: 250552
* [WinEH] Remove dead code/includes from WinEHPrepareDavid Majnemer2015-10-161-29/+2
| | | | | | No functionality change is intended. llvm-svn: 250545
* [WinEH] Fix endpad coloring/numberingJoseph Tremoulet2015-10-161-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: When a cleanup's cleanupendpad or cleanupret targets a catchendpad, stop trying to propagate the cleanup's parent's color to the catchendpad, since what's needed is the cleanup's grandparent's color and the catchendpad will get that color from the catchpad linkage already. We already had this exclusion for invokes, but were missing it for cleanupendpad/cleanupret. Also add a missing line that tags cleanupendpads' states in the EHPadStateMap, without with lowering invokes that target cleanupendpads which unwind to other handlers (and so don't have the -1 state) will fail. This fixes the reduced IR repro in PR25163. Reviewers: majnemer, andrew.w.kaylor, rnk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13797 llvm-svn: 250534
* This is a follow-up to the discussion in D12882.Sanjay Patel2015-10-161-16/+100
| | | | | | | | | | | | | | Ideally, we would like SimplifyCFG to be able to form select instructions even when the operands are expensive (as defined by the TTI cost model) because that may expose further optimizations. However, we would then like a later pass like CodeGenPrepare to undo that transformation if the target would likely benefit from not speculatively executing an expensive op (this patch). Once we have this safety mechanism in place, we can adjust SimplifyCFG to restore its select-formation behavior that changed with r248439. Differential Revision: http://reviews.llvm.org/D13297 llvm-svn: 250527
* Revert "[safestack] Fast access to the unsafe stack pointer on AArch64/Android."Evgeniy Stepanov2015-10-151-34/+0
| | | | | | Breaks the hexagon buildbot. llvm-svn: 250461
* Replace a forward declaration with an #include.Adrian Prantl2015-10-151-1/+2
| | | | | | | When building with modules the forward-declared inner class DebugLocStream::ListBuilder causes clang to fall over. llvm-svn: 250459
* [safestack] Fast access to the unsafe stack pointer on AArch64/Android.Evgeniy Stepanov2015-10-151-0/+34
| | | | | | | | | | | | | | | | Android libc provides a fixed TLS slot for the unsafe stack pointer, and this change implements direct access to that slot on AArch64 via __builtin_thread_pointer() + offset. This change also moves more code into TargetLowering and its target-specific subclasses to get rid of target-specific codegen in SafeStackPass. This change does not touch the ARM backend because ARM lowers builting_thread_pointer as aeabi_read_tp, which is not available on Android. llvm-svn: 250456
* [SelectionDAG] Remove dead code. NFC.Benjamin Kramer2015-10-156-139/+1
| | | | | | Carefully selected parts without deleting graph stuff and dumping methods. llvm-svn: 250434
* [AsmPrinter] Prune dead code. NFC.Benjamin Kramer2015-10-156-111/+0
| | | | | | I left all (dead) print and dump methods in place. llvm-svn: 250433
* A doccomment for CombineTo, and some NFC refactoringsArtyom Skrobov2015-10-141-39/+34
| | | | | | | | | | | | | | Summary: Caching SDLoc(N), instead of recreating it in every single function call, keeps the code denser, and allows to unwrap long lines. Reviewers: sunfish, atrick, sdmitrouk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13726 llvm-svn: 250305
* Merge DAGCombiner::visitSREM and DAGCombiner::visitUREM (NFC)Artyom Skrobov2015-10-141-66/+34
| | | | | | | | | | | | Summary: The two implementations had more code in common than not. Reviewers: sunfish, MatzeB, sdmitrouk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13724 llvm-svn: 250302
* [WinEH] Add CoreCLR EH table emissionJoseph Tremoulet2015-10-132-3/+282
| | | | | | | | | | | | | | | | | | Summary: Emit the handler and clause locations immediately after the standard xdata. Clauses are emitted in the same order and format used to communiate them to the CLR Execution Engine. Add a lit test to verify correct table generation on a small but interesting example function. Reviewers: majnemer, andrew.w.kaylor, rnk Subscribers: pgavlin, AndyAyers, llvm-commits Differential Revision: http://reviews.llvm.org/D13451 llvm-svn: 250219
* SelectionDAG: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-138-50/+50
| | | | llvm-svn: 250214
* [WinEH] Iterate state changes instead of invokesJoseph Tremoulet2015-10-132-151/+196
| | | | | | | | | | | | | | | | | | | | | | Summary: Add an iterator that can walk across blocks and which visits the state transitions rather than state ranges, with explicit transitions to -1 indicating the presence of top-level calls that may throw and cause the current function to unwind to caller. This will simplify code that needs to identify nested try regions. Refactor SEH and C++EH table generation to use the new InvokeStateChangeIterator, and remove the InvokeLabelIterator they were using. Reviewers: majnemer, andrew.w.kaylor, rnk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13623 llvm-svn: 250179
* DAGCombiner: Don't stop finding better chain on 2 aliasesMatt Arsenault2015-10-131-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The comment says this was stopped because it was unlikely to be profitable. This is not true if you want to combine vector loads with multiple components. For a simple case that looks like t0 = load t0 ... t1 = load t0 ... t2 = load t0 ... t3 = load t0 ... t4 = store t0:1, t0:1 t5 = store t4, t1:0 t6 = store t5, t2:0 t7 = store t6, t3:0 We want to get all of these stores onto a chain that is a TokenFactor of these N loads. This mostly solves the AMDGPU merge-stores.ll regressions with -combiner-alias-analysis for merging vector stores of vector loads. llvm-svn: 250138
* DAGCombiner: Combine extract_vector_elt from build_vectorMatt Arsenault2015-10-121-5/+20
| | | | | | | | | | | | | | This basic combine was surprisingly missing. AMDGPU legalizes many operations in terms of 32-bit vector components, so not doing this results in many extra copies and subregister extracts that need to be cleaned up later. InstCombine already does this for the hasOneUse case. The target hook is to fix a handful of tests which break (e.g. ARM/vmov.ll) which turn from a vector materialize repeated immediate instruction to a constant vector load with more scalar copies from it. llvm-svn: 250129
* Assign correct edge weights to unwind destinations when lowering invoke ↵Cong Hou2015-10-121-27/+46
| | | | | | | | | | statement. When lowering invoke statement, all unwind destinations are directly added as successors of call site block, and the weight of those new edges are not assigned properly. Actually, default weight 16 are used for those edges. This patch calculates the proper edge weights for those edges when collecting all unwind destinations. Differential revision: http://reviews.llvm.org/D13354 llvm-svn: 250119
* [SelectionDAG] Add common vector constant folding helper functionSimon Pilgrim2015-10-122-101/+95
| | | | | | | | | | | | We have a number of functions that implement constant folding of vectors (unary and binary ops) in near identical manners (and the differences don't appear to be critical). This patch introduces a common implementation (SelectionDAG::FoldConstantVectorArithmetic) and calls this in both the unary and binary op cases. After this initial patch I intend to begin enabling vector constant folding for a wider number of opcodes in SelectionDAG::getNode(). Differential Revision: http://reviews.llvm.org/D13665 llvm-svn: 250118
* Enable verifier after PeepholeOptimizerMatt Arsenault2015-10-121-1/+1
| | | | | | | No tests fail with this enabled so I assume it was an accident that it isn't enabled now. llvm-svn: 250070
* Don't call PrepareEHLandingPad on non EH padsReid Kleckner2015-10-121-2/+3
| | | | | | | | This was a minor bug in r249492. Calling PrepareEHLandingPad on a non-landingpad was a no-op, but it attempted to get the generic pointer register class, which apparently doesn't exist for some targets. llvm-svn: 250068
* [WinEH] Remove CatchObjRecoverIdxDavid Majnemer2015-10-123-15/+5
| | | | | | | CatchObjRecoverIdx was used for the old scheme, it is no longer relevant. llvm-svn: 250065
* [Debug] Look through bitcasts to find argument registersOliver Stannard2015-10-121-19/+13
| | | | | | | | | | On targets where f32 is not legal, we have to look through a BITCAST SDNode to find the register that an argument is stored in when emitting debug info, or we will not be able to emit a DW_AT_location for it. Differential Revision: http://reviews.llvm.org/D13005 llvm-svn: 250056
* [DAGCombiner] Improved FMA combine support for vectorsSimon Pilgrim2015-10-111-33/+36
| | | | | | | | Enabled constant canonicalization for all constants. Improved combining of constant vectors. llvm-svn: 249993
* [DAGCombiner] Tidyup FMINNUM/FMAXNUM constant foldingSimon Pilgrim2015-10-111-14/+14
| | | | | | | | Enable constant folding for vector splats as well as scalars. Enable constant canonicalization for all scalar and vector constants. llvm-svn: 249978
OpenPOWER on IntegriCloud