summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
* If known DebugLocs do not match then two DBG_VALUE machine instructions are ↵Devang Patel2011-07-071-0/+5
| | | | | | | | | | | not identical. For example, DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:32:10 ] DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:31:10 ] These two MIs represent identical value, 3.31..., for one variable, ds, but they are not identical because the represent two separate instances of inlined variable "ds". llvm-svn: 134620
* Add functions 'hasPredecessor' and 'hasPredecessorHelper' to SDNode. TheLang Hames2011-07-072-16/+36
| | | | | | | | | | | | | | | | hasPredecessorHelper function allows predecessors to be cached to speed up repeated invocations. This fixes PR10186. X.isPredecessorOf(Y) now just calls Y.hasPredecessor(X) Y.hasPredecessor(X) calls Y.hasPredecessorHelper(X, Visited, Worklist) with empty Visited and Worklist sets (i.e. no caching over invocations). Y.hasPredecessorHelper(X, Visited, Worklist) caches search state in Visited and Worklist to speed up repeated calls. The Visited set is searched for X before going to the worklist to further search the DAG if necessary. llvm-svn: 134592
* Add DEBUG messages.Devang Patel2011-07-071-2/+9
| | | | llvm-svn: 134572
* When tail-merging multiple blocks, make sure to correctly update the live-in ↵Eli Friedman2011-07-062-10/+23
| | | | | | | | | | list on the merged block to correctly account for the live-outs of all the predecessors. They might not be the same in all cases (the testcase I have involves a PHI node where one of the operands is an IMPLICIT_DEF). Unfortunately, the testcase I have is large and confidential, so I don't have a test to commit at the moment; I'll see if I can come up with something smaller where this issue reproduces. <rdar://problem/9716278> llvm-svn: 134565
* Remove dead code.Devang Patel2011-07-061-2/+0
| | | | llvm-svn: 134561
* Typo.Devang Patel2011-07-061-1/+1
| | | | llvm-svn: 134559
* Grammar and 80-col.Eric Christopher2011-07-061-7/+7
| | | | llvm-svn: 134555
* createMCInstPrinter doesn't need TargetMachine anymore.Evan Cheng2011-07-062-1/+2
| | | | llvm-svn: 134525
* Introduce "expect" intrinsic instructions.Jakub Staszak2011-07-062-0/+14
| | | | llvm-svn: 134516
* Remove the ObjC ARC passes from the default optimization list, and addDan Gohman2011-07-051-4/+0
| | | | | | extension points to be used by clang. llvm-svn: 134444
* Break infinite loop when the Hopfield network oscillates.Jakob Stoklund Olesen2011-07-051-8/+6
| | | | | | | | | | This is impossible in theory, I can prove it. In practice, our near-zero threshold can cause the network to oscillate between equally good solutions. <rdar://problem/9720596> llvm-svn: 134428
* Fix PR10277.Jakob Stoklund Olesen2011-07-052-0/+7
| | | | | | | | | | | | | | | Remat during spilling triggers dead code elimination. If a phi-def becomes unused, that may also cause live ranges to split into separate connected components. This type of splitting is different from normal live range splitting. In particular, there may not be a common original interval. When the split range is its own original, make sure that the new siblings are also their own originals. The range being split cannot be used as an original since it doesn't cover the new siblings. llvm-svn: 134413
* Tweak comment and debug output.Jakob Stoklund Olesen2011-07-051-2/+3
| | | | llvm-svn: 134412
* Move early tail duplication earlier.Rafael Espindola2011-07-041-6/+6
| | | | | | | | | | | | | | This fixes the issue noted in PR10251 where early tail dup of bbs with indirectbr would cause a bb to be duplicated into a loop preheader and then into its predecessors, creating phi nodes with identical operands just before register allocation. This helps with jsinterp.o size (__TEXT goes from 163568 to 126656) and a bit with performance 1.005x faster on sunspider (jits still enabled). The result on webkit with the jit disabled is more significant: 1.021x faster. llvm-svn: 134372
* Move most of the pre BB code to TailDuplicateAndUpdate. Change theRafael Espindola2011-07-041-112/+125
| | | | | | HasIndirectbr variable to be just that. No functionality change. llvm-svn: 134371
* Reduce indentation and fix the count of how many PHIs we have inserted.Rafael Espindola2011-07-041-75/+80
| | | | llvm-svn: 134370
* Fix PR10244.Jakob Stoklund Olesen2011-07-041-4/+4
| | | | | | | | | | | | A split point inserted in a block with a landing pad successor may be hoisted above the call to ensure that it dominates all successors. The code that handles the rest of the basic block must take this into account. I am not including a test case, it would be very fragile. PR10244 comes from building clang with exceptions enabled. llvm-svn: 134369
* Fix an easy fixme.Rafael Espindola2011-07-031-6/+10
| | | | llvm-svn: 134364
* Use getVNInfoAt.Rafael Espindola2011-07-021-2/+1
| | | | llvm-svn: 134312
* Better diagnostics when inline asm fails to allocate.Jakob Stoklund Olesen2011-07-022-22/+18
| | | | | | | | asm.c:2:7: error: ran out of registers during register allocation asm(""::"r"(0), "r"(1), "r"(2), "r"(3), "r"(4), "r"(5), "r"(6), "r"(7), "r"(8), "r"(9)); ^ llvm-svn: 134310
* Check the VN of the src register at the two copies, not just theRafael Espindola2011-07-021-1/+6
| | | | | | register number. llvm-svn: 134309
* Include a source location when complaining about bad inline assembly.Jakob Stoklund Olesen2011-07-021-0/+24
| | | | | | | | | | | | | | | | Add a MI->emitError() method that the backend can use to report errors related to inline assembly. Call it from X86FloatingPoint.cpp when the constraints are wrong. This enables proper clang diagnostics from the backend: $ clang -c pr30848.c pr30848.c:5:12: error: Inline asm output regs must be last on the x87 stack __asm__ ("" : "=u" (d)); /* { dg-error "output regs" } */ ^ 1 error generated. llvm-svn: 134307
* Use a new strategy for preventing eviction loops in RAGreedy.Jakob Stoklund Olesen2011-07-021-57/+74
| | | | | | | | | | | | | | | | | | | Every live range is assigned a cascade number the first time it is involved in an eviction. As the evictor, it gets a new cascade number. Every evictee is assigned the same cascade number as the evictor. Eviction is prohibited if the evictor has a lower assigned cascade number than the evictee. This means that assigned cascade numbers are monotonically increasing with every eviction, yet they are bounded by NextCascade which can only be incremented by new live ranges. Thus, infinite loops cannot happen, but eviction cascades can still be triggered by new live ranges as we want. Thanks to Andy for explaining this to me. llvm-svn: 134303
* Take a stab at fixing the llvm-x86_64-linux-checks failure.Cameron Zwarich2011-07-011-0/+2
| | | | llvm-svn: 134287
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-015-20/+21
| | | | llvm-svn: 134259
* Disable commit 134216 ("Add 134199 back, but disable the optimization when ↵Duncan Sands2011-07-011-0/+1
| | | | | | | | | the second copy is a kill") to see if it fixes the i386 dragonegg buildbot, which is timing out because gcc built with dragonegg is going into an infinite loop. llvm-svn: 134237
* Avoid DenseMap lookup.Rafael Espindola2011-07-011-6/+8
| | | | llvm-svn: 134231
* Fix off by one error. I misunderstood the comment about killedAt.Rafael Espindola2011-07-011-1/+1
| | | | llvm-svn: 134229
* Check the liveinterval, not the kill flag.Rafael Espindola2011-07-011-7/+10
| | | | llvm-svn: 134228
* Don't inflate register classes used by inline asm.Jakob Stoklund Olesen2011-07-011-0/+3
| | | | | | | | | | | | The constraints are represented by the register class of the original virtual register created for the inline asm. If the register class were included in the operand descriptor, we might be able to do this. For now, just give up on regclass inflation when inline asm is involved. No test case, this bug hasn't happened yet. llvm-svn: 134226
* Add 134199 back, but disable the optimization when the second copy is a kill.Rafael Espindola2011-07-011-10/+100
| | | | llvm-svn: 134216
* Revert my previous patch while I debug llvm-gcc bootstrap.Rafael Espindola2011-06-301-95/+10
| | | | llvm-svn: 134201
* Don't give up on coalescing A and B when we findRafael Espindola2011-06-301-10/+95
| | | | | | | | | | | | A = X B = X Instead, proceed as if we had found A = X B = A llvm-svn: 134199
* Create a isFullCopy predicate.Rafael Espindola2011-06-301-5/+1
| | | | llvm-svn: 134189
* Remove dead code.Rafael Espindola2011-06-301-88/+0
| | | | llvm-svn: 134148
* Reapply r134047 now that the world is ready for it.Jakob Stoklund Olesen2011-06-303-138/+291
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch will sometimes choose live range split points next to interference instead of always splitting next to a register point. That means spill code can now appear almost anywhere, and it was necessary to fix code that didn't expect that. The difficult places were: - Between a CALL returning a value on the x87 stack and the corresponding FpPOP_RETVAL (was FpGET_ST0). Probably also near x87 inline assembly, but that didn't actually show up in testing. - Between a CALL popping arguments off the stack and the corresponding ADJCALLSTACKUP. Both are fixed now. The only place spill code can't appear is after terminators, see SplitAnalysis::getLastSplitPoint. Original commit message: Rewrite RAGreedy::splitAroundRegion, now with cool ASCII art. This function has to deal with a lot of special cases, and the old version got it wrong sometimes. In particular, it would sometimes leave multiple uses in the stack interval in a single block. That causes bad code with multiple reloads in the same basic block. The new version handles block entry and exit in a single pass. It first eliminates all the easy cases, and then goes on to create a local interval for the blocks with difficult interference. Previously, we would only create the local interval for completely isolated blocks. It can happen that the stack interval becomes completely empty because we could allocate a register in all edge bundles, and the new local intervals deal with the interference. The empty stack interval is harmless, but we need to remove a SplitKit assertion that checks for empty intervals. llvm-svn: 134125
* Remove getRegClassForInlineAsmConstraint and all dependencies.Eric Christopher2011-06-302-108/+0
| | | | | | Fixes rdar://9643582 llvm-svn: 134123
* Revert r133953 for now.Devang Patel2011-06-292-24/+0
| | | | llvm-svn: 134116
* make compose and isMoveInstr static functions.Rafael Espindola2011-06-292-16/+10
| | | | llvm-svn: 134093
* Revert a part of r126557 which could create unschedulable DAGs.Benjamin Kramer2011-06-291-32/+0
| | | | llvm-svn: 134067
* Revert r134047 while investigating a llvm-gcc-i386-linux-selfhostJakob Stoklund Olesen2011-06-293-291/+138
| | | | | | miscompile. llvm-svn: 134053
* Sink SubtargetFeature and TargetInstrItineraries (renamed ↵Evan Cheng2011-06-295-3/+5
| | | | | | MCInstrItineraries) into MC. llvm-svn: 134049
* Rewrite RAGreedy::splitAroundRegion, now with cool ASCII art.Jakob Stoklund Olesen2011-06-293-138/+291
| | | | | | | | | | | | | | | | | | | | This function has to deal with a lot of special cases, and the old version got it wrong sometimes. In particular, it would sometimes leave multiple uses in the stack interval in a single block. That causes bad code with multiple reloads in the same basic block. The new version handles block entry and exit in a single pass. It first eliminates all the easy cases, and then goes on to create a local interval for the blocks with difficult interference. Previously, we would only create the local interval for completely isolated blocks. It can happen that the stack interval becomes completely empty because we could allocate a register in all edge bundles, and the new local intervals deal with the interference. The empty stack interval is harmless, but we need to remove a SplitKit assertion that checks for empty intervals. llvm-svn: 134047
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-281-4/+6
| | | | llvm-svn: 134030
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-2827-257/+258
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Print registers by name instead of by number.Jakob Stoklund Olesen2011-06-281-6/+7
| | | | llvm-svn: 134013
* Fix CMake build by removing this now dead file.Chandler Carruth2011-06-281-1/+0
| | | | llvm-svn: 133981
* Fix a bad iterator dereference that Evan uncovered.Jakob Stoklund Olesen2011-06-281-2/+4
| | | | llvm-svn: 133978
* Remove RegClass2VRegMap from MachineRegisterInfo.Evan Cheng2011-06-271-14/+0
| | | | llvm-svn: 133967
* Remove the experimental (and unused) pre-ra splitting pass. Greedy regalloc ↵Evan Cheng2011-06-273-1440/+0
| | | | | | can split live ranges. llvm-svn: 133962
OpenPOWER on IntegriCloud