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* [RegisterBank] Implement the verify method to check for the obvious mistakes.Quentin Colombet2016-04-051-4/+27
| | | | llvm-svn: 265479
* [RegisterBankInfo] Add debug print to check how the initialization is going.Quentin Colombet2016-04-051-0/+11
| | | | llvm-svn: 265475
* [RegisterBank] Add printable capabilities for future debugging.Quentin Colombet2016-04-051-0/+34
| | | | llvm-svn: 265473
* [RegisterBankInfo] Make addRegBankCoverage more capable to easeQuentin Colombet2016-04-051-4/+67
| | | | | | | | targeting jobs. Now, addRegBankCoverage also adds the subreg-classes not just the sub-classes of the given register class. llvm-svn: 265469
* [RegisterBankInfo] Implement the methods to create register banks.Quentin Colombet2016-04-051-4/+77
| | | | llvm-svn: 265464
* [RegisterBank] Provide a way to check if a register bank is valid.Quentin Colombet2016-04-051-1/+12
| | | | | | | | Change the default constructor to create invalid object. The target will have to properly initialize the register banks before using them. llvm-svn: 265460
* [GlobalISel] Add the RegisterBankInfo class for the handling of register banks.Quentin Colombet2016-04-052-0/+29
| | | | llvm-svn: 265449
* [GlobalISel] Add a class, RegisterBank, to represent register banks.Quentin Colombet2016-04-052-0/+40
| | | | llvm-svn: 265445
* [GlobalISel] Add the skeleton of the RegBankSelect pass.Quentin Colombet2016-04-053-0/+34
| | | | | | | This pass is reponsible for assigning the generic virtual registers to register banks. llvm-svn: 265440
* Swift Calling Convention: swifterror target-independent change.Manman Ren2016-04-055-4/+353
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At IR level, the swifterror argument is an input argument with type ErrorObject**. For targets that support swifterror, we want to optimize it to behave as an inout value with type ErrorObject*; it will be passed in a fixed physical register. The main idea is to track the virtual registers for each swifterror value. We define swifterror values as AllocaInsts with swifterror attribute or a function argument with swifterror attribute. In SelectionDAGISel.cpp, we set up swifterror values (SwiftErrorVals) before handling the basic blocks. When iterating over all basic blocks in RPO, before actually visiting the basic block, we call mergeIncomingSwiftErrors to merge incoming swifterror values when there are multiple predecessors or to simply propagate them. There, we create a virtual register for each swifterror value in the entry block. For predecessors that are not yet visited, we create virtual registers to hold the swifterror values at the end of the predecessor. The assignments are saved in SwiftErrorWorklist and will be materialized at the end of visiting the basic block. When visiting a load from a swifterror value, we copy from the current virtual register assignment. When visiting a store to a swifterror value, we create a virtual register to hold the swifterror value and update SwiftErrorMap to track the current virtual register assignment. Differential Revision: http://reviews.llvm.org/D18108 llvm-svn: 265433
* [BlockPlacement] Remove an unnecessary continueHaicheng Wu2016-04-051-1/+0
| | | | | | NFC. llvm-svn: 265407
* Don't delete empty preheaders in CodeGenPrepare if it would create a ↵Chuang-Yu Cheng2016-04-051-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | critical edge Presently, CodeGenPrepare deletes all nearly empty (only phi and branch) basic blocks. This pass can delete loop preheaders which frequently creates critical edges. A preheader can be a convenient place to spill registers to the stack. If the entrance to a loop body is a critical edge, then spills may occur in the loop body rather than immediately before it. This patch protects loop preheaders from deletion in CodeGenPrepare even if they are nearly empty. Since the patch alters the CFG, it affects a large number of test cases. In most cases, the changes are merely cosmetic (basic blocks have different names or instruction orders change slightly). I am somewhat concerned about the test/CodeGen/Mips/brdelayslot.ll test case. If the loop preheader is not deleted, then the MIPS backend does not take advantage of a branch delay slot. Consequently, I would like some close review by a MIPS expert. The patch also partially subsumes D16893 from George Burgess IV. George correctly notes that CodeGenPrepare does not actually preserve the dominator tree. I think the dominator tree was usually not valid when CodeGenPrepare ran, but I am using LoopInfo to mark preheaders, so the dominator tree is now always valid before CodeGenPrepare. Author: Tom Jablin (tjablin) Reviewers: hfinkel george.burgess.iv vkalintiris dsanders kbarton cycheng http://reviews.llvm.org/D16984 llvm-svn: 265397
* [IFUNC] Use GlobalIndirectSymbol when aliases and ifuncs have something similarDmitry Polukhin2016-04-051-39/+44
| | | | | | | | | | | Second part extracted from http://reviews.llvm.org/D15525 Use GlobalIndirectSymbol in all cases when aliases and ifuncs have something in common. Differential Revision: http://reviews.llvm.org/D18754 llvm-svn: 265382
* fix typos; NFCSanjay Patel2016-04-041-2/+2
| | | | llvm-svn: 265356
* Revert "CodeGen: Remove dead code in TailDuplicate"Justin Bogner2016-04-041-14/+58
| | | | | | | | | | | It seems this is reachable after all. It hit on 7zip-benchmark in lnt on ppc64: http://lab.llvm.org:8011/builders/clang-ppc64be-linux-lnt/builds/2317 This reverts r265347. llvm-svn: 265352
* MachineScheduler: Ignore COPYs with undef/dead op in CopyConstrain mutation.Matthias Braun2016-04-041-4/+6
| | | | | | | | There is no problem with the code today, but the fix will avoid a crash in test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll once the DetectDeadLanes pass is added. llvm-svn: 265351
* CodeGen: Remove dead code in TailDuplicateJustin Bogner2016-04-041-58/+14
| | | | | | | | | | | | | | | | I noticed that this isn't covered by our existing tests and spent some time trying to come up with an example it actually hits. I tried hand rolling something based on the explanation in the comment, but couldn't get anything that didn't abort tail duplication earlier for one reason or another. Then, I tried cranking tail-dup-size cranked up so this would fire more and ran a bootstrap of clang and the nightly test suite - those don't hit this either. This reverts r132816 and replaces it with an assert. llvm-svn: 265347
* Revert r263460: [SpillPlacement] Fix a quadratic behavior in spill placement.Chandler Carruth2016-04-042-44/+53
| | | | | | | | | | | | | | | | | That commit looks wonderful and awesome. Sadly, it greatly exacerbates PR17409 and effectively regresses build time for a lot of (very large) code when compiled with ASan or MSan. We thought this could be fixed forward by landing D15302 which at last fixes that PR, but some issues were discovered and it looks like that got reverted, so reverting this as well temporarily. As soon as the fix for PR17409 lands and sticks, we should re-land this patch as it won't trigger more significant test cases hitting that bug. Many thanks to Quentin and Wei here as they're doing all the awesome hard work!!! llvm-svn: 265331
* ARM, AArch64, X86: Check preserved registers for tail calls.Matthias Braun2016-04-041-0/+9
| | | | | | | | | | | | | | | | We can only perform a tail call to a callee that preserves all the registers that the caller needs to preserve. This situation happens with calling conventions like preserver_mostcc or cxx_fast_tls. It was explicitely handled for fast_tls and failing for preserve_most. This patch generalizes the check to any calling convention. Related to rdar://24207743 Differential Revision: http://reviews.llvm.org/D18680 llvm-svn: 265329
* Replace MachineRegisterInfo::isSSA() with a MachineFunctionPropertyDerek Schuff2016-04-042-17/+15
| | | | | | | | | Use the MachineFunctionProperty mechanism to indicate whether a MachineFunction is in SSA form instead of a custom method on MachineRegisterInfo. NFC Differential Revision: http://reviews.llvm.org/D18574 llvm-svn: 265318
* Revert r265309 and r265312 because they caused some errors I need to ↵Wei Mi2016-04-0410-715/+527
| | | | | | investigate. llvm-svn: 265317
* Add MachineFunctionProperty checks for AllVRegsAllocated for target passesDerek Schuff2016-04-042-0/+10
| | | | | | | | | | | | | | Summary: This adds the same checks that were added in r264593 to all target-specific passes that run after register allocation. Reviewers: qcolombet Subscribers: jyknight, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18525 llvm-svn: 265313
* Fix unused var warning caused by r265309.Wei Mi2016-04-041-3/+3
| | | | llvm-svn: 265312
* Replace analyzeSiblingValues with new algorithm to fix its compileWei Mi2016-04-0410-526/+714
| | | | | | | | | | | | | | | | | | | | | | | | | time issue. The patch is to solve PR17409 and its duplicates. analyzeSiblingValues is a N x N complexity algorithm where N is the number of siblings generated by reg splitting. Although it causes siginificant compile time issue when N is large, it is also important for performance since it removes redundent spills and enables rematerialization. To solve the compile time issue, the patch removes analyzeSiblingValues and replaces it with lower cost alternatives containing two parts. The first part creates a new spill hoisting method in postOptimization of register allocation. It does spill hoisting at once after all the spills are generated instead of inside every instance of selectOrSplit. The second part queries the define expr of the original register for rematerializaiton and keep it always available during register allocation even if it is already dead. It deletes those dead instructions only in postOptimization. With the two parts in the patch, it can remove analyzeSiblingValues without sacrificing performance. Differential Revision: http://reviews.llvm.org/D15302 llvm-svn: 265309
* [CodeGenPrepare] Fix r265264 (again).Peter Zotov2016-04-031-3/+3
| | | | | | | Don't require TLI for SinkCmpExpression, like it wasn't before r265264. llvm-svn: 265271
* [CodeGenPrepare] Fix r265264.Peter Zotov2016-04-031-3/+3
| | | | | | | The case where there was no TargetLowering was not handled, leading to null pointer dereferences. llvm-svn: 265265
* [CodeGenPrepare] Avoid sinking soft-FP comparisonsPeter Zotov2016-04-031-5/+9
| | | | | | | | | | | | | | | Sinking comparisons in CGP can undo the job of hoisting them done earlier by LICM, and soft-FP makes this an expensive mistake. A common pattern that produces floating point comparisons uniform over a loop is an explicit check for division by zero. If the divisor is hoisted out of the loop, the comparison can also be, but hoisting the function that unwinds is never legal, since it may cause side effects in the loop body prior to the unwinding to not be executed. Differential Revision: http://reviews.llvm.org/D18744 llvm-svn: 265264
* Swift Calling Convention: add swifterror attribute.Manman Ren2016-04-013-0/+9
| | | | | | | | | | | | A ``swifterror`` attribute can be applied to a function parameter or an AllocaInst. This commit does not include any target-specific change. The target-specific optimization will come as a follow-up patch. Differential Revision: http://reviews.llvm.org/D18092 llvm-svn: 265189
* Don't use an i64 return type with webkit_jsccSanjoy Das2016-04-011-6/+7
| | | | | | | | | Re-enable an assertion enabled by Justin Lebar in rL265092. rL265092 was breaking test/CodeGen/X86/deopt-intrinsic.ll because webkit_jscc does not like non-i64 return types. Change the test case to not do that. llvm-svn: 265099
* Fix Sub-register Rewriting in Aggressive Anti-Dependence BreakerChuang-Yu Cheng2016-04-011-13/+16
| | | | | | | | | | | | | | | | | | | Previously, HandleLastUse would delete RegRef information for sub-registers if they were dead even if their corresponding super-register were still live. If the super-register were later renamed, then the definitions of the sub-register would not be updated appropriately. This patch alters the behavior so that RegInfo information for sub-registers is only deleted when the sub-register and super-register are both dead. This resolves PR26775. This is the mirror image of Hal's r227311 commit. Author: Tom Jablin (tjablin) Reviewers: kbarton uweigand nemanjai hfinkel http://reviews.llvm.org/D18448 llvm-svn: 265097
* Revert "Protect some assertions with NDEBUG rather than DEBUG()."Justin Lebar2016-04-011-7/+6
| | | | | | This reverts r265092, because it breaks CodeGen/X86/deopt-intrinsic.ll. llvm-svn: 265093
* Protect some assertions with NDEBUG rather than DEBUG().Justin Lebar2016-04-011-6/+7
| | | | | | | DEBUG() only runs if you pass -debug, but these assertions are generally useful. llvm-svn: 265092
* [ifcnv] Add brief comment explaining what ifcnv is.Justin Lebar2016-04-011-1/+2
| | | | llvm-svn: 265088
* Move the DebugEmissionKind enum from DIBuilder into DICompileUnit.Adrian Prantl2016-03-312-3/+2
| | | | | | | | | | | | | This mostly cosmetic patch moves the DebugEmissionKind enum from DIBuilder into DICompileUnit. DIBuilder is not the right place for this enum to live in — a metadata consumer should not have to include DIBuilder.h. I also added a Verifier check that checks that the emission kind of a DICompileUnit is actually legal. http://reviews.llvm.org/D18612 <rdar://problem/25427165> llvm-svn: 265077
* [AsmPrinter] Print aliases in topological orderTim Shen2016-03-311-1/+18
| | | | | | | | | | Print aliases in topological order, that is, for any alias a = b, b must be printed before a. This is because on some targets (e.g. PowerPC) linker expects aliases in such an order to generate correct TOC information. GCC also prints aliases in topological order. llvm-svn: 265064
* Fix PR26940 where compiles times regressed massively.Chandler Carruth2016-03-311-33/+30
| | | | | | | | | | | | | | | Patch by Jonas Paulsson. Original description: Bugfix in buildSchedGraph() to make -dag-maps-huge-region work properly I found that the reduction of the maps did in fact never happen in this test case. This was because *all* the stores / loads were made with addresses from arguments and they thus became "unknown" stores / loads. Fixed by removing continue statements and making sure that the test for reduction always takes place. Differential Revision: http://reviews.llvm.org/D18673 llvm-svn: 265063
* fix typo; NFCSanjay Patel2016-03-311-2/+1
| | | | llvm-svn: 265054
* Change eliminateCallFramePseudoInstr() to return an iteratorHans Wennborg2016-03-311-9/+1
| | | | | | | | | | | | | | | | | | | | | This will become necessary in a subsequent change to make this method merge adjacent stack adjustments, i.e. it might erase the previous and/or next instruction. It also greatly simplifies the calls to this function from Prolog- EpilogInserter. Previously, that had a bunch of logic to resume iteration after the call; now it just continues with the returned iterator. Note that this changes the behaviour of PEI a little. Previously, it attempted to re-visit the new instruction created by eliminateCallFramePseudoInstr(). That code was added in r36625, but I can't see any reason for it: the new instructions will obviously not be pseudo instructions, they will not have FrameIndex operands, and we have already accounted for the stack adjustment. Differential Revision: http://reviews.llvm.org/D18627 llvm-svn: 265036
* Don't use potentially invalidated iteratorStephan Bergmann2016-03-311-2/+4
| | | | | | | | | | | | If the lhs is evaluated before the rhs, FuncletI's operator-> can trigger the assert(isHandleInSync() && "invalid iterator access!"); at include/llvm/ADT/DenseMap.h:1061. (Happens e.g. when compiled with GCC 6.) Differential Revision: http://reviews.llvm.org/D18440 llvm-svn: 265024
* Prevent X86ISelLowering from merging volatile loadsNirav Dave2016-03-312-14/+9
| | | | | | | | | | | | | Change isConsecutiveLoads to check that loads are non-volatile as this is a requirement for any load merges. Propagate change to two callers. Reviewers: RKSimon Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D18546 llvm-svn: 265013
* CodeGen: Factor out code for tail call result compatibility check; NFCMatthias Braun2016-03-301-0/+36
| | | | llvm-svn: 264959
* LegalizeDAG: Don't replace vector store with integer if not legalMatt Arsenault2016-03-303-41/+87
| | | | | | | | | | | For the same reason as the corresponding load change. Note that ExpandStore is completely broken for non-byte sized element vector stores, but preserve the current broken behavior which has tests for it. The behavior should be the same, but now introduces a new typed store that is incorrectly split later rather than doing it directly. llvm-svn: 264928
* LegalizeDAG: Don't replace vector load with integer unless legalMatt Arsenault2016-03-303-28/+71
| | | | | | | | | | | | | On AMDGPU we want to be able to promote i64/f64 loads to v2i32. If the access is unaligned, this would conclude that since i64 is legal, it would convert it back to i64 and there is an endless legalization loop. Extract the logic for scalarizing the load into a new TargetLowering function, where this can also replace the custom function AMDGPU has for this. llvm-svn: 264927
* MachineSink: make shouldSink a TII target hookFiona Glaser2016-03-291-7/+2
| | | | | | | Some targets may disagree on what they want sunk or not sunk, so make this a target hook instead of hardcoded. llvm-svn: 264799
* Add a print method to MachineFunctionProperties for better error messagesDerek Schuff2016-03-292-2/+37
| | | | | | | | | This makes check failures much easier to understand. Make it empty (but leave it in the class) for NDEBUG builds. Differential Revision: http://reviews.llvm.org/D18529 llvm-svn: 264780
* MachineVerifier: On dead-def live segments, check that corresponding machine ↵Matthias Braun2016-03-291-3/+18
| | | | | | operand has a dead flag llvm-svn: 264769
* LiveVariables: Fix typo and shorten commentMatthias Braun2016-03-291-4/+2
| | | | llvm-svn: 264768
* Add support for no-jump-tablesNirav Dave2016-03-291-2/+7
| | | | | | | | | | | | | Add function soft attribute to the generation of Jump Tables in CodeGen as initial step towards clang support of gcc's no-jump-table support Reviewers: hans, echristo Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D18321 llvm-svn: 264756
* Add MachineVerifier check for AllVRegsAllocated MachineFunctionPropertyDerek Schuff2016-03-295-15/+20
| | | | | | | | | | | | | | | | | Summary: Check that any function that has the property set is free of virtual register operands. Also, it is actually VirtRegMap (and not the register allocators) that acutally remove the VReg operands (except for RegAllocFast). Reviewers: qcolombet Subscribers: MatzeB, llvm-commits, qcolombet Differential Revision: http://reviews.llvm.org/D18535 llvm-svn: 264755
* Swift Calling Convention: add swiftself attribute.Manman Ren2016-03-293-0/+9
| | | | | | Differential Revision: http://reviews.llvm.org/D17866 llvm-svn: 264754
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