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* [GlobalISel] Mark newly-created gvregs as having a bank.Ahmed Bougacha2016-07-192-3/+10
| | | | | | | | | | Also verify that we never try to set the size of a vreg associated to a register class. Report an error when we encounter that in MIR. Fix a testcase that hit that error and had a size for no reason. llvm-svn: 276012
* [GlobalISel] Simplify more RegClassOrRegBank is+get. NFC.Ahmed Bougacha2016-07-191-5/+3
| | | | llvm-svn: 276011
* AVX-512: Fixed BT instruction selection.Elena Demikhovsky2016-07-191-0/+4
| | | | | | | | | | | The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
* CodeGenPrep: use correct function to determine Global's alignment.Tim Northover2016-07-181-1/+1
| | | | | | | | | Elsewhere (particularly computeKnownBits) we assume that a global will be aligned to the value returned by Value::getPointerAlignment. This is used to boost the alignment on memcpy/memset, so any target-specific request can only increase that value. llvm-svn: 275866
* [X86] Accept SELECT op code for x86-64 fp128 typeChih-Hung Hsieh2016-07-181-0/+1
| | | | | | | | | | DAGTypeLegalizer::CanSkipSoftenFloatOperand should allow SELECT op code for x86_64 fp128 type for MME targets, so SoftenFloatOperand does not abort on SELECT op code. Differential Revision: http://reviews.llvm.org/D21758 llvm-svn: 275818
* [inlineasm] Propagate operand constraints to the backendSimon Dardis2016-07-182-5/+36
| | | | | | | | | | | | | | | | | | | | | | | | When SelectionDAGISel transforms a node representing an inline asm block, memory constraint information is not preserved. This can cause constraints to be broken when a memory offset is of the form: offset + frame index when the frame is resolved. By propagating the constraints all the way to the backend, targets can enforce memory operands of inline assembly to conform to their constraints. For MIPSR6, some instructions had their offsets reduced to 9 bits from 16 bits such as ll/sc. This becomes problematic when using inline assembly to perform atomic operations, as an offset can generated that is too big to encode in the instruction. Reviewers: dsanders, vkalintris Differential Review: https://reviews.llvm.org/D21615 llvm-svn: 275786
* [PM] Convert IVUsers analysis to new pass manager.Dehao Chen2016-07-161-1/+1
| | | | | | | | | | | | Summary: Convert IVUsers analysis to new pass manager. Reviewers: davidxl, silvas Subscribers: junbuml, sanjoy, llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D22434 llvm-svn: 275698
* IPRA: avoid double query to the map (NFC)Mehdi Amini2016-07-161-2/+3
| | | | llvm-svn: 275689
* MIParser: reject subregister indexes on physregsMatthias Braun2016-07-161-0/+2
| | | | llvm-svn: 275658
* ExpandPostRAPseudos should transfer implicit uses, not only implicit defsMichael Kuperstein2016-07-151-12/+8
| | | | | | | | | | | | | | | | | | | Previously, we would expand: %BL<def> = COPY %DL<kill>, %EBX<imp-use,kill>, %EBX<imp-def> Into: %BL<def> = MOV8rr %DL<kill>, %EBX<imp-def> Dropping the imp-use on the floor. That confused CriticalAntiDepBreaker, which (correctly) assumes that if an instruction defs but doesn't use a register, that register is dead immediately before the instruction - while in this case, the high lanes of EBX can be very much alive. This fixes PR28560. Differential Revision: https://reviews.llvm.org/D22425 llvm-svn: 275634
* CodeGen: avoid emitting unnecessary CFISaleem Abdulrasool2016-07-151-4/+5
| | | | | | | | | | | | Remove unnecessary clutter in assembly output. When using SjLj EH, the CFI is not actually used for anything. Do not emit the CFI needlessly. The minor test adjustments are interesting. The prologue test was just overzealous matcching. The interesting case is the LSDA change. It was originally added to ensure that various compilations did not mangle the name (it explicitly checked the name!). However, subsequent cleanups made it more reliant on the CFI to find the name. Parse the generated code flow to generically find the label still. llvm-svn: 275614
* [MBP] Clean up of the comments, and a first attempt to better describe a partSjoerd Meijer2016-07-151-28/+49
| | | | | | | | of the algorithm. Differential Revision: https://reviews.llvm.org/D22364 llvm-svn: 275595
* [SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, ↵Justin Lebar2016-07-1512-607/+462
| | | | | | | | | | | | | | | | | | | | | | | getStore, and friends. Summary: Instead, we take a single flags arg (a bitset). Also add a default 0 alignment, and change the order of arguments so the alignment comes before the flags. This greatly simplifies many callsites, and fixes a bug in AMDGPUISelLowering, wherein the order of the args to getLoad was inverted. It also greatly simplifies the process of adding another flag to getLoad. Reviewers: chandlerc, tstellarAMD Subscribers: jholewinski, arsenm, jyknight, dsanders, nemanjai, llvm-commits Differential Revision: http://reviews.llvm.org/D22249 llvm-svn: 275592
* [CodeGen] Take a MachineMemOperand::Flags in ↵Justin Lebar2016-07-157-26/+19
| | | | | | | | | | | | | | | | | MachineFunction::getMachineMemOperand. Summary: Previously we took an unsigned. Hooray for type-safety. Reviewers: chandlerc Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D22282 llvm-svn: 275591
* Rename AnalyzeBranch* to analyzeBranch*.Jacques Pienaar2016-07-1510-38/+38
| | | | | | | | | | | | Summary: NFC. Rename AnalyzeBranch/AnalyzeBranchPredicate to analyzeBranch/analyzeBranchPredicate to follow LLVM coding style and be consistent with TargetInstrInfo's analyzeCompare and analyzeSelect. Reviewers: tstellarAMD, mcrosier Subscribers: mcrosier, jholewinski, jfb, arsenm, dschuff, jyknight, dsanders, nemanjai Differential Revision: https://reviews.llvm.org/D22409 llvm-svn: 275564
* [codeview] Shrink inlined call site line info tablesReid Kleckner2016-07-141-0/+3
| | | | | | | | | | | For a fully inlined call chain like a -> b -> c -> d, we were emitting line info for 'd' 3 separate times: once for d's actual InlineSite line table, and twice for 'b' and 'c'. This is particularly inefficient when all these functions are in different headers, because now we need to encode the file change. Windbg was coping with our suboptimal output, so this should not be noticeable from the debugger. llvm-svn: 275502
* Add debugging code to the packetizerKrzysztof Parzyszek2016-07-141-0/+25
| | | | llvm-svn: 275455
* [CodeGen] Refactor MachineMemOperand::Flags's target-specific flags.Justin Lebar2016-07-141-2/+0
| | | | | | | | | | | | | | | | | Summary: Make the target-specific flags in MachineMemOperand::Flags real, bona fide enum values. This simplifies users, prevents various constants from going out of sync, and avoids the false sense of security provided by declaring static members in classes and then forgetting to define them inside of cpp files. Reviewers: MatzeB Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22372 llvm-svn: 275451
* [CodeGen] Refactor MachineMemOperand's Flags enum.Justin Lebar2016-07-142-9/+13
| | | | | | | | | | | | | | | | | | | | | | | | Summary: - Give it a shorter name (because we're going to refer to it often from SelectionDAG and friends). - Split the flags and alignment into separate variables. - Specialize FlagsEnumTraits for it, so we can do bitwise ops on it without losing type information. - Make some enum values constants in MachineMemOperand instead. MOMaxBits should not be a valid Flag. - Simplify some of the bitwise ops for dealing with Flags. Reviewers: chandlerc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D22281 llvm-svn: 275438
* [GlobalISel] Fix #include ordering/spacing. NFC.Ahmed Bougacha2016-07-142-3/+2
| | | | llvm-svn: 275423
* Remove extra ';' to appease -WpedanticDean Michael Berris2016-07-141-1/+1
| | | | | | | | | Summary: Reviewers: dok Subscribers: llvm-commits llvm-svn: 275399
* XRay: Add entry and exit sledsDean Michael Berris2016-07-144-0/+99
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: In this patch we implement the following parts of XRay: - Supporting a function attribute named 'function-instrument' which currently only supports 'xray-always'. We should be able to use this attribute for other instrumentation approaches. - Supporting a function attribute named 'xray-instruction-threshold' used to determine whether a function is instrumented with a minimum number of instructions (IR instruction counts). - X86-specific nop sleds as described in the white paper. - A machine function pass that adds the different instrumentation marker instructions at a very late stage. - A way of identifying which return opcode is considered "normal" for each architecture. There are some caveats here: 1) We don't handle PATCHABLE_RET in platforms other than x86_64 yet -- this means if IR used PATCHABLE_RET directly instead of a normal ret, instruction lowering for that platform might do the wrong thing. We think this should be handled at instruction selection time to by default be unpacked for platforms where XRay is not availble yet. 2) The generated section for X86 is different from what is described from the white paper for the sole reason that LLVM allows us to do this neatly. We're taking the opportunity to deviate from the white paper from this perspective to allow us to get richer information from the runtime library. Reviewers: sanjoy, eugenis, kcc, pcc, echristo, rnk Subscribers: niravd, majnemer, atrick, rnk, emaste, bmakam, mcrosier, mehdi_amini, llvm-commits Differential Revision: http://reviews.llvm.org/D19904 llvm-svn: 275367
* MIRParser: Fix MIRParser not reporting nullptr on error.Matthias Braun2016-07-141-1/+1
| | | | | | | While some code paths in MIRParserImpl::parse() already returned nullptr in case of error one of the important ones did not. llvm-svn: 275355
* Add EnableIPRA to TargetOptions, and move the cl::opt -enable-ipra to ↵Mehdi Amini2016-07-132-8/+4
| | | | | | | | | | | | TargetMachine.cpp Avoid exposing a cl::opt in a public header and instead promote this option in the API. Alternatively, we could land the cl::opt in CommandFlags.h so that it is available to every tool, but we would still have to find an option for clang. llvm-svn: 275348
* [IPRA] Set callee saved registers to none for local function when IPRA is ↵Mehdi Amini2016-07-133-10/+29
| | | | | | | | | | | | | | | | | | | | enabled. IPRA try to optimize caller saved register by propagating register usage information from callee to caller so it is beneficial to have caller saved registers compare to callee saved registers when IPRA is enabled. Please find more detailed explanation here https://groups.google.com/d/msg/llvm-dev/XRzGhJ9wtZg/tjAJqb0eEgAJ. This change makes local function do not have any callee preserved register when IPRA is enabled. A simple test case is also added to verify this change. Patch by Vivek Pandya <vivekvpandya@gmail.com> Differential Revision: http://reviews.llvm.org/D21561 llvm-svn: 275347
* Fix copy/paste bug in r275340.Michael Kuperstein2016-07-131-1/+1
| | | | llvm-svn: 275343
* MIRParser: Move SlotMapping and SourceMgr refs to PFS; NFCMatthias Braun2016-07-133-88/+69
| | | | | | | | Code cleanup: Move references to SlotMapping and SourceMgr into the PerFunctionMIParsingState to avoid unnecessary passing around in parameters. llvm-svn: 275342
* [DAG] Correctly chain masked loadsMichael Kuperstein2016-07-131-9/+8
| | | | | | | | | If a masked loads is not added to the chain, it should not reset the chain's root. This fixes the remaining part of PR28515. llvm-svn: 275340
* [MI] Clean up some loops over MachineInstr::memoperands(). NFCJustin Lebar2016-07-131-14/+11
| | | | | | | Use range-based for loops and llvm::any_of instead of explicit iterators. llvm-svn: 275332
* [MI] Fix MachineInstr::isInvariantLoad.Justin Lebar2016-07-131-2/+1
| | | | | | | | | | | | | | | | | | | | Summary: Previously it would say we had an invariant load if any of the memory operands were invariant. But the load should be invariant only if *all* the memory operands are invariant. No testcase because this has proven to be very difficult to tickle in practice. As just one example, ARM's ldrd instruction, which loads 64 bits into two 32-bit regs, is theoretically affected by this. But when it's produced, it loses its memoperands' invariance bits! Reviewers: jfb Subscribers: llvm-commits, aemerson Differential Revision: http://reviews.llvm.org/D22318 llvm-svn: 275331
* MIRParser: Move MachineFunction reference into PFS; NFCMatthias Braun2016-07-133-141/+132
| | | | | | | | | | Code cleanup: The PerFunctionMIParsingState is per function, moving a reference into PFS we can avoid passing around the MachineFunction in an extra parameter most of the time. Also change most signatures to consistently pass PFS reference first. llvm-svn: 275329
* [MIR] Print on the given output instead of stderr.Quentin Colombet2016-07-131-1/+1
| | | | | | | | | | | | Currently the MIR framework prints all its outputs (errors and actual representation) on stderr. This patch fixes that by printing the regular output in the output specified with -o. Differential Revision: http://reviews.llvm.org/D22251 llvm-svn: 275314
* Reverting r275284 due to platform-specific test failuresAndrew Kaylor2016-07-132-47/+0
| | | | llvm-svn: 275304
* Fix for Bug 26903, adds support to inline __builtin_mempcpyAndrew Kaylor2016-07-132-0/+47
| | | | | | | | Patch by Sunita Marathe Differential Revision: http://reviews.llvm.org/D21920 llvm-svn: 275284
* PatchableFunction: Skip pseudos that do not create codeMatthias Braun2016-07-131-5/+23
| | | | | | This fixes http://llvm.org/PR28524 llvm-svn: 275278
* GlobalISel: freeze reserved regs after IRTranslator.Tim Northover2016-07-121-0/+5
| | | | | | | | | | We can freeze the registers after the MachineFrameInfo has been configured (by telling it about calls, inline asm, ...). This doesn't happen at all yet, but will be part of IR translation. Fixes -verify-machineinstrs assertion. llvm-svn: 275221
* BranchFolding: Use LivePhysReg to update live in lists.Matthias Braun2016-07-122-29/+30
| | | | | | | | | | | | | | | Use LivePhysRegs with a backwards walking algorithm to update live in lists, this way the results do not depend on the presence of kill flags anymore. This patch also reduces the number of registers added as live-in. Previously all pristine registers as well as all sub registers of a super register were added resulting in unnecessarily large live in lists. This fixed https://llvm.org/PR25263. Differential Revision: http://reviews.llvm.org/D22027 llvm-svn: 275201
* Fix printing of debugging information in LiveIntervals::shrinkToUsesKrzysztof Parzyszek2016-07-121-1/+1
| | | | | | | Print VNI->def before calling VNI->markUnused(), since markUnused makes the def invalid. llvm-svn: 275196
* Add print/dump routines to LiveInterval::SubRangeKrzysztof Parzyszek2016-07-121-10/+18
| | | | llvm-svn: 275194
* [codeview] Improved array type support.Amjad Aboud2016-07-124-33/+87
| | | | | | | | | | | | Added support for: 1. Multi dimension array. 2. Array of structure type, which previously was declared incompletely. 3. Dynamic size array. 4. Array where element type is a typedef, volatile or constant (this should resolve PR28311). Differential Revision: http://reviews.llvm.org/D21526 llvm-svn: 275167
* Codegen: Fix comment in BranchFolding.cppKyle Butt2016-07-111-7/+6
| | | | | | | | Blocks to be tail-merged may share more than one successor. Correct the comment to state that they share a specific successor, SuccBB, rather than a single successor, which is not true. llvm-svn: 275104
* fix documentation comments; NFCSanjay Patel2016-07-111-42/+7
| | | | llvm-svn: 275101
* [IPRA] Properly compute register usage at call sites.Chad Rosier2016-07-112-4/+6
| | | | | | | | Differential Revision: http://reviews.llvm.org/D21395 Patch by Vivek Pandya. PR28144 llvm-svn: 275087
* Provide support for preserving assembly commentsNirav Dave2016-07-111-0/+2
| | | | | | | | | | | | | | | | | Preserve assembly comments from input in output assembly and flags to toggle property. This is on by default for inline assembly and off in llvm-mc. Parsed comments are emitted immediately before an EOL which generally places them on the expected line. Reviewers: rtrieu, dwmw2, rnk, majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D20020 llvm-svn: 275058
* [DAG] make isConstantSplatVector() available to the rest of loweringSanjay Patel2016-07-102-32/+25
| | | | llvm-svn: 275025
* fix documentation comments; NFCSanjay Patel2016-07-101-11/+3
| | | | llvm-svn: 275021
* reformat, fix comments/names; NFCISanjay Patel2016-07-101-27/+22
| | | | llvm-svn: 275015
* Give helper classes/functions internal linkage. NFC.Benjamin Kramer2016-07-101-1/+1
| | | | llvm-svn: 275014
* [COFF, Dwarf] Don't emit DW_AT_location for dllimported entitiesDavid Majnemer2016-07-092-55/+66
| | | | | | | There exists no relocation which can describe the address of a dllimported variable: do not try to describe their location. llvm-svn: 274986
* fix documentation comments; NFCSanjay Patel2016-07-093-159/+143
| | | | llvm-svn: 274981
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