| Commit message (Collapse) | Author | Age | Files | Lines |
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the number of value bits, not the number of bits of allocation for in-memory
storage.
Make getTypeStoreSize and getTypeAllocSize work consistently for arrays and
vectors.
Fix several places in CodeGen which compute offsets into in-memory vectors
to use TargetData information.
This fixes PR1784.
llvm-svn: 97064
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more elegant.
llvm-svn: 97059
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llvm-svn: 97057
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llvm-svn: 97056
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the hopes of fixing PPC bootstrap.
llvm-svn: 97040
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necessary to swap the operands to handle NaN and negative zero properly.
Also, reintroduce logic for checking for NaN conditions when forming
SSE min and max instructions, fixed to take into consideration NaNs and
negative zeros. This allows forming min and max instructions in more
cases.
llvm-svn: 97025
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to adding them in a determinstic order (bottom up from
the root) based on the structure of the graph itself.
This updates tests for some random changes, interesting
bits: CodeGen/Blackfin/promote-logic.ll no longer crashes.
I have no idea why, but that's good right?
CodeGen/X86/2009-07-16-LoadFoldingBug.ll also fails, but
now compiles to have one fewer constant pool entry, making
the expected load that was being folded disappear. Since it
is an unreduced mass of gnast, I just removed it.
This fixes PR6370
llvm-svn: 97023
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llvm-svn: 97019
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llvm-svn: 97011
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creating a new node then replacing uses.
llvm-svn: 97000
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llvm-svn: 96995
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Previously, LiveIntervalAnalysis would infer phi joins by looking for multiply
defined registers. That doesn't work if the phi join is implicitly defined in
all but one of the predecessors.
llvm-svn: 96994
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no id's would cause early exit allowing IsLegalToFold to return true
instead of false, producing a cyclic dag.
This was striking the new isel because it isn't using SelectNodeTo yet,
which theoretically is just an optimization.
llvm-svn: 96972
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llvm-svn: 96971
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segment.
llvm-svn: 96967
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llvm-svn: 96956
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llvm-svn: 96837
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126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.
llvm-svn: 96822
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llvm-svn: 96779
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for ages (we emitted a reference to a stub, but no stub was emitted). The code inside x86-32/macho target objfile lowering should actually be the generic one - move it there.
This (I really, really hope) should fix EH issues on ppc/darwin
and arm/darwin.
llvm-svn: 96755
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This changes the stack overflow in PR6363 to an assertion failure.
llvm-svn: 96744
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the armv6 nightly tests.
llvm-svn: 96691
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Also, FileCheck'ize a test.
llvm-svn: 96686
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ARM and Thumb tests.
llvm-svn: 96680
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dragonegg self-host build. I reverted 96640 in order to revert
96556 (96640 goes on top of 96556), but it also looks like with
both of them applied the breakage happens even earlier. The
symptom of the 96556 miscompile is the following crash:
llvm[3]: Compiling AlphaISelLowering.cpp for Release build
cc1plus: /home/duncan/tmp/tmp/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:4982: void llvm::SelectionDAG::ReplaceAllUsesWith(llvm::SDNode*, llvm::SDNode*, llvm::SelectionDAG::DAGUpdateListener*): Assertion `(!From->hasAnyUseOfValue(i) || From->getValueType(i) == To->getValueType(i)) && "Cannot use this version of ReplaceAllUsesWith!"' failed.
Stack dump:
0. Running pass 'X86 DAG->DAG Instruction Selection' on function '@_ZN4llvm19AlphaTargetLowering14LowerOperationENS_7SDValueERNS_12SelectionDAGE'
g++: Internal error: Aborted (program cc1plus)
This occurs when building LLVM using LLVM built by LLVM (via
dragonegg). Probably LLVM has miscompiled itself, though it
may have miscompiled GCC and/or dragonegg itself: at this point
of the self-host build, all of GCC, LLVM and dragonegg were built
using LLVM. Unfortunately this kind of thing is extremely hard
to debug, and while I did rummage around a bit I didn't find any
smoking guns, aka obviously miscompiled code.
Found by bisection.
r96556 | evancheng | 2010-02-18 03:13:50 +0100 (Thu, 18 Feb 2010) | 5 lines
Some dag combiner goodness:
Transform br (xor (x, y)) -> br (x != y)
Transform br (xor (xor (x,y), 1)) -> br (x == y)
Also normalize (and (X, 1) == / != 1 -> (and (X, 1)) != / == 0 to match to "test on x86" and "tst on arm"
r96640 | evancheng | 2010-02-19 01:34:39 +0100 (Fri, 19 Feb 2010) | 16 lines
Transform (xor (setcc), (setcc)) == / != 1 to
(xor (setcc), (setcc)) != / == 1.
e.g. On x86_64
%0 = icmp eq i32 %x, 0
%1 = icmp eq i32 %y, 0
%2 = xor i1 %1, %0
br i1 %2, label %bb, label %return
=>
testl %edi, %edi
sete %al
testl %esi, %esi
sete %cl
cmpb %al, %cl
je LBB1_2
llvm-svn: 96672
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(xor (setcc), (setcc)) != / == 1.
e.g. On x86_64
%0 = icmp eq i32 %x, 0
%1 = icmp eq i32 %y, 0
%2 = xor i1 %1, %0
br i1 %2, label %bb, label %return
=>
testl %edi, %edi
sete %al
testl %esi, %esi
sete %cl
cmpb %al, %cl
je LBB1_2
llvm-svn: 96640
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This hopefulyl should unbreak EH on PPC/Darwin.
llvm-svn: 96637
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for ARM to just check if a function has a FP to determine if it's safe
to simplify the stack adjustment pseudo ops prior to eliminating frame
indices. Allow targets to override the default behavior and does so for ARM
and Thumb2.
llvm-svn: 96634
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Moderate the weight given to very small intervals.
The spill weight given to new intervals created when spilling was not
normalized in the same way as the original spill weights calculated by
CalcSpillWeights. That meant that restored registers would tend to hang around
because they had a much higher spill weight that unspilled registers.
This improves the runtime of a few tests by up to 10%, and there are no
significant regressions.
llvm-svn: 96613
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checking whether AnalyzeBranch disagrees with the CFG
directly, rather than looking for EH_LABEL instructions.
EH_LABEL instructions aren't always at the end of the
block, due to FP_REG_KILL and other things. This fixes
an infinite loop compiling MultiSource/Benchmarks/Bullet.
llvm-svn: 96611
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Russell Wallace.
llvm-svn: 96580
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out by Russell Wallace.
llvm-svn: 96579
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Transform br (xor (x, y)) -> br (x != y)
Transform br (xor (xor (x,y), 1)) -> br (x == y)
Also normalize (and (X, 1) == / != 1 -> (and (X, 1)) != / == 0 to match to "test on x86" and "tst on arm"
llvm-svn: 96556
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CSE'd or otherwise combined with temporal MemSDNodes.
llvm-svn: 96505
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llvm-svn: 96496
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and add a sparc implementation that knows about delay slots. Patch by
Nathan Keynes!
llvm-svn: 96492
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tblgen splatted code into the implementation.
llvm-svn: 96460
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live-in sets or run the rewriter.
llvm-svn: 96450
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existing scope end marker, if any. Scope must begin before it ends and nested inlined scope do not truncate surrounding scope.
llvm-svn: 96445
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and T->isPointerTy(). Convert most instances of the first form to the second form.
Requested by Chris.
llvm-svn: 96344
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elimination. Before a DBG_VALUE could affect codegen.
The solution here is imperfect and not final.
llvm-svn: 96318
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at older buildbot messages, I see the failure predates
this patch.
llvm-svn: 96307
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but it's harder to believe it's the other candidate,
so reverting. Temporarily I hope.
llvm-svn: 96303
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llvm-svn: 96295
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llvm-svn: 96294
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llvm-svn: 96292
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llvm-svn: 96290
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llvm-svn: 96288
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early beginning! The "z" CIE augmentation mark indicates that there is an extra word containing the size of augmentation section. However, even for frames w/o any augmentation data we emitted size uleb! (this is the case of "unwinding through C code"). Thus frame moves information was emitterd completely wrong.
llvm-svn: 96287
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Personality / FDE / LSDA / TType encoding depending on target / options (e.g. code model / relocation model) - MCIzation of Dwarf EH printer to use encoding information - Stub generation for ELF target (needed for indirect references) - Some other small changes here and there
llvm-svn: 96285
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