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* Add register mask support to ScheduleDAGRRList.Jakob Stoklund Olesen2012-02-131-11/+49
| | | | | | | | | The scheduler will sometimes check the implicit-def list on instructions to properly handle pre-colored DAG edges. Also check any register mask operands for physreg clobbers. llvm-svn: 150428
* LiveIntervalAnalysis does not depend on MachineLoopInfo.Andrew Trick2012-02-131-4/+2
| | | | llvm-svn: 150411
* Check regmask interference for -join-physregs.Jakob Stoklund Olesen2012-02-131-0/+8
| | | | llvm-svn: 150404
* Fix a bug in DAGCombine for the optimization of BUILD_VECTOR. We cant ↵Nadav Rotem2012-02-131-2/+6
| | | | | | generate a shuffle node from two vectors of different types. llvm-svn: 150383
* This patch addresses the problem of poor code generation for the zextNadav Rotem2012-02-121-14/+29
| | | | | | | | | | | | | | | | | | | v8i8 -> v8i32 on AVX machines. The codegen often scalarizes ANY_EXTEND nodes. The DAGCombiner has two optimizations that can mitigate the problem. First, if all of the operands of a BUILD_VECTOR node are extracted from an ZEXT/ANYEXT nodes, then it is possible to create a new simplified BUILD_VECTOR which uses UNDEFS/ZERO values to eliminate the scalar ZEXT/ANYEXT nodes. Second, another dag combine optimization lowers BUILD_VECTOR into a shuffle vector instruction. In the case of zext v8i8->v8i32 on AVX, a value in an XMM register is to be shuffled into a wide YMM register. This patch modifes the second optimization and allows the creation of shuffle vectors even when the newly generated vector and the original vector from which we extract the values are of different types. llvm-svn: 150340
* Add support for implicit TLS model used with MS VC runtime.Anton Korobeynikov2012-02-111-1/+10
| | | | | | Patch by Kai Nacke! llvm-svn: 150307
* Add TargetPassConfig hooks for scheduling/bundling.Andrew Trick2012-02-111-3/+41
| | | | | | | | | In case the MachineScheduling pass I'm working on doesn't work well for another target, they can completely override it. This also adds a hook immediately after the RegAlloc pass to cleanup immediately after vregs go away. We may want to fold it into the postRA hook later. llvm-svn: 150298
* Allow Post-RA LICM to hoist reserved register reads.Jakob Stoklund Olesen2012-02-111-0/+11
| | | | | | | | When using register masks, registers like %rip are clobbered by the register mask. LICM should still be able to hoist instructions reading %rip from a loop containing calls. llvm-svn: 150288
* Handle register masks in local live range splitting.Jakob Stoklund Olesen2012-02-111-0/+25
| | | | | | | Again the goal is to produce identical assembly with register mask operands enabled. llvm-svn: 150287
* Don't read PreRegAlloc before it is initialized.Jakob Stoklund Olesen2012-02-111-6/+6
| | | | llvm-svn: 150286
* Add a static MachineOperand::clobbersPhysReg().Jakob Stoklund Olesen2012-02-101-7/+2
| | | | | | | | It can be necessary to detach a register mask pointer from its MachineOperand. This method is convenient for checking clobbered physregs on a detached bitmask pointer. llvm-svn: 150261
* Add register mask support to InterferenceCache.Jakob Stoklund Olesen2012-02-103-5/+42
| | | | | | | | | | | | | | | | This makes global live range splitting behave identically with and without register mask operands. This is not necessarily the best way of using register masks for live range splitting. It would be more efficient to first split global live ranges around calls (i.e., register masks), and reserve the fine grained per-physreg interference guidance for global live ranges that do not cross calls. For now the goal is to produce identical assembly when enabling register masks. llvm-svn: 150259
* Remove unused variable.Jakob Stoklund Olesen2012-02-101-2/+1
| | | | llvm-svn: 150258
* Put instruction names into an indexed string table on the side, removing a ↵Benjamin Kramer2012-02-102-2/+5
| | | | | | | | | pointer from MCInstrDesc. Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64. llvm-svn: 150245
* comment grammarAndrew Trick2012-02-101-1/+1
| | | | llvm-svn: 150233
* RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick2012-02-1012-101/+144
| | | | | | | | | | | | | | | | Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. llvm-svn: 150226
* whitespaceAndrew Trick2012-02-101-11/+11
| | | | llvm-svn: 150225
* Remove unused 'isAlias' parameter.Lang Hames2012-02-101-8/+3
| | | | llvm-svn: 150224
* Constrain the regmask search space for local live ranges.Jakob Stoklund Olesen2012-02-101-3/+13
| | | | | | | When checking a local live range for interference, restrict the binary search to the single block. llvm-svn: 150220
* Cache basic block boundaries for faster RegMaskSlots access.Jakob Stoklund Olesen2012-02-101-0/+9
| | | | | | | Provide API to get a list of register mask slots and bits in a basic block. llvm-svn: 150219
* Optimize LiveIntervals::intervalIsInOneMBB().Jakob Stoklund Olesen2012-02-101-17/+22
| | | | | | | | No looping and binary searches necessary. Return a pointer to the containing block instead of just a bool. llvm-svn: 150218
* Cache iterators. Some of these are expensive to create.Benjamin Kramer2012-02-101-14/+16
| | | | llvm-svn: 150214
* Add register mask support to RAGreedy.Jakob Stoklund Olesen2012-02-091-2/+25
| | | | | | | | This only adds the interference checks required for correctness. We still need to take advantage of register masks for the interference driven live range splitting. llvm-svn: 150191
* Preserve physreg kills in MachineBasicBlock::SplitCriticalEdge.Lang Hames2012-02-091-4/+7
| | | | | | | Failure to preserve kills was causing LiveIntervals to miss some EFLAGS live ranges. Unfortunately I've been unable to reduce a good test case yet. llvm-svn: 150152
* Fix kill flags when moving instructions using LiveIntervals::moveInstr(...).Lang Hames2012-02-091-6/+23
| | | | llvm-svn: 150150
* Remove assertion. Not all use operands are reads.Lang Hames2012-02-091-3/+0
| | | | llvm-svn: 150149
* Improve TargetPassConfig. No intended functionality.Andrew Trick2012-02-091-98/+149
| | | | | | | Split CodeGen into stages. Distinguish between optimization and correctness. llvm-svn: 150122
* commentAndrew Trick2012-02-091-1/+1
| | | | llvm-svn: 150121
* Erase dead copies that are clobbered by a call.Jakob Stoklund Olesen2012-02-091-5/+17
| | | | | | This does make a difference, at least when using RABasic. llvm-svn: 150118
* Never delete instructions that define reserved registers.Jakob Stoklund Olesen2012-02-091-6/+10
| | | | | | | | | | | I think this was already the intention, but DeadMachineInstructionElim was accidentally tracking the liveness of reserved registers. Now, instructions with reserved defs are never deleted. This prevents the call stack adjustment instructions from getting deleted when enabling register masks. llvm-svn: 150116
* Handle register masks in MachineCopyPropagation.Jakob Stoklund Olesen2012-02-081-0/+17
| | | | | | | | For simplicity, treat calls with register masks as basic block boundaries. This means we can't copy propagate callee-saved registers across calls, but I don't think that is a big deal. llvm-svn: 150108
* Codegen pass definition cleanup. No functionality.Andrew Trick2012-02-0822-157/+86
| | | | | | | | | | | | | Moving toward a uniform style of pass definition to allow easier target configuration. Globally declare Pass ID. Globally declare pass initializer. Use INITIALIZE_PASS consistently. Add a call to the initializer from CodeGen.cpp. Remove redundant "createPass" functions and "getPassName" methods. While cleaning up declarations, cleaned up comments (sorry for large diff). llvm-svn: 150100
* Move pass configuration out of pass constructors: MachineLICM.Andrew Trick2012-02-082-5/+6
| | | | llvm-svn: 150099
* whitespaceAndrew Trick2012-02-081-11/+11
| | | | llvm-svn: 150098
* Move pass configuration out of pass constructors: StackSlotColoring.Andrew Trick2012-02-082-3/+3
| | | | llvm-svn: 150097
* Move pass configuration out of pass constructors: PostRAScheduler.Andrew Trick2012-02-082-7/+9
| | | | llvm-svn: 150096
* Move pass configuration out of pass constructors: BranchFolderPassAndrew Trick2012-02-083-13/+20
| | | | llvm-svn: 150095
* whitespaceAndrew Trick2012-02-088-80/+80
| | | | llvm-svn: 150094
* Added TargetPassConfig::setOptAndrew Trick2012-02-082-1/+12
| | | | llvm-svn: 150093
* Added Pass::createPass(ID) to handle pass configuration by IDAndrew Trick2012-02-081-2/+6
| | | | llvm-svn: 150092
* Move pass configuration out of pass constructors: TailDuplicate::PreRegAllocAndrew Trick2012-02-082-8/+9
| | | | llvm-svn: 150091
* Add Register mask support to RABasic.Jakob Stoklund Olesen2012-02-081-0/+14
| | | | | | | When a virtual register is live across a call, limit the search space to call-preserved registers. llvm-svn: 150081
* Keep track of register masks in LiveIntervalAnalysis.Jakob Stoklund Olesen2012-02-081-0/+62
| | | | | | | | | | | | | Build an ordered vector of register mask operands (i.e., calls) when computing live intervals. Provide a checkRegMaskInterference() function that computes a bit mask of usable registers for a live range. This is a quick way of determining of a live range crosses any calls, and restricting it to the callee saved registers if it does. Previously, we had to discover call clobbers for each candidate register independently. llvm-svn: 150077
* Added MachineInstr::isBundled() to check if an instruction is part of a bundle.Andrew Trick2012-02-082-1/+11
| | | | llvm-svn: 150044
* misched: bug in debug output.Andrew Trick2012-02-081-2/+4
| | | | llvm-svn: 150043
* stale commentAndrew Trick2012-02-081-2/+0
| | | | llvm-svn: 150041
* Remove tabs.Devang Patel2012-02-071-17/+17
| | | | llvm-svn: 150012
* Expose TargetPassConfig to PEI PassAndrew Trick2012-02-062-0/+2
| | | | llvm-svn: 149927
* Add TargetPassConfig to the PassManager for use inside passesAndrew Trick2012-02-061-2/+2
| | | | llvm-svn: 149926
* Don't explicitly renumber slot indices.Jakob Stoklund Olesen2012-02-061-2/+0
| | | | | | We have automatic local renumbering now. llvm-svn: 149920
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