summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
...
* Eliminate additional redundant copies of Triple objects. NFC.Daniel Sanders2015-06-242-2/+2
| | | | | | | | Subscribers: rafael, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10654 llvm-svn: 240540
* Fix instruction scheduling live register trackingPawel Bylica2015-06-241-8/+17
| | | | | | | | | | | | | | | | | | | Summary: This patch fixes PR23405 (https://llvm.org/bugs/show_bug.cgi?id=23405). During a node unscheduling an entry in LiveRegGens can be replaced with a new value. That corrupts the live reg tracking and LiveReg* structure is not cleared as should be during unscheduling. Problematic condition that enforces Gen replacement is `I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight()`. This condition should be checked only if LiveRegGen was set in current node unscheduling. Test Plan: Regression test included. Reviewers: hfinkel, atrick Reviewed By: atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9993 llvm-svn: 240538
* MILexer.cpp: Try to fix a warning. [-Wsign-compare]NAKAMURA Takumi2015-06-241-1/+1
| | | | llvm-svn: 240525
* MIR Serialization: Serialize immediate machine operands.Alex Lorenz2015-06-234-2/+41
| | | | | | | | Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10573 llvm-svn: 240481
* MIR Parser: Use correct source locations for machine instruction diagnostics.Alex Lorenz2015-06-231-2/+23
| | | | | | | | | | | | This commit translates the source locations for MIParser diagnostics from the locations in the machine instruction string to the locations in the MIR file. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10574 llvm-svn: 240474
* Revert "[FaultMaps] Move FaultMapParser to Object/"Sanjoy Das2015-06-231-0/+36
| | | | | | | This reverts commit r240364 (git c49542e5bb186). The issue r240364 was trying to fix was fixed independently in r240362. llvm-svn: 240448
* MIR Serialization: Serialize physical register machine operands.Alex Lorenz2015-06-234-4/+213
| | | | | | | | | | | This commit introduces functionality that's used to serialize machine operands. Only the physical register operands are serialized by this commit. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10525 llvm-svn: 240425
* [BranchFolding] Document why replacing HashMachineInstr with hash_code ↵Benjamin Kramer2015-06-231-1/+3
| | | | | | doesn't work llvm-svn: 240415
* [MachineBasicBlock] Add getFirstNonDebugInstr to complement getLastNonDebugInstrBenjamin Kramer2015-06-234-70/+30
| | | | | | Use it in CodeGen where applicable. No functionality change intended. llvm-svn: 240414
* [MachineBasicBlock] Use the const_cast(this) trick to reduce duplicationBenjamin Kramer2015-06-231-25/+0
| | | | | | NFC. llvm-svn: 240413
* Simplify the Mangler interface now that DataLayout is mandatory.Rafael Espindola2015-06-232-5/+4
| | | | | | | We only need to pass in a DataLayout when mangling a raw string, not when constructing the mangler. llvm-svn: 240405
* Use MCSymbols for FastISel.Rafael Espindola2015-06-231-1/+20
| | | | | | | | | | | The summary is that it moves the mangling earlier and replaces a few calls to .addExternalSymbol with addSym. I originally wanted to replace all the uses of addExternalSymbol with addSym, but noticed it was a lot of work and doesn't need to be done all at once. llvm-svn: 240395
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-2369-86/+86
| | | | | | Apparently, the style needs to be agreed upon first. llvm-svn: 240390
* [FaultMaps] Move FaultMapParser to Object/Sanjoy Das2015-06-231-36/+0
| | | | | | | | | | | | | | | | | | Summary: That way llvm-objdump can rely on it without adding an extra dependency on CodeGen. This change duplicates the FaultKind enum and the code that serializes it to a string. I could not figure out a way to get around this without adding a new dependency to Object Reviewers: rafael, ab Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10619 llvm-svn: 240364
* [x86] generalize reassociation optimization in machine combiner to 2 ↵Sanjay Patel2015-06-231-18/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instructions Currently ( D10321, http://reviews.llvm.org/rL239486 ), we can use the machine combiner pass to reassociate the following sequence to reduce the critical path: A = ? op ? B = A op X C = B op Y --> A = ? op ? B = X op Y C = A op B 'op' is currently limited to x86 AVX scalar FP adds (with fast-math on), but in theory, it could be any associative math/logic op (see TODO in code comment). This patch generalizes the pattern match to ignore the instruction that defines 'A'. So instead of a sequence of 3 adds, we now only need to find 2 dependent adds and decide if it's worth reassociating them. This generalization has a compile-time cost because we can now match more instruction sequences and we rely more heavily on the machine combiner to discard sequences where reassociation doesn't improve the critical path. For example, in the new test case: A = M div N B = A add X C = B add Y We'll match 2 reassociation patterns, but this transform doesn't reduce the critical path: A = M div N B = A add Y C = B add X We need the combiner to reject that pattern but select this: A = M div N B = X add Y C = B add A Differential Revision: http://reviews.llvm.org/D10460 llvm-svn: 240361
* Revert r240291: causes problems in self-hosted builds.Pawel Bylica2015-06-221-1/+1
| | | | llvm-svn: 240343
* MIR Serialization: Introduce a lexer for machine instructions.Alex Lorenz2015-06-224-11/+193
| | | | | | | | | | | | This commit adds a function that tokenizes the string containing the machine instruction. This commit also adds a struct called 'MIToken' which is used to represent the lexer's tokens. Reviewers: Sean Silva Differential Revision: http://reviews.llvm.org/D10521 llvm-svn: 240323
* Fix MSVC build.Sanjoy Das2015-06-221-4/+3
| | | | | | | | I had some unnecessary `typename`s left in after addressing review. This compiled successfully with clang++ but MSVC reported an error. Fix the build error by removing the redundant `typename`s. llvm-svn: 240307
* [FaultMaps] Add a parser for the __llvm__faultmaps section.Sanjoy Das2015-06-221-0/+37
| | | | | | | | | | | | | | | Summary: The parser is exercised by llvm-objdump using -print-fault-maps. As is probably obvious, the code itself was "heavily inspired" by http://reviews.llvm.org/D10434. Reviewers: reames, atrick, JosephTremoulet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10491 llvm-svn: 240304
* Avoid a Symbol -> Name -> Symbol conversion.Rafael Espindola2015-06-226-6/+24
| | | | | | | | | | | | | | Before this we were producing a TargetExternalSymbol from a MCSymbol. That meant extracting the symbol name and fetching the symbol again down the pipeline. This patch adds a DAG.getMCSymbol that lets the MCSymbol pass unchanged on the DAG. Doing so removes the need for MO_NOPREFIX and fixes the root cause of pr23900, allowing r240130 to be committed again. llvm-svn: 240300
* MIR Serialization: Serialize machine instruction names.Alex Lorenz2015-06-225-3/+185
| | | | | | | | | | | | | | | | This commit implements initial machine instruction serialization. It serializes machine instruction names. The instructions are represented using a YAML sequence of string literals and are a part of machine basic block YAML mapping. This commit introduces a class called 'MIParser' which will be used to parse the machine instructions and operands. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10481 llvm-svn: 240295
* Fix shl folding in DAG combiner.Pawel Bylica2015-06-221-1/+1
| | | | | | | | | | | | | | | | Summary: The code responsible for shl folding in the DAGCombiner was assuming incorrectly that all constants are less than 64 bits. This patch simply changes the way values are compared. Test Plan: A regression test included. Reviewers: andreadb Reviewed By: andreadb Subscribers: andreadb, test, llvm-commits Differential Revision: http://reviews.llvm.org/D10602 llvm-svn: 240291
* [PM/AA] Hoist the AliasResult enum out of the AliasAnalysis class.Chandler Carruth2015-06-222-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This will allow classes to implement the AA interface without deriving from the class or referencing an internal enum of some other class as their return types. Also, to a pretty fundamental extent, concepts such as 'NoAlias', 'MayAlias', and 'MustAlias' are first class concepts in LLVM and we aren't saving anything by scoping them heavily. My mild preference would have been to use a scoped enum, but that feature is essentially completely broken AFAICT. I'm extremely disappointed. For example, we cannot through any reasonable[1] means construct an enum class (or analog) which has scoped names but converts to a boolean in order to test for the possibility of aliasing. [1]: Richard Smith came up with a "solution", but it requires class templates, and lots of boilerplate setting up the enumeration multiple times. Something like Boost.PP could potentially bundle this up, but even that would be quite painful and it doesn't seem realistically worth it. The enum class solution would probably work without the need for a bool conversion. Differential Revision: http://reviews.llvm.org/D10495 llvm-svn: 240255
* AsmPrinter: Don't emit empty .debug_loc entriesDuncan P. N. Exon Smith2015-06-215-14/+122
| | | | | | | | | | | If we don't know how to represent a .debug_loc entry, skip the entry entirely rather than emitting an empty one. Similarly, if a .debug_loc list has no entries, don't create the list. We still want to create the variables, just in an optimized-out form that doesn't have a DW_AT_location. llvm-svn: 240244
* AsmPrinter: Rewrite initialization of DbgVariable, NFCDuncan P. N. Exon Smith2015-06-213-64/+85
| | | | | | | | | | | | | | | | | | | | | | | There are three types of `DbgVariable`: - alloca variables, created based on the MMI table, - register variables, created based on DBG_VALUE instructions, and - optimized-out variables. This commit reconfigures `DbgVariable` to make it easier to tell which kind we have, and make initialization a little clearer. For MMI/alloca variables, `FrameIndex.size()` must always equal `Expr.size()`, and there shouldn't be an `MInsn`. For register variables (with a `MInsn`), `FrameIndex` must be empty, and `Expr` should have 0 or 1 element depending on whether it has a complex expression (registers with multiple locations use `DebugLocListIndex`). Optimized-out variables shouldn't have any of these fields. Moreover, this separates DBG_VALUE initialization until after the variable is created, simplifying logic in a future commit that changes `collectVariableInfo()` to stop creating empty .debug_loc entries/lists. llvm-svn: 240243
* Switch lowering: add heuristic for filling leaf nodes in the weight-balanced ↵Hans Wennborg2015-06-202-0/+59
| | | | | | | | | | | | | | | | | | binary search tree Sparse switches with profile info are lowered as weight-balanced BSTs. For example, if the node weights are {1,1,1,1,1,1000}, the right-most node would end up in a tree by itself, bringing it closer to the top. However, a leaf in this BST can contain up to 3 cases, and having a single case in a leaf node as in the example means the tree might become unnecessarily high. This patch adds a heauristic to the pivot selection algorithm that moves more cases into leaf nodes unless that would lower their rank. It still doesn't yield the optimal tree in every case, but I believe it's conservatibely correct. llvm-svn: 240224
* Reformat.NAKAMURA Takumi2015-06-201-7/+12
| | | | llvm-svn: 240213
* Revert r240040, "[BranchFolding] Replace custom MachineInstr with ↵NAKAMURA Takumi2015-06-201-6/+46
| | | | | | | | MachineInstrExpressionTrait" It caused different emission between stage2 and stage3. Investigating. llvm-svn: 240212
* [Statepoint] Remove unnecessary argument from Statepoint::getRelocatesSanjoy Das2015-06-201-4/+2
| | | | | | NFC. llvm-svn: 240198
* name change: hasPattern() -> getMachineCombinerPatterns() ; NFCSanjay Patel2015-06-191-5/+5
| | | | | | | This was suggested as part of D10460, but it's independent of any functional change. llvm-svn: 240192
* MIR Parser: report an error when a basic block isn't found.Alex Lorenz2015-06-191-1/+3
| | | | | | | This commit reports an error when the MIR parser can't find a basic block with the machine basic block's name. llvm-svn: 240174
* MIR Serialization: Serialize the list of machine basic blocks with simple ↵Alex Lorenz2015-06-192-0/+50
| | | | | | | | | | | | | | attributes. This commit implements the initial serialization of machine basic blocks in a machine function. Only the simple, scalar MBB attributes are serialized. The reference to LLVM IR's basic block is preserved when that basic block has a name. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10465 llvm-svn: 240145
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-1970-87/+87
| | | | | | | | | | | | | The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! llvm-svn: 240137
* Fix "the the" in comments.Eric Christopher2015-06-194-5/+5
| | | | llvm-svn: 240112
* Avoid redundant select node in early if-conversion passYi Jiang2015-06-181-4/+13
| | | | llvm-svn: 240072
* Switch lowering: enable whole-switch jump tables at -O0.Hans Wennborg2015-06-181-15/+31
| | | | | | | | To same compile time, the analysis to find dense case-clusters in switches is not done at -O0. However, when the whole switch is dense enough, it is easy to turn it into a jump table, resulting in much faster code with no extra effort. llvm-svn: 240071
* [BranchFolding] Replace custom MachineInstr with MachineInstrExpressionTraitBenjamin Kramer2015-06-181-46/+6
| | | | | | | While the hash functions are subtly different it shouldn't have an impact. Instructions are checked with isIdenticalTo later. llvm-svn: 240040
* [CodeGen] Don't emit a random reference to the personality functionDavid Majnemer2015-06-181-4/+0
| | | | | | This should fix issues we've been seeing with Darwin. llvm-svn: 240036
* fix typo; NFCSanjay Patel2015-06-181-4/+4
| | | | llvm-svn: 240022
* [AsmPrinter] Make isRepeatedByteSequence smarter about odd integer typesBenjamin Kramer2015-06-171-26/+16
| | | | | | | | | | | | - zext the value to alloc size first, then check if the value repeats with zero padding included. If so we can still emit a .space - Do the checking with APInt.isSplat(8), which handles non-pow2 types - Also handle large constants (bit width > 64) - In a ConstantArray all elements have the same type, so it's sufficient to check the first constant recursively and then just compare if all following constants are the same by pointer compare llvm-svn: 239977
* remove unnecessary casts; NFCSanjay Patel2015-06-171-4/+2
| | | | llvm-svn: 239942
* Move the personality function from LandingPadInst to FunctionDavid Majnemer2015-06-177-30/+36
| | | | | | | | | | | | | | | | | | | The personality routine currently lives in the LandingPadInst. This isn't desirable because: - All LandingPadInsts in the same function must have the same personality routine. This means that each LandingPadInst beyond the first has an operand which produces no additional information. - There is ongoing work to introduce EH IR constructs other than LandingPadInst. Moving the personality routine off of any one particular Instruction and onto the parent function seems a lot better than have N different places a personality function can sneak onto an exceptional function. Differential Revision: http://reviews.llvm.org/D10429 llvm-svn: 239940
* [CodeGenPrepare] Generalize inserted set from truncs to any inst.Ahmed Bougacha2015-06-171-21/+28
| | | | | | | | | It's been used before to avoid infinite loops caused by separate CGP optimizations undoing one another. We found one more such issue caused by r238054. To avoid it, generalize the "InsertedTruncs" set to any inst, and use it to avoid touching those again. llvm-svn: 239938
* fix typos in comments; NFCSanjay Patel2015-06-171-2/+2
| | | | llvm-svn: 239916
* [PM/AA] Remove the Location typedef from the AliasAnalysis class nowChandler Carruth2015-06-174-23/+18
| | | | | | | | | | | | that it is its own entity in the form of MemoryLocation, and update all the callers. This is an entirely mechanical change. References to "Location" within AA subclases become "MemoryLocation", and elsewhere "AliasAnalysis::Location" becomes "MemoryLocation". Hope that helps out-of-tree folks update. llvm-svn: 239885
* Rename and improve emitSectionOffset.Rafael Espindola2015-06-164-29/+19
| | | | | | | | | | | | | | | | | | | | | | | Different object formats represent references from dwarf in different ways. ELF uses a relocation to the referenced point (except for .dwo) and COFF/MachO use the offset of the referenced point inside its section. This patch renames emitSectionOffset because * It doesn't produce an offset on ELF. * It changes behavior depending on how DWARF is represented, so adding dwarf to its name is probably a good thing. The patch also adds an option to force the use of offsets.That avoids funny looking code like if (!UseOffsets) Asm->emitSectionOffset.... It was correct, but read as if the ! was inverted. llvm-svn: 239866
* rename variables; NFCSanjay Patel2015-06-161-13/+13
| | | | | | ...because I see 'StoreBW' and read it as 'store bandwidth' llvm-svn: 239850
* extract some code into a helper function for MergeConsecutiveStores(); NFCISanjay Patel2015-06-161-43/+57
| | | | llvm-svn: 239847
* VirtRegMap: Add undef flag when reading undefined subregisters.Matthias Braun2015-06-161-18/+63
| | | | | | | | | | | | | | | | | While completely undefined registers are easy to catch and get their <undef> flag early in ProcessImplicitDefs/RegisterCoalescer reading from a partially defined register where just the subreg happens to be undefined is harder to catch so we only add the undef flag in the virtual register rewriting step. No testcase as I cannot reproduce the problem on any of the in-tree targets at the moment. This fixes rdar://21387089 Differential Revision: http://reviews.llvm.org/D10470 llvm-svn: 239838
* TargetRegisterInfo: Make the concept of imprecise lane masks explicitMatthias Braun2015-06-161-1/+2
| | | | | | | | | | | | | | | | | | | | LaneMasks as given by getSubRegIndexLaneMask() have a limited number of of bits, so for targets with more than 31 disjunct subregister there may be cases where: getSubReg(Reg,A) does not overlap getSubReg(Reg,B) but we still have (getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B)) != 0. I had hoped to keep this an implementation detail of the tablegen but as my next commit shows we can avoid unnecessary imp-defs operands if we know that the lane masks in use are precise. This is in preparation to http://reviews.llvm.org/D10470. llvm-svn: 239837
OpenPOWER on IntegriCloud